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2003-2006 (17) 2007 (17) 2008 (19) 2009 (20) 2010 (27) 2011 (18) 2012 (31) 2013 (32) 2014 (77) 2015 (105) 2016 (86) 2017 (81) 2018 (122) 2019 (118) 2020 (94) 2021 (105) 2022 (100) 2023 (104) 2024 (18)
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Found 1191 publication records. Showing 1191 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
136Feng Wang 0004, Yuan Xie 0001, Kerry Bernstein, Yan Luo Dependability Analysis of Nano-scale FinFET circuits. Search on Bibsonomy ISVLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
118Jin Ouyang, Yuan Xie 0001 Power optimization for FinFET-based circuits using genetic algorithms. Search on Bibsonomy SoCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
118Zhiyu Liu, Sherif A. Tawfik, Volkan Kursun Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF static noise margin distribution, robust operation, active power, standby power distribution, double gate MOSFET, process variations, Cache memory
118Sherif A. Tawfik, Volkan Kursun Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
112Brian Swahn, Soha Hassoun Gate sizing: finFETs vs 32nm bulk MOSFETs. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF gate sizing, thermal modeling, FinFET
91Aarti Choudhary, Sandip Kundu A process variation tolerant self-compensating FinFET based sense amplifier design. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF sense amplifier, robustness, process -variation, yield, sram, finfet
91Tarun Sairam, Wei Zhao, Yu Cao 0001 Optimizing finfet technology for high-speed and low-power design. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF power, energy, variations, speed, threshold voltage, FinFET, noise margin
87Anish Muttreja, Niket Agarwal, Niraj K. Jha CMOS logic design with independent-gate FinFETs. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
84Prateek Mishra, Anish Muttreja, Niraj K. Jha Low-power FinFET circuit synthesis using multiple supply and threshold voltages. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Low-power, linear programming, synthesis, TCMS
84Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi Low power 8T SRAM using 32nm independent gate FinFET technology. Search on Bibsonomy SoCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
69Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF decoupled design, 8T, 6T, stacked devices, stability, yield, sram, double gate
66Seid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee High-speed low-power FinFET based domino logic. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
66Sherif A. Tawfik, Volkan Kursun Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
66Animesh Datta, Ashish Goel, R. T. Cakici, Hamid Mahmoodi, Dheepa Lekshmanan, Kaushik Roy 0001 Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
66Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King 0001, Borivoje Nikolic FinFET-based SRAM design. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF double gate transistors, low power, memory, SRAM
49Chenyue Ma, Bo Li, Lining Zhang, Jin He 0003, Xing Zhang 0002, Xinnan Lin, Mansun Chan A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
49Jie Gu 0003, John Keane 0001, Sachin S. Sapatnekar, Chris H. Kim Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
49Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction. Search on Bibsonomy PATMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
49Davide Ponton, Pierpaolo Palestri, David Esseni, Luca Selmi, Marc Tiebout, Bertrand Parvais, Gerhard Knoblinger Design of UWB LNA in 45nm CMOS technology: Planar bulk vs. FinFET. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
49Anish Muttreja, Prateek Mishra, Niraj K. Jha Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
49Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy 0001 Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
49Jung Hwan Choi, Jayathi Murthy, Kaushik Roy 0001 The effect of process variation on device temperature in FinFET circuits. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
49Aditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy 0001 Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
49Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy 0001 Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
49Saihua Lin, Rong Luo, Huazhong Yang, Hui Wang 0004 A 0.9V 10GHz 71µW Static D Flip-flop by using FinFET Devices. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
49Hari Ananthan, Aditya Bansal, Kaushik Roy 0001 FinFET SRAM - Device and Circuit Design Considerations. Search on Bibsonomy ISQED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
43Kiyoo Itoh 0001 Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF 0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
43Wei Zhao, Yu Cao 0001 Predictive technology model for nano-CMOS design exploration. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF early design exploration, process variations, predictive modeling, Technology scaling, FinFET
39Darsen D. Lu, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu Compact Modeling of Variation in FinFET SRAM Cells. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF multigate MOSFETs, variability, design for manufacturing, SRAM, design and test, FinFET, compact modeling
39Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj FinFET SRAM Design. Search on Bibsonomy VLSI Design The full citation details ... 2010 DBLP  DOI  BibTeX  RDF variability, SRAM, FinFET, Double gate
31Sherif A. Tawfik, Volkan Kursun Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
28Myoungsu Son, Juho Sung, Hyoung Won Baac, Changhwan Shin Comparative Study of Novel u-Shaped SOI FinFET Against Multiple-Fin Bulk/SOI FinFET. Search on Bibsonomy IEEE Access The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
28Ravindra Kumar Maurya, Vivek Kumar, Rajesh Saha, Brinda Bhowmick Effect of curie temperature on electrical parameters of NC-FinFET and digital switching application of NC-FinFET. Search on Bibsonomy Microelectron. J. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
28Divya Praneetha Ravipati, Rajesh Kedia, Victor M. van Santen, Jörg Henkel, Preeti Ranjan Panda, Hussam Amrouch FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
28Jin Hyo Park, Geon Kim, Dong Yeong Kim, Su Yeon Kim, Sunyong Yoo, Myoung Jin Lee S-TAT Leakage Current in Partial Isolation Type Saddle-FinFET (Pi-FinFET)s. Search on Bibsonomy IEEE Access The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
28Aniket Gupta, Nitanshu Chauhan, Om Prakash 0007, Hussam Amrouch Variability Effects in FinFET Transistors and Emerging NC-FinFET. Search on Bibsonomy ICICDT The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
28Ramin Rajaei, Yen-Kai Lin, Sayeef S. Salahuddin, Michael T. Niemier, Xiaobo Sharon Hu GC-eDRAM design using hybrid FinFET/NC-FinFET. Search on Bibsonomy ISLPED The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
28Chia-Ning Chang, Yin-Nien Chen, Po-Tsang Huang, Pin Su, Ching-Te Chuang Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations. Search on Bibsonomy ISCAS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
28Syed Samsuz Zaman, Pankaj Kumar, Manash Pratim Sarma, Ashok Ray, Gaurav Trivedi Design and Simulation of SF-FinFET and SD-FinFET and Their Performance in Analog, RF and Digital Applications. Search on Bibsonomy iNIS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
28Shushanik Karapetyan, Veit Kleeberger, Ulf Schlichtmann FinFET-based product performance: Modeling and evaluation of standard cells in FinFET technologies. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
28Sourindra Chaudhuri, Niraj K. Jha FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage. Search on Bibsonomy VLSID The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
28Chun-Yi Lee, Niraj K. Jha CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations. Search on Bibsonomy DAC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
25Vaidyanathan Subramanian, Abdelkarim Mercha, Bertrand Parvais, Morin Dehan, Guido Groeseneken, Willy M. C. Sansen, Stefaan Decoutere Identifying the Bottlenecks to the RF Performance of FinFETs. Search on Bibsonomy VLSI Design The full citation details ... 2010 DBLP  DOI  BibTeX  RDF multiple gate FET, multi-gate FET, RF, FinFET
25Yiming Li 0005, Chih-Hong Hwang, Shao-Ming Yu Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors. Search on Bibsonomy International Conference on Computational Science (4) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF computational statistics, SRAM, modeling and simulation, FinFET
25Hari Ananthan, Kaushik Roy 0001 A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF leakage distribution, multiple-gate, tri-gate, process variations, finFET, double-gate
17Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil Automated design and optimization of circuits in emerging technologies. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
17Abhisek Dixit, Anirban Bandhyopadhyay, Nadine Collaert, Kristin De Meyer, Malgorzata Jurczak Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
17Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi Creating an affordable 22nm node using design-lithography co-optimization. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF design technology co-optimization, templates, DFM, regular fabric
17ChenMing Hu BSIM - making the first international standard MOSFET model. Search on Bibsonomy Sci. China Ser. F Inf. Sci. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF BSIM, MOS, compact modeling
17Hamed F. Dadgour, Vivek De, Kaustav Banerjee Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
17Volkan Kursun, Sherif A. Tawfik, Zhiyu Liu Leakage-Aware Design of Nanometer SoC. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
17Changhyun Kim Future Memory Technology Trends and Challenges. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
17Abdelkarim Mercha Technology and architecture for deep submicron RF CMOS technology. Search on Bibsonomy SBCCI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
17Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri Design and CAD Challenges in sub-90nm CMOS Technologies. Search on Bibsonomy ICCAD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
14Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14Bo Zhang 0029, Anand Vasani, Ashutosh Sinha, Alireza Nilchi, Haitao Tong, Lakshmi P. Rao, Karapet Khanoyan, Hamid Hatamkhani, Xiaochen Yang, Xin Meng, Alexander Wong, Jun Kim, Ping Jing, Yehui Sun, Ali Nazemi, Dean Liu, Anthony Brewster, Jun Cao 0001, Afshin Momtaz A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14Jeongkyun Kim, Byungho Yook, Youngo Lee, Taemin Choi, Kyuwon Choi, Chanho Lee, Juchang Lee, Hyeongcheol Kim, Seok Yun, Changhoon Do, Minwoo Kwak, Mijoung Kim, Yunrong Li, Hoyoung Tang, Jaeyoung Kim, Inhak Lee, Dongwook Seo, Sangyeop Baeck A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14Sajjad Rostami Sani, Andy Gean Ye Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm. Search on Bibsonomy ACM Trans. Reconfigurable Technol. Syst. The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14Rinku Rani Das, Alex James 0001 Multi-Channel Step FinFET With Spacer Engineering. Search on Bibsonomy IEEE Access The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14Rinku Rani Das, Rajalekshmi TR, Alex James 0001 FinFET to GAA MBCFET: A Review and Insights. Search on Bibsonomy IEEE Access The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14Shams-Ul-Haq, Vijay Kumar Sharma Improved Stability for Robust and Low-Power SRAM Cell Using FinFET Technology. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14Parthiv Bhau, Vijay Savani Design and Analysis of Low-Voltage and Low-Power 19T FinFET-TGDI-Based Hybrid Full Adders. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14Prachuryya Subash Das, Deepjyoti Deb, Rupam Goswami, Santanu Sharma, Rajesh Saha Fin core dimensionality and corner effect in dual core gate-all-around FinFET. Search on Bibsonomy Microelectron. J. The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14Baojun Liu, Xiaokuo Yang, Jing Zhu Variations of single event transient induced by line edge roughness (LER) and temperature in FinFET. Search on Bibsonomy Microelectron. J. The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14Linfang Wang, Weizeng Li, Zhidao Zhou, Hanghang Gao, Zhi Li, Wang Ye, Hongyang Hu, Jing Liu, Jinshan Yue, Jianguo Yang, Qing Luo, Chunmeng Dou, Qi Liu, Ming Liu 34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process. Search on Bibsonomy ISSCC The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14Marco Cusmai, Noam Familia, Elad Kuperberg, Mohammad Nashash, Dovid Gottesman, Daljeet Kumar, Zvi Marcus, Yeshayahu Horwitz, Sagi Zalcman, Jihwan Kim, Sandipan Kundu, Ilia Radashkevich, Yoav Segal, Dror Lazar, Udi Virobnik, Mike Peng Li, Ariel Cohen 0001 7.2 A 224Gb/s sub pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET. Search on Bibsonomy ISSCC The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14Yi-Cheng Huang, Shang-Hsuan Liu, Hsu-Shun Chen, Hsin-Chang Feng, Chih-Feng Li, Chou-Ying Yang, Wei-Keng Chang, Chang-Feng Yang, Chun-Yu Wu, Yen-Cheng Lin, Tsung-Tse Yang, Chih-Yang Chang, Wen-Ting Chu, Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang 15.7 A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm2 Bit-Cell, a 3.2GB/S Read Throughput, a 10KCycle Write Endurance and a 10-Year Retention at 105°C. Search on Bibsonomy ISSCC The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14J. Q. Wang, A. Tan, A. Iyer, A. Fan, A. Farhoodfar, B. Alnabulsi, B. Smith, C. Loi, Cheng-Ru Ho, D. Cartina, Jamal Riani, J. Casanova, K. Raviprakash, L. Patra, L. Wang, M. Bachu, S. Ray, S. Chong, S. Dallaire, T. Nguyen, Tzu-Fan Wu, V. Giridharan, V. Gurumoorthy, X. Ding, Y. Yin, Z. Sun, S. Jantzi, L. Tse 7.1 A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET. Search on Bibsonomy ISSCC The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang 15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture. Search on Bibsonomy ISSCC The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14Dirk Pfaff, Muhammad Nummer, Noman Hai, Peter Xia, Kai Ge Yang, Mohammad-Mahdi Mohsenpour, Marc-Andre LaCroix, Babak Zamanlooy, Tom Eeckelaert, Dmitry Petrov, Mostafa Haroun, Carson Dick, Alif Zaman, Haitao Mei, Shahab Moazzeni, Tahseen Shakir, Carlos Carvalho, Howard Huang, Pratibha Kumari 0004, Ralph Mason, Fahmida Brishty, Ifrah Jaffri 7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS. Search on Bibsonomy ISSCC The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14R. L. Nguyen, A. Mellati, A. Fernandez, A. Iyer, A. Fan, Benjamín T. Reyes, Cindra Abidin, Claudio Nani, D. Albano, F. Ahmad, Fredy Solis, Gabriele Minoia, Geoff Hatcher, M. Bachu, Marco Garampazzi, Mohsen Hassanpourghadi, N. Fan, P. Prabha, S. Fan, S. Ho, T. Dusatko, Tzu-Fan Wu, W. Elsharkasy, Z. Sun, S. Jantzi, L. Tse 18.4 A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET. Search on Bibsonomy ISSCC The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
14Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Dan Lake, Brent R. Carlton A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Richard Dorrance, Deepak Dasalukunte, Hechen Wang, Renzhi Liu, Brent R. Carlton An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Yuanming Zhu, Tong Liu, Srujan Kumar Kaile, Shiva Kiran, Il-Min Yi, Ruida Liu, Julian Camilo Gomez Diaz, Sebastian Hoyos, Samuel Palermo A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Troy J. Beukema, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Yuanming Zhu, Julian Camilo Gomez Diaz, Srujan Kumar Kaile, Il-Min Yi, Tong Liu, Sebastian Hoyos, Samuel Palermo A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Abhishek Agrawal, Amy Whitcombe, Woorim Shin, Ritesh Bhat, Somnath Kundu, Peter Sagazio, Hariprasad Chandrakumar, Thomas William Brown, Brent R. Carlton, Christopher Dennis Hull, Steven Callender, Stefano Pellerano A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Nanditha Maragowdanahalli Shivalingaiah, Vijaya Prakash Anamanahalli Mariyappa Performance Analysis of FinFET-Based LVDS I/O Receiver Architecture. Search on Bibsonomy SN Comput. Sci. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Shelja Kaushal, Ashwani K. Rana Reliable and low power Negative Capacitance Junctionless FinFET based 6T SRAM cell. Search on Bibsonomy Integr. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Chua-Chin Wang, Lean Karlo S. Tolentino, Shao-Wei Lu, Oliver Lexter July A. Jose, Ralph Gerard B. Sangalang, Tzung-Je Lee, Pang-Yen Lou, Wei-Chih Chang A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process. Search on Bibsonomy Integr. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14D. Rebecca Florance, B. Prabhakar Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies. Search on Bibsonomy Integr. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Nehru Kandasamy, Nagarjuna Telagam, K. Chitra Design of novel low power architectures of 4:2, 5:2 compressors and 2-bit counter using 7 nm FinFET technology. Search on Bibsonomy J. Ambient Intell. Humaniz. Comput. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Netanel Shavit, Inbal Stanger, Ramiro Taco, Alexander Fish, Itamar Levi Programmable All-in-One 4×8-/2×16-/1×32-Bits Dual Mode Logic Multiplier in 16 nm FinFET With Semi-Automatic Flow. Search on Bibsonomy IEEE Access The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Mohammad Khaleqi Qaleh Jooq, Mostafa Rahimi Azghadi, Fereshteh Behbahani, Alaaddin Al-Shidaifat, Hanjung Song High-Performance and Energy-Efficient Leaky Integrate-and-Fire Neuron and Spike Timing-Dependent Plasticity Circuits in 7nm FinFET Technology. Search on Bibsonomy IEEE Access The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Divya Praneetha Ravipati, Victor M. van Santen, Sami Salamin, Hussam Amrouch, Preeti Ranjan Panda Performance and Energy Studies on NC-FinFET Cache-Based Systems With FN-McPAT. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Erfan Abbasian, Bahare Grailoo, Mahdieh Nayeri Design of a 10-nm FinFET 11 T Near-Threshold SRAM Cell for Low-Energy Internet-of-Things Applications. Search on Bibsonomy Circuits Syst. Signal Process. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Chua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tzung-Je Lee A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder. Search on Bibsonomy Circuits Syst. Signal Process. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Shivendra Singh Parihar, Victor M. van Santen, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Heng Xu, Jun Wang, Hang Xu, Yi Gu, Hao Zhu, Qing-Qing Sun, David Wei Zhang Impact Study of Layout-Dependent Effects Toward FinFET Combinational Standard Cell Optimization. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Gerson D. Andrade, Matheus Silva, Cínthia Schneider, Guilherme Paim, Sergio Bampi, Eduardo Costa 0001, Alexandra L. Zimpeck Robustness Analysis of 3-2 Adder Compressor Designed in 7-nm FinFET Technology. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Kyungmin Lee, Jaehong Jung, Seungjin Kim, Seunghyun Oh, Jongwoo Lee, Sung Min Park 0001 A 208-MHz, 0.75-mW Self-Calibrated Reference Frequency Quadrupler for a 2-GHz Fractional-N Ring-PLL in 4-nm FinFET CMOS. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14A. Venkatesan, P. T. Vanathi, M. Elangovan Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7 nm FINFET Technology for MIMO Applications. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14A. Venkatesan, P. T. Vanathi, M. Elangovan Erratum: Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7nm FINFET Technology for MIMO Applications. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Mohammad Khaleqi Qaleh Jooq, Fereshteh Behbahani, Mohammad Hossein Moaiyeri Ultra-efficient fully programmable membership function generator based on independent double-gate FinFET technology. Search on Bibsonomy Int. J. Circuit Theory Appl. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Milad Haghi Kashani, Hossein Shakiba, Ali Sheikholeslami An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process. Search on Bibsonomy IEEE Open J. Circuits Syst. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14K. Sarath Chandra, Kakarla Hari Kishore 0002 Design and Analysis of Low Power FinFET SRAM with Leakage Current Reduction Techniques. Search on Bibsonomy Wirel. Pers. Commun. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14T. Santosh Kumar, Suman Lata Tripathi Low Power and Suppressed Noise 6T, 7T SRAM Cell Using 18 nm FinFET. Search on Bibsonomy Wirel. Pers. Commun. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
14Freddy Forero, Víctor H. Champac, Michel Renovell B-open Defect: A Novel Defect Model in FinFET Technology. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
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