Search results for "gate-sizing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
135	Puneet Gupta 0001, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma	Eyecharts: constructive benchmarking of gate sizing heuristics.	DAC	2010	DBLP DOI BibTeX RDF	dynamic programming, benchmarking, gate sizing
128	Narender Hanchate, Nagarajan Ranganathan	Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Game theory, gate sizing, transmission lines, crosstalk noise, interconnect models, interconnect delay
115	Vishal Khandelwal, Ankur Srivastava 0001	Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation.	ISPD	2007	DBLP DOI BibTeX RDF	post-silicon tunability, variability, stochastic optimization, timing optimization, gate sizing
100	Debjit Sinha, Hai Zhou 0001, Chris C. N. Chu	Optimal gate sizing for coupling-noise reduction.	ISPD	2004	DBLP DOI BibTeX RDF	coupling-noise, gate-sizing, lattice theory, fixpoint
92	Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj	Post-route gate sizing for crosstalk noise reduction.	DAC	2003	DBLP DOI BibTeX RDF	crosstalk noise repair, gate sizing
92	Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru	An iterative gate sizing approach with accurate delay evaluation.	ICCAD	1995	DBLP DOI BibTeX RDF	delay evaluation, linear program, iteration, gate sizing
91	Vishal Khandelwal, Ankur Srivastava 0001	Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
88	Ashok K. Murugavel, N. Ranganathan	Gate Sizing and Buffer Insertion using Economic Models for Power Optimization.	VLSI Design	2004	DBLP DOI BibTeX RDF
83	Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang	Switching-activity driven gate sizing and Vth assignment for low power design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
83	Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn	Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization.	ICCAD	1995	DBLP DOI BibTeX RDF	acyclic pipelines, area-delay tradeoff, clock skew optimization, cycle-borrowing, logic design, combinational circuits, logic CAD, pipeline processing, circuit CAD, circuit optimisation, gate sizing, logic gates, pipelined circuits, timing specifications
80	Koustav Bhattacharya, Nagarajan Ranganathan	A linear programming formulation for security-aware gate sizing.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	dynamic power variance, linear programming., path balancing, differential power analysis, gate sizing
80	Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. Sapatnekar	Robust gate sizing by geometric programming.	DAC	2005	DBLP DOI BibTeX RDF	posynomial, uncertainty ellipsoid, optimization, gate sizing, geometric program
79	Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodrag Potkonjak, Majid Sarrafzadeh	General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
76	Hiran Tennakoon, Carl Sechen	Efficient and accurate gate sizing with piecewise convex delay models.	DAC	2005	DBLP DOI BibTeX RDF	piecewise convex, optimization, Lagrangian relaxation, gate sizing, delay modeling
74	Ashutosh Chakraborty, David Z. Pan	On stress aware active area sizing, gate sizing, and repeater insertion.	ISPD	2009	DBLP DOI BibTeX RDF	performance, buffer, sizing, stress, repeater
72	Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III	A novel approach for variation aware power minimization during gate sizing.	ISLPED	2006	DBLP DOI BibTeX RDF
72	Venkataraman Mahalingam, N. Ranganathan	A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection.	ISVLSI	2005	DBLP DOI BibTeX RDF
72	Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam	Variation-aware multimetric optimization during gate sizing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	optimization, delay, power, mathematical programming, Gate sizing, crosstalk noise
72	Zhanyuan Jiang, Weiping Shi	Circuit-wise buffer insertion and gate sizing algorithm with scalability.	DAC	2008	DBLP DOI BibTeX RDF	buffer insertion, gate sizing, interconnect synthesis
68	Narender Hanchate, Nagarajan Ranganathan	Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization.	ISQED	2006	DBLP DOI BibTeX RDF
68	Yifang Liu, Jiang Hu	A new algorithm for simultaneous gate sizing and threshold voltage assignment.	ISPD	2009	DBLP DOI BibTeX RDF	threshold voltage assignment, gate sizing
67	Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Majid Sarrafzadeh	Soft Error-Aware Power Optimization Using Gate Sizing.	PATMOS	2007	DBLP DOI BibTeX RDF
67	Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj	Postroute gate sizing for crosstalk noise reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
67	N. Ranganathan, Ashok K. Murugavel	A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization.	ICCD	2003	DBLP DOI BibTeX RDF
67	Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj	Post-Route Gate Sizing for Crosstalk Noise Reduction.	ISQED	2003	DBLP DOI BibTeX RDF
67	Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn	Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
64	Sachin S. Sapatnekar, Weitong Chuang	Power vs. delay in gate sizing: conflicting objectives?	ICCAD	1995	DBLP DOI BibTeX RDF	power-delay tradeoffs, short-circuit power, logic design, logic CAD, integrated circuit design, circuit CAD, optimization problem, circuit optimisation, gate sizing, convex programming, CMOS digital integrated circuits, dynamic power
63	Debjit Sinha, Hai Zhou 0001	Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation.	ICCAD	2004	DBLP DOI BibTeX RDF
60	Noriyuki Miura, Naoki Kato, Tadahiro Kuroda	Practical methodology of post-layout gate sizing for 15% more power saving.	ASP-DAC	2004	DBLP DOI BibTeX RDF
60	Joe G. Xi, Wayne Wei-Ming Dai	Useful-Skew Clock Routing with Gate Sizing for Low Power Design.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
58	I-Min Liu, Adnan Aziz	Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing.	ICCD	2000	DBLP DOI BibTeX RDF
56	Quming Zhou, Kartik Mohanram	Gate sizing to radiation harden combinational logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
56	Scott Hanson, Dennis Sylvester, David T. Blaauw	A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	voltage scaling, gate sizing, subthreshold circuits
56	Azadeh Davoodi, Ankur Srivastava 0001	Variability driven gate sizing for binning yield optimization.	DAC	2006	DBLP DOI BibTeX RDF	speed binning, process variations, gate sizing
56	Brian Swahn, Soha Hassoun	Gate sizing: finFETs vs 32nm bulk MOSFETs.	DAC	2006	DBLP DOI BibTeX RDF	gate sizing, thermal modeling, FinFET
56	Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar	A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
56	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja	False Path and Clock Scheduling Based Yield-Aware Gate Sizing.	VLSI Design	2005	DBLP DOI BibTeX RDF
56	E. T. A. F. Jacobs, Michel R. C. M. Berkelaar	Gate Sizing Using a Statistical Delay Model.	DATE	2000	DBLP DOI BibTeX RDF
56	Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru	A power optimization method considering glitch reduction by gate sizing.	ISLPED	1998	DBLP DOI BibTeX RDF
52	Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow	A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
52	Narender Hanchate, Nagarajan Ranganathan	Statistical Gate Sizing for Yield Enhancement at Post Layout Level.	ISVLSI	2007	DBLP DOI BibTeX RDF
52	Debjit Sinha, Narendra V. Shenoy, Hai Zhou 0001	Statistical Timing Yield Optimization by Gate Sizing.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
50	Murari Mani, Mahesh Sharma, Michael Orshansky	Application of fast SOCP based statistical sizing in the microprocessor design flow.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF
48	Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David T. Blaauw	A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
48	Min Ni, Seda Ogrenci Memik	Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dual-Vth, leakage power optimization, gate sizing, clock skew scheduling
48	Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang	A methodology to improve timing yield in the presence of process variations.	DAC	2004	DBLP DOI BibTeX RDF	timing analysis, gate sizing, timing yield
48	Sarvesh Bhardwaj, Sarma B. K. Vrudhula	Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
48	Giorgos Dimitrakopoulos, Dimitris Nikolos	Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing.	PATMOS	2005	DBLP DOI BibTeX RDF
48	Olivier Coudert	Gate sizing for constrained delay/power/area optimization.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
47	Kerry S. Lowe, P. Glenn Gulak	A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
44	Jason Cong, John Lee 0002, Lieven Vandenberghe	Robust gate sizing via mean excess delay minimization.	ISPD	2008	DBLP DOI BibTeX RDF	robust gate sizing, process variation, geometric programming, conditional value-at-risk
44	Feng Gao 0017, John P. Hayes	Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages.	DAC	2005	DBLP DOI BibTeX RDF	low power, linear programming, gate sizing, dual Vt
44	Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen	Efficient timing closure without timing driven placement and routing.	DAC	2004	DBLP DOI BibTeX RDF	digital design flow, gate sizing, placement and routing, timing closure
44	Arindam Mukherjee 0001, Krishna Reddy Dusety, Rajsaktish Sankaranarayan	A practical CAD technique for reducing power/ground noise in DSM circuits.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	power/ground noise, low power, linear programming, timing analysis, gate sizing, simultaneous switching noise
44	Xiangning Yang, Kewal K. Saluja	Combating NBTI Degradation via Gate Sizing.	ISQED	2007	DBLP DOI BibTeX RDF
44	Shiyan Hu, Mahesh Ketkar, Jiang Hu	Gate Sizing For Cell Library-Based Designs.	DAC	2007	DBLP DOI BibTeX RDF
44	Hsinwei Chou, Yu-Hao Wang, Charlie Chung-Ping Chen	Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation.	ASP-DAC	2005	DBLP DOI BibTeX RDF
44	Debjit Sinha, Hai Zhou 0001	Yield driven gate sizing for coupling-noise reduction under uncertainty.	ASP-DAC	2005	DBLP DOI BibTeX RDF
44	Murari Mani, Michael Orshansky	A New Statistical Optimization Algorithm for Gate Sizing.	ICCD	2004	DBLP DOI BibTeX RDF
44	Hiran Tennakoon, Carl Sechen	Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step.	ICCAD	2002	DBLP DOI BibTeX RDF
44	Wei Chen, Cheng-Ta Hsieh, Massoud Pedram	Simultaneous gate sizing and placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
44	Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess	Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
44	Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru	Timing and Power Optimization by Gate Sizing Considering False Paths.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
44	Wing Ning	Strongly NP-hard discrete gate-sizing problems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
44	Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess	Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator.	ICCAD	1994	DBLP DOI BibTeX RDF
43	Sanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Chen, Shih-Pin Hung, Tse-Yu Chiang, Jiuan-Guei Tseng	An optimal algorithm for sizing sequential circuits for industrial library based designs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
41	Debjit Sinha, Hai Zhou 0001	Gate-size optimization under timing constraints for coupling-noise reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
40	N. Ranganathan, Upavan Gupta, Venkataraman Mahalingam	Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	optimization, delay, power, gate sizing, crosstalk noise, fuzzy programming
40	Jianhua Liu, Yi Zhu 0002, Haikun Zhu, Chung-Kuan Cheng, John Lillis	Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space.	ASP-DAC	2007	DBLP DOI BibTeX RDF	optimum prefix adders, static power consumptions, dynamic power consumptions, high-level synthesis, integer linear programming, buffer insertion, gate sizing, power models, ASIC designs, parallel prefix adder, binary adder
40	Aseem Agarwal, Kaviraj Chopra, David T. Blaauw	Statistical Timing Based Optimization using Gate Sizing.	DATE	2005	DBLP DOI BibTeX RDF
40	Rajeev R. Rao, David T. Blaauw, Dennis Sylvester	Soft error reduction in combinational logic using gate resizing and flipflop selection.	ICCAD	2006	DBLP DOI BibTeX RDF
39	Weiguang Sheng, Liyi Xiao, Zhigang Mao	Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm.	DAC	2009	DBLP DOI BibTeX RDF	genetic algorithm, optimization, soft error, multi-objective
39	Chen Li 0004, Cheng-Kok Koh, Patrick H. Madden	Floorplan management: incremental placement for gate sizing and buffer insertion.	ASP-DAC	2005	DBLP DOI BibTeX RDF
36	R. Reed Taylor, Herman Schmit	Creating a power-aware structured ASIC.	ISLPED	2004	DBLP DOI BibTeX RDF	VPGA, low-power, voltage scaling, power optimization, gate sizing, structured ASIC
36	Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone	Power reduction through iterative gate sizing and voltage scaling.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
36	How-Rern Lin, TingTing Hwang	Dynamical identification of critical paths for iterative gate sizing.	ICCAD	1994	DBLP DOI BibTeX RDF
36	Tao Luo 0002, David Newmark, David Z. Pan	Total power optimization combining placement, sizing and multi-Vt through slack distribution management.	ASP-DAC	2008	DBLP DOI BibTeX RDF
36	David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer	Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization.	ISLPED	2003	DBLP DOI BibTeX RDF	dual threshold, sizing, dual supply voltage, simultaneous
36	Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim	Interleaving buffer insertion and transistor sizing into a single optimization.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
32	Koustav Bhattacharya, Nagarajan Ranganathan	A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations.	ISQED	2009	DBLP DOI BibTeX RDF
32	Azadeh Davoodi, Ankur Srivastava 0001	Variability Driven Gate Sizing for Binning Yield Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
32	Sanghamitra Roy, Weijen Chen, Charlie Chung-Ping Chen, Yu Hen Hu	Numerically Convex Forms and Their Application in Gate Sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
32	Ashish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava 0001	Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence.	VLSI Design	2007	DBLP DOI BibTeX RDF
31	M. Emadi, Amir Jafargholi, M. H. Sargazi Moghadam, Mohammad Mahdi Nayebi	Optimum Supply and Threshold Voltages and Transistor Sizing Effects on Low Power SOI Circuit Design.	APCCAS	2006	DBLP DOI BibTeX RDF
31	Philippe Maurine, Xavier Michel, Nadine Azémard, Daniel Auvergne	Gate speed improvement at minimal power dissipation.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
31	Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis 0001	Transistor sizing and gate sizing using geometric programming considering delay minimization.	NEWCAS	2012	DBLP DOI BibTeX RDF
29	Nathaniel A. Conos, Saro Meguerdichian, Miodrag Potkonjak	Gate sizing in the presence of gate switching activity and input vector control.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
29	Sarvesh Bhardwaj, Yu Cao 0001, Sarma B. K. Vrudhula	Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection.	J. Low Power Electron.	2006	DBLP DOI BibTeX RDF
28	Chin Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi	Path-Based Buffer Insertion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
28	Narender Hanchate, Nagarajan Ranganathan	Integrated Gate and Wire Sizing at Post Layout Level.	ISVLSI	2007	DBLP DOI BibTeX RDF
28	Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi	Path based buffer insertion.	DAC	2005	DBLP DOI BibTeX RDF	layout, physical design, global routing, buffer insertion, power minimization, interconnect synthesis
28	Weitong Chuang, Ibrahim N. Hajj	Delay and area optimization for compact placement by gate resizing and relocation.	ICCAD	1994	DBLP DOI BibTeX RDF
27	Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy 0001	Profit Aware Circuit Design Under Process Variations Considering Speed Binning.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
27	Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy 0001	Speed binning aware design methodology to improve profit under parameter variations.	ASP-DAC	2006	DBLP DOI BibTeX RDF
25	Zhuo Li 0001, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou	Ultra-fast interconnect driven cell cloning for minimizing critical path delay.	ISPD	2010	DBLP DOI BibTeX RDF	gate duplication, physical synthesis, timing-driven placement
24	Peter-Michael Seidel, Guy Even	Delay-Optimized Implementation of IEEE Floating-Point Addition.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	IEEE rounding, dual path algorithm, optimized gate sizing, buffer insertion, delay optimization, logical effort, Floating-point addition
24	Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera	Crosstalk noise optimization by post-layout transistor sizing.	ISPD	2002	DBLP DOI BibTeX RDF	capacitive coupling noise, post-layout optimization, gate sizing, transistor sizing, crosstalk noise
24	Chris C. N. Chu, D. F. Wong 0001	VLSI Circuit Performance Optimization by Geometric Programming.	Ann. Oper. Res.	2001	DBLP DOI BibTeX RDF	unary geometric programming, circuit performance optimization, VLSI design, Lagrangian relaxation, gate sizing, transistor sizing, wire sizing
24	Jason Cong, Patrick H. Madden	Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
24	Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen	Timing and Crosstalk Driven Area Routing.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization