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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2634 occurrences of 1291 keywords
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Results
Found 4878 publication records. Showing 4770 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
96 | S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury |
Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 361-366, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates |
76 | Chris J. Myers, Peter A. Beerel, Teresa H.-Y. Meng |
Technology mapping of timed circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 138-, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
gate library, C-elements, ATACS, timing, logic design, logic CAD, asynchronous circuits, asynchronous circuits, timing information, AND gates, synthesis tool, OR gates, timed circuits |
68 | Nathan O. Scott, Gerhard W. Dueck |
Pairwise decomposition of toffoli gates in a quantum circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 231-236, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
elementary quantum gates, synthesis, minimization, reversible logic, quantum circuits |
64 | Shoujue Wang, Xunwei Wu, Hongjuan Feng |
The High-Speed Ternary Logic Gates Based on the Multiple beta Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 178-181, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high speed ternary logic gates, multiple /spl beta/ transistors, multiple emitter transistor, current gain, linear AND/OR gates, multi valued literal circuits, high speed multi valued logic circuits, multivalued logic circuits, logic gates, ternary logic, transistors |
56 | Stephen S. Bullock, Igor L. Markov |
An arbitrary twoqubit computation In 23 elementary gates or less. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 324-329, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
CNOT, circuit decomposition, elementary gates, lie theory, optimization, algorithms, lower bounds, synthesis, quantum circuits, qubit |
54 | Vincenzo Catania, Marco Russo |
Analog gates for a VLSI fuzzy processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 299-304, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
VLSI fuzzy processor, synchronous fuzzy circuits, high noise immunity, fuzzy gates, VLSI, fuzzy logic, CMOS logic circuits, CMOS technology, logic gates, analogue processing circuits |
53 | Ahmed N. Sulaiman, Patrick Olivier |
Attribute gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UIST ![In: Proceedings of the 21st Annual ACM Symposium on User Interface Software and Technology, Monterey, CA, USA, October 19-22, 2008, pp. 57-66, 2008, ACM, 978-1-59593-975-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
crossing interfaces, large interactive displays, tabletop territories, pen-based input, digital tabletops, user interface components |
51 | Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller |
Toffoli network synthesis with templates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6), pp. 807-817, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
51 | Mawahib Hussein Sulieman |
On the Reliability of Interconnected CMOS Gates Considering MOSFET Threshold-Voltage Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings, pp. 251-258, 2009, Springer, 978-3-642-04849-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Reliability, CMOS, threshold voltage, gates |
47 | Stasys Jukna |
Finite Limits and Monotone Computations: The Lower Bounds Criterion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCC ![In: Proceedings of the Twelfth Annual IEEE Conference on Computational Complexity, Ulm, Germany, June 24-27, 1997, pp. 302-313, 1997, IEEE Computer Society, 0-8186-7907-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
real gates, lower bounds, threshold gates, monotone circuits |
47 | Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng |
Automatic synthesis of gate-level timed circuits with choice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 42-58, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates |
47 | Kristoffer Arnsfelt Hansen |
Depth Reduction for Circuits with a Single Layer of Modular Counting Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSR ![In: Computer Science - Theory and Applications, Fourth International Computer Science Symposium in Russia, CSR 2009, Novosibirsk, Russia, August 18-23, 2009. Proceedings, pp. 117-128, 2009, Springer, 978-3-642-03350-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
47 | Yu Hu 0002, Satyaki Das, Steven Trimberger, Lei He 0001 |
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 188-193, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Rolando Ramírez Ortiz, John P. Knight |
Compatible cell connections for multifamily dynamic logic gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(3), pp. 327-340, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
47 | Sudhakar Bobba, Ibrahim N. Hajj |
Current-Mode Threshold Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 235-240, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
47 | Mitsuru Igusa, Mark Beardslee, Alberto L. Sangiovanni-Vincentelli |
ORCA a Sea-of-Gates Place and Route System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 122-127, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
46 | Rajesh Garg, Sunil P. Khatri |
A novel, highly SEU tolerant digital circuit design approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 14-20, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
46 | Wolfgang Maass 0001, Georg Schnitger, Eduardo D. Sontag |
On the Computational Power of Sigmoid versus Boolean Threshold Circuits ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 32nd Annual Symposium on Foundations of Computer Science, San Juan, Puerto Rico, 1-4 October 1991, pp. 767-776, 1991, IEEE Computer Society, 0-8186-2445-0. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
polynomially bounded weights, sigmoid threshold gates, smooth threshold gates, depth 2 circuits, Boolean threshold circuits, constant size circuits, Boolean threshold gates, polynomial size sigmoid threshold circuits, Boolean functions, computational power, constant depth circuits |
45 | Shane Greenstein |
The Long Arc Behind Bill Gates' Wealth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 28(1), pp. 4-7, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
William Gates, antitrust, economics, competition, browser, Microsoft, bundling |
45 | Thomas Flohr 0002 |
Defining Suitable Criteria for Quality Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSM/Metrikon/Mensura ![In: Software Process and Product Measurement, International Conferences: IWSM 2008, Metrikon 2008, and Mensura 2008, Munich, Germany, November 18-19, 2008. Proceedings, pp. 245-256, 2008, Springer, 978-3-540-89402-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Practical measurement application, Measurement acceptance, Quality Gates |
44 | Youngja Park, Christopher S. Gates, Stephen C. Gates |
Estimating Asset Sensitivity by Profiling Users. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESORICS ![In: Computer Security - ESORICS 2013 - 18th European Symposium on Research in Computer Security, Egham, UK, September 9-13, 2013. Proceedings, pp. 94-110, 2013, Springer, 978-3-642-40202-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
43 | Hung Chi Lai, Saburo Muroga |
Minimum Parallel Binary Adders with NOR (NAND) Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 28(9), pp. 648-659, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
NOR gates, carry-ripple adders, minimum adders, NAND gates, logic design, Adders |
43 | Jay Niel Culliney, Ming Huei Young, Tomoyasu Nakagawa, Saburo Muroga |
Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 28(1), pp. 76-85, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
n-p-n-equivalence classes, four variable switching functions, optimal networks, logical design, branch-and-bound method, AND gates, OR gates |
41 | Xiaojun Ma, Jing Huang 0001, Cecilia Metra, Fabrizio Lombardi |
Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 297-311, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Testing, Emerging technologies, Reversible computing, QCA |
41 | Asif Islam Khan, Nadia Nusrat, Samira Manabi Khan, Masud Hasan, Mozammel H. A. Khan |
Quantum Realization of Some Ternary Circuits Using Muthukrishnan-Stroud Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 20, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang 0006, Marek A. Perkowski |
Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9), pp. 1652-1663, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Pawel Kerntopf, Marek A. Perkowski, Mozammel H. A. Khan |
On Universality of General Reversible Multiple-Valued Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 19-22 May 2004, Toronto, Canada, pp. 68-73, 2004, IEEE Computer Society, 0-7695-2130-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Marek A. Perkowski, Nouraddin Alhagi, Martin Lukac, Neha Saxena, Scott Blakely |
Synthesis of Small Reversible and Pseudo-Reversible Circuits Using Y-Gates and Inverse Y-Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010, Barcelona, Spain, 26-28 May 2010, pp. 245-251, 2010, IEEE Computer Society, 978-0-7695-4024-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
pseudo-reversible logic gates, reversible circuits |
40 | Mozammel H. A. Khan, Marek A. Perkowski |
GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 11, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller |
Synthesis of Fredkin-Toffoli reversible networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(6), pp. 765-769, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
40 | Märt Saarepera, Tomohiro Yoneda |
A Self-Timed Implementation of Boolean Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 19-22 April 1999, Barcelona, Spain, pp. 243-, 1999, IEEE Computer Society, 0-7695-0031-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
40 | Kerry S. Lowe, P. Glenn Gulak |
A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(5), pp. 419-434, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
39 | Xinliang Zhang, Jing Xu, Jianji Dong, Dexiu Huang |
All-Optical Logic Gates Based on Semiconductor Optical Amplifiers and Tunable Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OSC ![In: Optical SuperComputing, Second International Workshop, OSC 2009, Bertinoro, Italy, November 18-20, 2009. Proceedings, pp. 19-29, 2009, Springer, 978-3-642-10441-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
all-optical logic gates, semiconductor optical amplifiers (SOAs), delay interferometer, bandpass filter |
39 | Shane Greenstein |
The Long Arc Behind Bill Gates' Wealth, Part 2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 28(2), pp. 2-5, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
William Gates, antitrust, economics, competition, browser, Microsoft, bundling |
38 | Francisco J. Artigas, Soon Ae Chun, Yogi Sookhu |
Real-time ocean surge warning system, meadowlands district of New Jersey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
D.GO ![In: Proceedings of the 10th Annual International Conference on Digital Government Research, Partnerships for Public Innovation, DG.O 2009, Puebla, Mexico, May 17-20, 2009, pp. 216-222, 2009, Digital Government Research Center, 978-1-60558-535-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
emergency management system, real-time ocean surge warnings, tide gates, sensor network, flood, information dissemination, emergency management, sensor system |
38 | David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah |
Timing verification of sequential domino circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 127-132, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
domino gates, sequential domino circuits, static timing verification, logic testing, input signals |
36 | Yuri B. Boiko, Gabriel A. Wainer |
Modeling quantum dot devices in Cell-DEVS environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SpringSim ![In: Proceedings of the 2008 Spring Simulation Multiconference, SpringSim 2008, Ottawa, Canada, April 14-17, 2008, pp. 18, 2008, SCS/ACM, 1-56555-319-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
majority vote gates, quantum wire, cellular automata, discrete event simulation, quantum dot, XOR gates, cell-DEVS, quantum automata |
36 | Yuyun Liao, D. M. H. Walker |
Optimal voltage testing for physically-based faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 344-353, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise |
36 | M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor |
Compact test sets for industrial circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 358-366, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
compact test sets, industrial circuits, binary logic elements, three-state elements, compaction oriented decision making, heuristics, logic testing, integrated circuit testing, automatic test pattern generation, combinational circuits, automatic testing, multivalued logic circuits, test patterns, bidirectionals, xor gates, or gates, test set size |
36 | S. C. Prasad, Kaushik Roy 0001 |
Circuit optimization for minimisation of power consumption under delay constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 305-309, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates |
35 | Falk Unger |
Noise Threshold for Universality of Two-Input Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 54(8), pp. 3693-3698, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Yang Zhao 0001, Tao Xu 0002, Krishnendu Chakrabarty |
Digital Microfluidic Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - Third International ICST Conference, NanoNet 2008, Boston, MA, USA, September 14-16, 2008, Revised Selected Papers, pp. 54-60, 2008, Springer, 978-3-642-02426-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
microfluidic computing, digital microfluidics, logic gate |
35 | Krishna Santhanam, Kenneth S. Stevens |
Dynamic gates with hysteresis and configurable noise tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 184-189, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Jose M. Marulanda, Ashok Kumar Srivastava, Ashwani K. Sharma |
Transfer characteristics and high frequency modeling of logic gates using carbon nanotube field effect transistors (CNT-FETs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 202-206, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
CNT-logic, cut-off frequency, small signal model, transfer characteristics, carbon nanotubes |
35 | Wenping Wang, Zile Wei, Shengqi Yang, Yu Cao 0001 |
An efficient method to identify critical gates under circuit aging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 735-740, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Xiaoyu Song, Guowu Yang, Marek A. Perkowski, Yuke Wang |
Algebraic Characterization of Reversible Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Theory Comput. Syst. ![In: Theory Comput. Syst. 39(2), pp. 311-319, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Josep Carmona 0001, Jordi Cortadella, Yousuke Takada, Ferdinand Peper |
From molecular interactions to gates: a systematic approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 891-898, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
nanocascades, formal methods, nanocomputing |
35 | Sandeep Dechu, Manoj Kumar Goparaju, Spyros Tragoudas |
A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 318-326, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Wladyslaw Homenda, Witold Pedrycz |
Balanced Fuzzy Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RSCTC ![In: Rough Sets and Current Trends in Computing, 5th International Conference, RSCTC 2006, Kobe, Japan, November 6-8, 2006, Proceedings, pp. 107-116, 2006, Springer, 3-540-47693-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Arkadev Chattopadhyay, Kristoffer Arnsfelt Hansen |
Lower Bounds for Circuits with Few Modular and Symmetric Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP ![In: Automata, Languages and Programming, 32nd International Colloquium, ICALP 2005, Lisbon, Portugal, July 11-15, 2005, Proceedings, pp. 994-1005, 2005, Springer, 3-540-27580-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Stefan Mangard, Thomas Popp, Berndt M. Gammel |
Side-Channel Leakage of Masked CMOS Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CT-RSA ![In: Topics in Cryptology - CT-RSA 2005, The Cryptographers' Track at the RSA Conference 2005, San Francisco, CA, USA, February 14-18, 2005, Proceedings, pp. 351-365, 2005, Springer, 3-540-24399-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu |
Identification of Gates for Covering all Critical Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), Common Challenges and Solutions, 08-10 September 2004, Austin, Texas, USA, pp. 92-96, 2004, IEEE Computer Society, 0-7695-2320-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Peter M. Kelly, C. J. Thompson, T. Martin McGinnity, Liam P. Maguire |
A Binary Multiplier Using RTD Based Threshold Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN (2) ![In: Artificial Neural Nets Problem Solving Methods, 7th International Work-Conference on Artificial and Natural Neural Networks, IWANN2003, Maó, Menorca, Spain, June 3-6, 2003 Proceedings, Part II, pp. 41-48, 2003, Springer, 3-540-40211-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Pawel Kerntopf |
Synthesis of Multipurpose Reversible Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 259-267, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Alexis De Vos, Bart Desoete, Artur Adamski, Piotr Pietrzak, Maciej Sibínski, Tomasz Widerski |
Design of Reversible Logic Circuits by Means of Control Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, pp. 255-264, 2000, Springer, 3-540-41068-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
35 | Mayukh Bhattacharya, Pinaki Mazumder |
Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 65-70, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Quantum devices, Digital circuits, Resonant Tunneling Diode, Noise margin, Threshold gate |
35 | Nicholas Pippenger |
Invariance of complexity measures for networks with unreliable gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 36(3), pp. 531-539, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
35 | G. D. Adams, Carlo H. Séquin |
Template Style Considerations for Sea-of-Gates Layout Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 31-36, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
35 | Donald L. Richards |
Efficient Exercising of Switching Elements in Nets of Identical Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 20(1), pp. 88-111, 1973. The full citation details ...](Pics/full.jpeg) |
1973 |
DBLP DOI BibTeX RDF |
|
34 | Kazuo Iwama, Hiroki Morizumi, Jun Tarui |
Negation-Limited Complexity of Parity and Inverters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmica ![In: Algorithmica 54(2), pp. 256-267, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Negation-limited circuit, Parity function, Inversion complexity, Gate elimination, Circuit complexity, Inverter |
34 | Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud |
Dual-threshold pass-transistor logic design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 291-296, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dual threshold, pass transistor, low power, leakage |
34 | Chia-Ming Chang 0002, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang 0002, Yu-Sheng Lu |
Type-matching clock tree for zero skew clock gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 714-719, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
physical design, gated clock, clock network synthesis |
34 | Wieland Fischer, Berndt M. Gammel |
Masking at Gate Level in the Presence of Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings, pp. 187-200, 2005, Springer, 3-540-28474-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
random masking, masked logic circuits, Cryptanalysis, side-channel attacks, DPA, power analysis, logic circuits, digital circuits, masking, glitches |
34 | Li Ding 0002, Pinaki Mazumder |
On circuit techniques to improve noise immunity of CMOS dynamic logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(9), pp. 910-925, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller |
Fredkin/Toffoli Templates for Reversible Logic Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 256-261, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Chuen-Der Huang, I-Fang Chung, Nikhil R. Pal, Chin-Teng Lin |
Machine Learning for Multi-class Protein Fold Classification Based on Neural Networks with Feature Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICANN ![In: Artificial Neural Networks and Neural Information Processing - ICANN/ICONIP 2003, Joint International Conference ICANN/ICONIP 2003, Istanbul, Turkey, June 26-29, 2003, Proceedings, pp. 1168-1175, 2003, Springer, 3-540-40408-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka |
Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 15-20, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Vince Grolmusz, Gábor Tardos |
Lower Bounds for (MOD p - MOD m) Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 39th Annual Symposium on Foundations of Computer Science, FOCS '98, November 8-11, 1998, Palo Alto, California, USA, pp. 279-289, 1998, IEEE Computer Society, 0-8186-9172-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Sorin Cotofana, Stamatis Vassiliadis |
On the Design Complexity of the Issue Logic of Superscalar Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10277-10284, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Rajesh S. Parthasarathy, Ramalingam Sridhar |
Double Pass Transistor Logic for High Performance Wave Pipeline Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 495-500, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas |
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 407-410, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
leakage estimation, logic design, cmos gates |
34 | Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider |
A comparative study of CMOS gates with minimum transistor stacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 93-98, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
PTL, unateness, BDDs, technology mapping, switch theory, logical effort, CMOS gates |
34 | Frank Sill, Jiaxi You, Dirk Timmermann |
Design of mixed gates for leakage reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 263-268, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
mixed gates, leakage current, threshold voltage, gate leakage |
34 | Markus Dichtl, Jovan Dj. Golic |
High-Speed True Random Number Generation with Logic Gates Only. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings, pp. 45-62, 2007, Springer, 978-3-540-74734-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
generalized ring oscillators, true randomness, Random number generation, logic gates, ring oscillators |
34 | Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee |
A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 977-982, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
dynamic gates, keeper design, reliability, VLSI, robustness, low-power design, process variation |
34 | Michal Koucký 0001, Pavel Pudlák, Denis Thérien |
Bounded-depth circuits: separating wires from gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 37th Annual ACM Symposium on Theory of Computing, Baltimore, MD, USA, May 22-24, 2005, pp. 257-265, 2005, ACM, 1-58113-960-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
communication, complexity, lower bounds, regular languages, wires, constant-depth circuits, gates |
34 | Joshua Berman, Arthur Drisko, François Lemieux, Cristopher Moore, Denis Thérien |
Circuits and Expressions with NOn-Associative Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCC ![In: Proceedings of the Twelfth Annual IEEE Conference on Computational Complexity, Ulm, Germany, June 24-27, 1997, pp. 193-203, 1997, IEEE Computer Society, 0-8186-7907-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
non-associative gates, non-associative groupoid, polyabelian groupoids, arbitrary Boolean functions, NC/sup 1/-complete, CIRCUIT VALUE, Boolean functions, multiplication, P-complete, EXPRESSION EVALUATION |
32 | Oriol Roig, Jordi Cortadella, Enric Pastor |
Hierarchical gate-level verification of speed-independent circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 128-137, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
hierarchical gate-level verification, state signals, computational complexity, logic testing, time complexity, asynchronous circuits, speed-independent circuits, complex gates |
32 | Sandip Kundu, Sudhakar M. Reddy |
Robust tests for parity trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(3), pp. 191-200, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
linear gates, parity trees, URTS, robust tests, test length |
31 | Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(7), pp. 830-836, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Esther Rodríguez-Villegas, José M. Quintana, Maria J. Avedillo, Adoración Rueda |
High-speed low-power logic gates using floating gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 389-392, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Guilu Long 0001, Yang Liu |
Duality quantum computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Frontiers Comput. Sci. China ![In: Frontiers Comput. Sci. China 2(2), pp. 167-178, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
duality computer, duality quantum computer, duality parallelism, duality gates, duality mode, generalized quantum gates, combiner, divider |
30 | Michel Renovell, P. Huc, Yves Bertrand |
The concept of resistance interval: a new parametric model for realistic resistive bridging fault. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 184-189, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
electric resistance, resistance interval, intrinsic resistance, logic behavior, 0 to 500 ohm, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, fault detection, automatic testing, fault coverage, bridging faults, parametric model, logic gates, logic gates, resistive bridging fault, faulty behavior |
30 | Shyue-Win Wei |
A Systolic Power-Sum Circuit for GF(2^m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(2), pp. 226-229, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
systolic power-sum circuit, power-sum circuit, error correction codes, error-correcting codes, finite field, systolic arrays, decoding, logic circuits, logic gates, logical gates |
30 | Ingo Wegener |
Comments on "A Characterization of Binary Decision Diagrams". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(3), pp. 383-384, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
EXOR gates, NEXOR gates, free BDDs, ordered BDDs, repeated BDDs, computational complexity, complexity, Boolean functions, binary decision diagrams, decision tables, combinatorial circuits |
30 | Niraj K. Jha |
Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(2), pp. 179-189, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
CVS parity trees, strongly self-checking parity, single stuck-at, stuck-open, stuck-on fault detection, cascode voltage switch, differential cascode voltage switch, EX-OR gates, single-ended cascode voltage switch, logic testing, fault location, logic gates, two-rail checkers |
30 | Eric Allender |
A Note on the Power of Threshold Circuits ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 30th Annual Symposium on Foundations of Computer Science, Research Triangle Park, North Carolina, USA, 30 October - 1 November 1989, pp. 580-584, 1989, IEEE Computer Society, 0-8186-1982-1. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
unbounded-fan-in circuits, depth-three threshold circuits, polynomial hierarchy, threshold circuits, AND gates, OR gates |
30 | Hung Chi Lai, Saburo Muroga |
Logic Networks of Carry-Save Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(9), pp. 870-882, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
parallel adder in double-rail input logic, Carry?save adders, input bundles, multioperand adders, NAND gates, NOR gates, output bundles, logic design, multipliers, full adders |
30 | Jing Wang 0001, Gianluca Meloni, Gianluca Berrettini, Luca Potì, Antonella Bogoni |
All-Optical Clocked Flip-Flops Exploiting SOA-Based SR Latches and Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OSC ![In: Optical SuperComputing, Second International Workshop, OSC 2009, Bertinoro, Italy, November 18-20, 2009. Proceedings, pp. 5-18, 2009, Springer, 978-3-642-10441-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
optical flip-flop, optical logic gate, optical signal processing, semiconductor optical amplifier (SOA) |
30 | Hagen Sämrow, Claas Cornelius, Frank Sill, Andreas Tockhorn, Dirk Timmermann |
Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
gate oxide breakdown, reliability, integrated circuit design, redundant systems |
30 | Ashish Goel, Morteza Ibrahimi |
Renewable, Time-Responsive DNA Logic Gates for Scalable Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DNA ![In: DNA Computing and Molecular Programming, 15th International Conference, DNA 15, Fayetteville, AR, USA, June 8-11, 2009, Revised Selected Papers, pp. 67-77, 2009, Springer, 978-3-642-10603-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | James Donald, Niraj K. Jha |
Reversible logic synthesis with Fredkin and Peres gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(1), pp. 2:1-2:19, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Quantum computing, reversible logic |
30 | David Guerrero Martos, Alejandro Millán 0001, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo |
Static Power Consumption in CMOS Gates Using Independent Bodies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 404-412, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Mario Vélez, Juan Ospina |
Universal Quantum Gates Via Yang-Baxterization of Dihedral Quantum Double. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICANNGA (1) ![In: Adaptive and Natural Computing Algorithms, 8th International Conference, ICANNGA 2007, Warsaw, Poland, April 11-14, 2007, Proceedings, Part I, pp. 120-127, 2007, Springer, 978-3-540-71589-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Arkadev Chattopadhyay, Navin Goyal, Pavel Pudlák, Denis Thérien |
Lower bounds for circuits with MOD_m gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 47th Annual IEEE Symposium on Foundations of Computer Science (FOCS 2006), 21-24 October 2006, Berkeley, California, USA, Proceedings, pp. 709-718, 2006, IEEE Computer Society, 0-7695-2720-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Kristian Granhaug, Snorre Aunet, Tor Sverre Lande |
Body-bias regulator for ultra low power multifunction CMOS gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson |
CMOS Realization of Online Testable Reversible Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 309-310, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Kazuyuki Amano, Akira Maruoka |
On the Complexity of Depth-2 Circuits with Threshold Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MFCS ![In: Mathematical Foundations of Computer Science 2005, 30th International Symposium, MFCS 2005, Gdansk, Poland, August 29 - September 2, 2005, Proceedings, pp. 107-118, 2005, Springer, 3-540-28702-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Emanuele Viola |
Pseudorandom Bits for Constant Depth Circuits with Few Arbitrary Symmetric Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCC ![In: 20th Annual IEEE Conference on Computational Complexity (CCC 2005), 11-15 June 2005, San Jose, CA, USA, pp. 198-209, 2005, IEEE Computer Society, 0-7695-2364-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Geoff V. Merrett, Bashir M. Al-Hashimi |
Leakage Power Analysis and Comparison of Deep Submicron Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 198-207, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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