Search results for "FPGAs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Ken McElvain	FPGAs at 65NM and Beyond - Powerful New FPGAs Bring New Challenges.	FPL	2006	DBLP DOI BibTeX RDF
31	István Vassányi	Implementing Processor Arrays on FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
31	Neil Woolfries, Patrick Lysaght, Stephen Marshall, Gordon Charles McGregor, David Robinson	Fast Adaptive Image Processing in FPGAs Using Stack Filters.	FPL	1998	DBLP DOI BibTeX RDF
30	Chen Huang 0005, Frank Vahid	Server-side coprocessor updating for mobile devices with FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	coprocessing, fpgas, dynamic optimization, acceleration
30	Christoph Bösch, Jorge Guajardo, Ahmad-Reza Sadeghi, Jamshid Shokrollahi, Pim Tuyls	Efficient Helper Data Key Extractor on FPGAs.	CHES	2008	DBLP DOI BibTeX RDF	Intrinsic PUF, Fuzzy Extractor, Helper Data Algorithm, FPGAs, Implementation, Physical Unclonable Functions
30	Ahsan Shabbir, Akash Kumar 0001, Bart Mesman, Henk Corporaal	Enabling MPSoC Design Space Exploration on FPGAs.	IMTIC	2008	DBLP DOI BibTeX RDF	FPGAs, MPSoC, FIFO, FSL
30	Vishal Suthar, Shantanu Dutt	High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	built-in self-tester (BISTer), roving tester (ROTE), FPGAs, functional testing, on-line testing, diagnosability
30	Hasan Arslan, Shantanu Dutt	An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	bump and refit paradigm, bumping cost, hop-based routing, switchbox, FPGAs, detailed routing, MST
30	Pongstorn Maidee, Cristinel Ababei, Kia Bazargan	Fast timing-driven partitioning-based placement for island style FPGAs.	DAC	2003	DBLP DOI BibTeX RDF	FPGA placement, partitioning based placement, FPGAs, timing-driven placement
30	Deepali Deshpande, Arun K. Somani, Akhilesh Tyagi	Hybrid Data/Configuration Caching for Striped FPGAs.	FCCM	1999	DBLP DOI BibTeX RDF	Striped FPGAs, data caching, configuration caching
30	Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara	On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Look-up table FPGAs, universal fault diagnosis, diagnosis complexity, C-diagnosable
30	Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar	A multiplier generator for Xilinx FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs
30	Aiguo Lu, Erik L. Dagless, Jonathan M. Saul	DART: delay and routability driven technology mapping for LUT based FPGAs.	ICCD	1995	DBLP DOI BibTeX RDF	DART, delay driven technology mapping, LUT based FPGAs, two-phased approach, routability directed delay-optimal mapping, stochastic routability analysis, delay-optimal mapping, field programmable gate arrays, delays, logic design, programmable logic arrays, table lookup, minimisation of switching nets
30	Mahesh Mehendale, M. K. Ram Prasad	AATMA: an algorithm for technology mapping for antifuse-based FPGAs.	VLSI Design	1995	DBLP DOI BibTeX RDF	AATMA, antifuse-based FPGAs, logic module structure, complex functions, signature-matching based approach, mapping quality, logic module architectures, field programmable gate arrays, directed graphs, combinational circuits, logic CAD, technology mapping, execution times
30	A. Pal, R. K. Gorai, V. V. S. S. Raju	Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs.	VLSI Design	1995	DBLP DOI BibTeX RDF	multiplexing equipment, multiplexer network, ratio parameters, Actel ACT1, MCNC benchmark problems, field programmable gate arrays, FPGAs, VLSI, Boolean functions, Boolean functions, logic design, iterative methods, combinational circuits, combinational circuits, logic CAD, multiplexing, search space, tree network, iterative approach
29	Yee Jern Chong, Sri Parameswaran	Flexible multi-mode embedded floating-point unit for field programmable gate arrays.	FPGA	2009	DBLP DOI BibTeX RDF	dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture
29	Suresh Srinivasan, Krishnan Ramakrishnan, Prasanth Mangalagiri, Yuan Xie 0001, Vijaykrishnan Narayanan, Mary Jane Irwin, Karthik Sarpatwari	Toward Increasing FPGA Lifetime.	IEEE Trans. Dependable Secur. Comput.	2008	DBLP DOI BibTeX RDF	Reliability, Reconfigurable hardware, availability and serviceability
29	Jorge Guajardo, Sandeep S. Kumar, Geert Jan Schrijen, Pim Tuyls	FPGA Intrinsic PUFs and Their Use for IP Protection.	CHES	2007	DBLP DOI BibTeX RDF
29	Ling Zhuo, Viktor K. Prasanna	Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems.	ICPADS (1)	2006	DBLP DOI BibTeX RDF
29	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
29	Arifur Rahman, Shamik Das, Anantha P. Chandrakasan, Rafael Reif	Wiring requirement and three-dimensional integration technology for field programmable gate arrays.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
29	Zhibin Dai, Dilip K. Banerji	Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy.	VLSI Design	2003	DBLP DOI BibTeX RDF
29	Arifur Rahman, Shamik Das, Anantha P. Chandrakasan, Rafael Reif	Wiring requirement and three-dimensional integration of field-programmable gate arrays.	SLIP	2001	DBLP DOI BibTeX RDF	3-D integrated circuits, FPGA, system-level modeling, wire-length
29	Carl Ebeling, Larry McMurchie, Scott Hauck, Steven M. Burns	Placement and routing tools for the Triptych FPGA.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
29	Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto	Universal test complexity of field-programmable gate arrays.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	universal test complexity, arbitrary logic circuits, sequential loading, random access loading, programming schemes, block-sliced loading, configuration memory cells, field programmable gate arrays, field-programmable gate array, computational complexity, fault diagnosis, logic testing, design for testability, fault model, logic CAD, table lookup, look-up tables, automatic test software, C-testable
27	Gregory Lucas, Chen Dong 0003, Deming Chen	Variation-aware placement for FPGAs with multi-cycle statistical timing analysis.	FPGA	2010	DBLP DOI BibTeX RDF	multi-cycle, variation-aware, fpga, placement, ssta, statistical static timing analysis
27	Mike Brugge, Mohammed A. S. Khalid	Design and evaluation of a parameterizable NoC router for FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, architecture, system-on-chip, network-on-chip, design space exploration, router
27	Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung	Self-Measurement of Combinatorial Circuit Delays in FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, Testing, configuration, delay measurement
27	Jason Agron	Domain-Specific Language for HW/SW Co-design for FPGAs.	DSL	2009	DBLP DOI BibTeX RDF
27	Andrei Hagiescu, Weng-Fai Wong, David F. Bacon, Rodric M. Rabbah	A computing origami: folding streams in FPGAs.	DAC	2009	DBLP DOI BibTeX RDF	FPGA, streaming, throughput, latency
27	Junqing Sun, Gregory D. Peterson, Olaf O. Storaasli	High-Performance Mixed-Precision Linear Solver for FPGAs.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
27	Boyan Valtchanov, Alain Aubert, Florent Bernard, Viktor Fischer	Modeling and observing the jitter in ring oscillators implemented in FPGAs.	DDECS	2008	DBLP DOI BibTeX RDF
27	Michael T. Frederick, Arun K. Somani	Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	carry chain, depth optimal mapping, logic chain
27	Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer	A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	simulation, FPGA, prototyping, performance models, emulation
27	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne	Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming.	DATE	2008	DBLP DOI BibTeX RDF
27	Maurizio Tranchero, Leonardo Maria Reyneri	Implementation of Self-Timed Circuits onto FPGAs Using Commercial Tools.	DSD	2008	DBLP DOI BibTeX RDF
27	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne	Efficient synthesis of compressor trees on FPGAs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
27	Justin S. J. Wong, Peter Y. K. Cheung, N. Pete Sedcole	Combating process variation on FPGAS with a precise at-speed delay measurement method.	FPL	2008	DBLP DOI BibTeX RDF
27	Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung	Fault tolerant methods for reliability in FPGAs.	FPL	2008	DBLP DOI BibTeX RDF
27	Michail Maniatakos, Songhua Xu, Willard L. Miranker	Constraint-Based Placement and Routing for FPGAs Using Self-Organizing Maps.	ICTAI (2)	2008	DBLP DOI BibTeX RDF
27	Ian Kuon, Jonathan Rose	Measuring the Gap Between FPGAs and ASICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
27	Julien Lamoureux, Steven J. E. Wilton	Clock-Aware Placement for FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
27	Chi Wai Yu	VPH - A Tool for Exploring Hybrid FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
27	Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan	Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs.	IPDPS	2007	DBLP DOI BibTeX RDF
27	Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung	Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs.	FCCM	2007	DBLP DOI BibTeX RDF
27	Walid A. Najjar	Compiling code accelerators for FPGAs.	CASES	2007	DBLP DOI BibTeX RDF	FPGA code acceleration
27	Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew	SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs.	ISQED	2007	DBLP DOI BibTeX RDF
27	Premachandran R. Menon, Weifeng Xu, Russell Tessier	Design-specific path delay testing in lookup-table-based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
27	Ian Kuon, Jonathan Rose	Measuring the gap between FPGAs and ASICs.	FPGA	2006	DBLP DOI BibTeX RDF	area comparison, delay comparison, power comparison, FPGA, ASIC
27	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko	Yield enhancements of design-specific FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	design-specific FPGA, interconnect faults, interconnect utilization, yield enhancement, yield prediction, structured ASIC, FPGA interconnect
27	Manuel Saldaña, Lesley Shannon, Paul Chow	The routability of multiprocessor network topologies in FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF
27	Yan Zhang, Jussi Roivainen, Aarne Mämmelä	Clock-Gating in FPGAs: A Novel and Comparative Evaluation.	DSD	2006	DBLP DOI BibTeX RDF
27	Mike Hutton, Yan Lin 0001, Lei He 0001	Placement and Timing for FPGAs Considering Variations.	FPL	2006	DBLP DOI BibTeX RDF
27	Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann	FPGAs, GPUs and the PS2 - A Single Programming Methodology.	FCCM	2006	DBLP DOI BibTeX RDF
27	Manuel Saldaña, Lesley Shannon, Paul Chow	The routability of multiprocessor network topologies in FPGAs.	SLIP	2006	DBLP DOI BibTeX RDF	FPGA, multiprocessor, network-on-chip, topology, interconnect
27	Yan Feng, Dinesh P. Mehta	Heterogeneous Floorplanning for FPGAs.	VLSI Design	2006	DBLP DOI BibTeX RDF
27	Viktor K. Prasanna	Energy-Efficient Computations on FPGAs.	J. Supercomput.	2005	DBLP DOI BibTeX RDF	embedded signal processing, FPGA, energy efficiency, performance optimization, algorithm design
27	Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama	Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs.	ISVLSI	2005	DBLP DOI BibTeX RDF
27	Justin L. Tripp, Henning S. Mortveit, Anders A. Hansson, Maya B. Gokhale	Metropolitan Road Traffic Simulation on FPGAs.	FCCM	2005	DBLP DOI BibTeX RDF
27	Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo	Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
27	Matteo Sonza Reorda, Luca Sterpone, Massimo Violante	Efficient Estimation of SEU Effects in SRAM-Based FPGAs.	IOLTS	2005	DBLP DOI BibTeX RDF
27	Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung	CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
27	Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan	Reducing leakage energy in FPGAs using region-constrained placement.	FPGA	2004	DBLP DOI BibTeX RDF	region-constrained placement, FPGA, leakage power
27	Mark Dickinson	System-Level Design Tools Can Provide Low Cost Solutions in FPGAs: TRUE or FALSE?	FPL	2004	DBLP DOI BibTeX RDF
27	Maya B. Gokhale, Paul S. Graham, Darrel Eric Johnson, Nathan Rollins, Michael J. Wirthlin	Dynamic Reconfiguration for Management of Radiation-Induced Faults in FPGAs.	IPDPS	2004	DBLP DOI BibTeX RDF
27	Christian F. da Silva, Alice M. Tokarnia	RECASTER: Synthesis of Fault-Tolerant Embedded Systems Based on Dynamically Reconfigurable FPGAs.	IPDPS	2004	DBLP DOI BibTeX RDF
27	Sumit Mohanty, Viktor K. Prasanna	Duty Cycle Aware Application Design using FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
27	Lei Cheng 0001, Martin D. F. Wong	Floorplan design for multi-million gate FPGAs.	ICCAD	2004	DBLP DOI BibTeX RDF
27	Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante	On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs.	IOLTS	2004	DBLP DOI BibTeX RDF
27	Hyung Gyu Lee, Sungyuep Nam, Naehyuck Chang	Cycle-accurate Energy Measurement and High-Level Energy Characterization of FPGAs.	ISQED	2003	DBLP DOI BibTeX RDF
27	Fernanda Lima 0001, Luigi Carro, Ricardo Augusto da Luz Reis	Designing fault tolerant systems into SRAM-based FPGAs.	DAC	2003	DBLP DOI BibTeX RDF	fault-tolerance, FPGA
27	Francisco Cardells-Tormo, Javier Valls-Coquillat	High Performance Quadrature Digital Mixers for FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
27	Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland	Implementing Asynchronous Circuits on LUT Based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
27	Oskar Mencer	PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs.	FCCM	2002	DBLP DOI BibTeX RDF
27	Channakeshav, Kuan Zhou, Russell P. Kraft, John F. McDonald 0001	Gigahertz FPGAs with New Power Saving Techniques and Decoding Logic.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
27	Uwe Meyer-Bäse, Antonio García 0001, Fred J. Taylor	Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	field-programmable logic (FPL), complex programmable logic devices (CPLD), zero-IF filter, field programmable gate array (FPGA), digital signal processing (DSP), residue number system (RNS), channelizer
27	Kenneth Yan	Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks.	ASP-DAC	2001	DBLP DOI BibTeX RDF
27	Bruce A. Draper, A. P. Wim Böhm, Jeffrey Hammes, Walid A. Najjar, J. Ross Beveridge, Charlie Ross, Monica Chawathe, Mitesh Desai, José Bins	Compiling SA-C Programs to FPGAs: Performance Results.	ICVS	2001	DBLP DOI BibTeX RDF
27	Rajeev Jayaraman	Physical design for FPGAs.	ISPD	2001	DBLP DOI BibTeX RDF	FPGA, routing, placement, physical design
27	Michel Renovell	A Specific Test Methodology for Symmetric SRAM-Based FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
27	Jens-Peter Kaps, Christof Paar	Fast DES Implementation for FPGAs and Its Application to a Universal Key-Search Machine.	Selected Areas in Cryptography	1998	DBLP DOI BibTeX RDF
27	Scott Hauck, Matthew M. Hosler, Thomas W. Fry	High-Performance Carry Chains for FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
27	Wei Liang Huang, Fred J. Meyer, Fabrizio Lombardi	Multiple fault detection in logic resources of FPGAs.	DFT	1997	DBLP DOI BibTeX RDF	logic resources, AND tree, OR tree, CLB test generation, field programmable gate arrays, fault model, configurability, testability, programmability, multiple fault detection, SRAM-based FPGA
27	Madhav Y. Chikodikar, Shridhar Laddha, Ashish Sirasao	A Technology Mapper for Xilinx FPGAs.	VLSI Design	1997	DBLP DOI BibTeX RDF
27	Chun-Chao Yeh, Chun-Hsing Wu, Jie-Yong Juang	Design and implementation of a multicomputer interconnection network using FPGAs.	FCCM	1995	DBLP DOI BibTeX RDF
26	Jason Agron, David Andrews 0001	Building heterogeneous reconfigurable systems with a hardware microkernel.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	FPGAs, operating systems, heterogeneous architectures
26	Vincenzo Rana, Srinivasan Murali, David Atienza, Marco D. Santambrogio, Luca Benini, Donatella Sciuto	Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	FPGAs, reconfigurable computing, mapping algorithms
26	John Sachs Beeckler, Warren J. Gross	Particle graphics on reconfigurable hardware.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	FPGAs, Reconfigurable computing, particle systems, special-purpose architectures
26	Chen Huang 0005, Frank Vahid	Dynamic coprocessor management for FPGA-enhanced compute platforms.	CASES	2008	DBLP DOI BibTeX RDF	coprocessing, online algorithms., FPGAs, dynamic optimization, acceleration, runtime configuration
26	Ahmad Darabiha, W. James MacLean, Jonathan Rose	Reconfigurable hardware implementation of a phase-correlation stereoalgorithm.	Mach. Vis. Appl.	2006	DBLP DOI BibTeX RDF	Stereo disparity estimation, Frame rate implementation, Reconfigurable hardware implementation, Field Programmable Gate Arrays (FPGAs), Phase correlation
26	Tim Tuan, Sean Kao, Arifur Rahman, Satyaki Das, Steven Trimberger	A 90nm low-power FPGA for battery-powered applications.	FPGA	2006	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, low-power design, programmable logic
26	Attif A. Ibrahem, Hamed Elsimary, Aly E. Salama	FPGA Implementation of Fast Radix 4 Division Algorithm.	IWSOC	2004	DBLP DOI BibTeX RDF	fast division, radix 4 division, quotient selection, Field programmable gate arrays (FPGAs)
26	Massimo Buzzoni, Dario Cardini, Roberto Gallino, Roberto Romagnese	ATM Traffic Management Systems: ASIC Fast Prototyping.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	VHDL macrocells, FPGAs, Prototyping, ATM, Traffic Management
25	Crina Costea, Florent Bernard, Viktor Fischer, Robert Fouquet	Analysis and Enhancement of Ring Oscillators Based Physical Unclonable Functions in FPGAs.	ReConFig	2010	DBLP DOI BibTeX RDF
25	Reiner W. Hartenstein, Michael Herz, Frank Gilbert	Designing for Xilinx XC6200 FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
25	Joy Shetler, Brian Hemme, Chia Yang, Christopher Hinsz	Prototyping New ILP Architectures Using FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
25	Juri Põldre, Kalle Tammemäe, Marek Mandre	Modular Exponent Realization on FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
25	Robert Macketanz, Wolfgang Karl	JVX - A Rapid Prototyping System Based on Java and FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
25	Elena Cerro-Prada, Philip James-Roxby	High Speed Low Level Image Processing on FPGAs Using Distributed Arithmetic.	FPL	1998	DBLP DOI BibTeX RDF
25	Valery Sklyarov, Ricardo Sal Monteiro, Nuno Lau, Andreia Melo, Arnaldo S. R. Oliveira, Konstantin Kondratjuk	Integrated Development Environment for Logic Synthesis Based on Dynamically Reconfigurable FPGAs.	FPL	1998	DBLP DOI BibTeX RDF