Search results for "Interconnect"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
39	Mike Chou, Jacob K. White 0001	Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect.	ICCAD	1995	DBLP DOI BibTeX RDF	Arnoldi method, SPICE-level simulation, Taylor series terms, surface-volume methods, three-dimensional interconnect, circuit analysis computing, transient analysis, integrated circuit interconnect, integrated circuit interconnections, reduced-order modeling, reduced-order models, transient simulation, series (mathematics)
39	Amit Singh 0001, Malgorzata Marek-Sadowska	FPGA interconnect planning.	SLIP	2002	DBLP DOI BibTeX RDF
39	Dirk Stroobandt	A priori system-level interconnect prediction: Rent's rule and wire length distribution models.	SLIP	2001	DBLP DOI BibTeX RDF
39	Basab Datta, Wayne P. Burleson	Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	tunable buffer, variability, NBTI, global-interconnect
39	Xiaoxia Wu, Guangyu Sun 0003, Xiangyu Dong, Reetuparna Das, Yuan Xie 0001, Chita R. Das, Jian Li 0059	Cost-driven 3D integration with interconnect layers.	DAC	2010	DBLP DOI BibTeX RDF	interconnect service layer, three-dimensional integrated circuit, network-on-chip
39	Wenyi Feng, Sinan Kaptanoglu	Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	cluster, FPGAs, entropy, interconnect, counting, PLDs, LUT
39	DiaaEldin Khalil, Yehea I. Ismail	A global interconnect link design for many-core microprocessors.	IFMT	2008	DBLP DOI BibTeX RDF	interconnect, link, bus, repeater insertion
39	Basab Datta, Wayne P. Burleson	Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	sensor, interconnect, temperature, oscillator
39	Wenyi Feng, Sinan Kaptanoglu	Designing efficient input interconnect blocks for LUT clusters using counting and entropy.	FPGA	2007	DBLP DOI BibTeX RDF	cluster, FPGAs, entropy, interconnect, counting, PLDs, LUT
39	Naveen Muralimanohar, Rajeev Balasubramonian	Interconnect design considerations for large NUCA caches.	ISCA	2007	DBLP DOI BibTeX RDF	non-uniform cache architecture, network-on-chip, interconnect, memory hierarchies, cache models
39	Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh	Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	system-on-chip, Network-on-chip, interconnect architecture, MP-SoC, infrastructure IP
39	Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen	Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining.	DAC	2004	DBLP DOI BibTeX RDF	interconnect pipelining, statistical timing analysis
39	Magdy A. El-Moursy, Eby G. Friedman	Shielding effect of on-chip interconnect inductance.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	on-chip inductance, shielding effect, propagation delay, interconnect modeling, gate delay
39	Xiaoling Sun, A. Alimohammad, Pieter M. Trouborst	Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test Configurations.	DFT	2002	DBLP DOI BibTeX RDF	global/local interconnect testing, modeling, graph coloring, greedy algorithms, FPGA testing
39	Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang	Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning.	ISQED	2002	DBLP DOI BibTeX RDF	Interconnect-Driven Floorplanning, Performance Optimization
39	Tao Lin, Lawrence T. Pileggi	RC(L) interconnect sizing with second order considerations via posynomial programming.	ISPD	2001	DBLP DOI BibTeX RDF	RC trees, VLSI design automation, central moments, posynomiality, convex programming, interconnect optimization
39	Abby A. Ilumoka	Efficient prediction of interconnect crosstalk using neural networks.	ICTAI	2000	DBLP DOI BibTeX RDF	interconnect crosstalk prediction, deep submicron downscaling, wirecells, modular artificial neural networks, multiparadigm prototyping system, equicoupling contours, isocouples, transconductance amplifier, neural networks, delays, delay, finite element method, neural nets, crosstalk, experimental results, circuit CAD, finite element analysis, circuit simulation, circuit simulator, integrated circuit interconnections, wafer-scale integration, wafer scale integration
39	Nuno Alexandre Marques, Mattan Kamon, Jacob K. White 0001, Luís Miguel Silveira	An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models.	DATE	1998	DBLP DOI BibTeX RDF	Passive Model Order Reduction, Modified Nodal Analysis, PEEC, Extraction, Interconnect Modeling
39	Lizyamma Kurian, Daniel Brewer, Eugene John	Design of a highly reconfigurable interconnect for array processors.	VLSI Design	1995	DBLP DOI BibTeX RDF	reconfigurable interconnect, static-RAM programming technology, faulty elements, fault-tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, network topology, reconfigurable architectures, array processors, interconnection topologies, mesh topologies
39	Jung-Cheun Lien, Melvin A. Breuer	An optimal scheduling algorithm for testing interconnect using boundary scan.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	Boundary scan, test scheduling, interconnect test
38	Manuel Sellier, Jean-Michel Portal, Bertrand Borot, Steve Colquhoun, Richard Ferrant, Frédéric Boeuf, Alexis Farcy	Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework.	ISQED	2008	DBLP DOI BibTeX RDF	Predictive SPICE Modeling, Interconnect Resistance, Buffer Insertion, Interconnect Delay
38	Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De	Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.	ISLPED	2006	DBLP DOI BibTeX RDF	intra-die variations, multi-cycle interconnect, parameter fluctuations, time borrowing, interconnect, parameter variations, within-die variations, variation tolerant
38	Jifeng Chen, Jin Sun 0006, Janet Meiling Wang	Robust interconnect communication capacity algorithm by geometric programming.	ISPD	2009	DBLP DOI BibTeX RDF	communication capacity, optimization, robust, uncertainty, process variation, geometric programming, ellipsoid
38	Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton	Practical Asynchronous Interconnect Network Design.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
38	Andrew Labun, Karan Jagjitkumar	Rapid Detailed Temperature Estimation for Highly Coupled IC Interconnect.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
38	Md. Sajjad Rahaman, Masud H. Chowdhury	Time diversity approach for intra-chip RF/wireless interconnect systems.	ISCAS	2008	DBLP DOI BibTeX RDF
38	Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown	Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
38	Ian O'Connor, Faress Tissafi-Drissi, Frédéric Gaffiot, Joni Dambre, Michiel De Wilde, Jan Van Campenhout, Dries Van Thourhout, Dirk Stroobandt	Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
38	Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud	Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures.	ISVLSI	2007	DBLP DOI BibTeX RDF
38	Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong	Interconnect Power Optimization Based on Timing Analysis.	ISVLSI	2007	DBLP DOI BibTeX RDF
38	Zhipeng Liu, Jinian Bian, Qiang Zhou 0001, Hui Dai	Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan.	ISVLSI	2007	DBLP DOI BibTeX RDF
38	Vineet Agarwal, Jin Sun 0006, Alexander V. Mitev, Janet Meiling Wang	Delay Uncertainty Reduction by Interconnect and Gate Splitting.	ASP-DAC	2007	DBLP DOI BibTeX RDF
38	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding.	ISCAS	2007	DBLP DOI BibTeX RDF
38	Arthur Nieuwoudt, Yehia Massoud	Assessing the Implications of Process Variations on Future Carbon Nanotube Bundle Interconnect Solutions.	ISQED	2007	DBLP DOI BibTeX RDF
38	Navneeth Kankani, Vineet Agarwal, Janet Meiling Wang	A probabilistic analysis of pipelined global interconnect under process variations.	ASP-DAC	2006	DBLP DOI BibTeX RDF
38	Krishnamoorthy Natarajan, S. J. Nagalakshmi	Repeater Sizing and Insertion Length of Interconnect to Minimize the Overall Time Delay using a Truncated Fourier Series Approach.	CCECE	2006	DBLP DOI BibTeX RDF
38	Lin Zhong 0001, Niraj K. Jha	Interconnect-aware low-power high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
38	Rohini Krishnan, R. I. M. P. Meijer, Durand Guillaume	Energy-efficient FPGA interconnect architecture design (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
38	Yan Lin 0001, Fei Li 0003, Lei He 0001	Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction.	ASP-DAC	2005	DBLP DOI BibTeX RDF
38	Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen	Wave-pipelined on-chip global interconnect.	ASP-DAC	2005	DBLP DOI BibTeX RDF
38	Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton	Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow.	ICCD	2005	DBLP DOI BibTeX RDF
38	Andres Teene, Bob Davis, Ruggero Castagnetti, Jeff Brown, S. Ramesh 0004	Impact of Interconnect Process Variations on Memory Performance and Design.	ISQED	2005	DBLP DOI BibTeX RDF
38	John Shalf, Shoaib Kamil 0001, Leonid Oliker, David Skinner	Analyzing Ultra-Scale Application Communication Requirements for a Reconfigurable Hybrid Interconnect.	SC	2005	DBLP DOI BibTeX RDF
38	Francky Catthoor, Andrea Cuomo, Grant Martin, Patrick Groeneveld, Rudy Lauwereins, Karen Maex, Patrick van de Steeg, Ron Wilson	How Can System-Level Design Solve the Interconnect Technology Scaling Problem?	DATE	2004	DBLP DOI BibTeX RDF
38	N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara	Interconnect Modeling for Copper/Low-k Technologies.	VLSI Design	2004	DBLP DOI BibTeX RDF
38	Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick	Encoded-Low Swing Technique for Ultra Low Power Interconnect.	FPL	2003	DBLP DOI BibTeX RDF
38	PariVallal Kannan, Dinesh Bhatia	Interconnect Estimation for FPGAs under Timing Driven Domains.	ICCD	2003	DBLP DOI BibTeX RDF
38	Payman Zarkesh-Ha, S. Lakshminarayann, Ken Doniger, William Loh, Peter Wright	Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow.	ISQED	2003	DBLP DOI BibTeX RDF
38	Martijn T. Bennebroek	Validation of wire length distribution models on commercial designs.	SLIP	2003	DBLP DOI BibTeX RDF
38	Ankireddy Nalamalpu, Sriram Srinivasan, Wayne P. Burleson	Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
38	Ian G. Harris, Russell Tessier	Testing and diagnosis of interconnect faults in cluster-based FPGA architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
38	Lin Zhong 0001, Niraj K. Jha	Interconnect-aware high-level synthesis for low power.	ICCAD	2002	DBLP DOI BibTeX RDF
38	Vikas Mehrotra, Shiou Lin Sam, Duane S. Boning, Anantha P. Chandrakasan, Rakesh Vallishayee, Sani R. Nassif	A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance.	DAC	2000	DBLP DOI BibTeX RDF
38	Jason Cong, Lei He 0001	Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
38	Anirudh Devgan, Peter R. O'Brien	Realizable reduction for RC interconnect circuits.	ICCAD	1999	DBLP DOI BibTeX RDF
38	Lizy Kurian John, E. John	A dynamically reconfigurable interconnect for array processors.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
38	Wolf-Dietrich Weber, Stephen Gold, Pat Helland, Takeshi Shimizu, Thomas Wicki, Winfried W. Wilcke	The Mercury Interconnect Architecture: A Cost-effective Infrastructure for High-performance Servers.	ISCA	1997	DBLP DOI BibTeX RDF
38	Curtis L. Ratzlaff, Lawrence T. Pillage	RICE: rapid interconnect circuit evaluation using AWE.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
38	Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai	Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	interconnect, power, SMP, cache coherence protocol
37	Ajay Joshi, Gerald G. Lopez, Jeffrey A. Davis	Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
37	Qi Zhu 0002, Hai Zhou 0001, Tong Jing, Xianlong Hong, Yang Yang 0040	Spanning graph-based nonrectilinear steiner tree algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
34	Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl	Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session).	SLIP	2000	DBLP DOI BibTeX RDF
34	Jason Cong, Mau-Chung Frank Chang, Glenn Reinman, Sai-Wang Tam	Multiband RF-interconnect for reconfigurable network-on-chip communications.	SLIP	2009	DBLP DOI BibTeX RDF	fdma, morfic, rf-interconnect, network-on-chip, reconfigurable, chip multiprocessor
34	Dae Hyun Kim 0004, Saibal Mukhopadhyay, Sung Kyu Lim	Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs.	SLIP	2009	DBLP DOI BibTeX RDF	wirelength distribution, rent's rule, 3d ic, tsv, interconnect prediction, through silicon via
34	Prashant Saxena	The scaling of interconnect buffer needs.	SLIP	2006	DBLP DOI BibTeX RDF	interconnect, scaling, buffers, repeaters
34	J. Balachandran, Steven Brebels, Geert Carchon, Maarten Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne	Constant impedance scaling paradigm for interconnect synthesis.	SLIP	2006	DBLP DOI BibTeX RDF	transmission lines, interconnect optimization, global interconnects
34	Tao Wan, Malgorzata Chrzanowska-Jeske	Prediction of interconnect net-degree distribution based on Rent's rule.	SLIP	2004	DBLP DOI BibTeX RDF	net-degree distribution, Rent's rule, interconnect prediction
34	Ganapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee 0001, Amit Singh 0001	Interconnect complexity-aware FPGA placement using Rent's rule.	SLIP	2001	DBLP DOI BibTeX RDF	Rent's exponent, interconnect, placement
34	Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl	Prediction of interconnect fan-out distribution using Rent's rule.	SLIP	2000	DBLP DOI BibTeX RDF	fan-out distribution, interconnect network prediction, Rent's rule
34	Louis Scheffer, Eric Nequist	Why interconnect prediction doesn't work.	SLIP	2000	DBLP DOI BibTeX RDF	constructive estimation, wire load model, interconnect prediction
34	Sunghoon Chun, YongJoon Kim, Sungho Kang 0001	MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	RLC interconnect model, fault modeling, signal integrity, interconnect test
34	Jae-sun Seo, Dennis Sylvester, David T. Blaauw, Himanshu Kaul, Ram Krishnamurthy 0001	A robust edge encoding technique for energy-efficient multi-cycle interconnect.	ISLPED	2007	DBLP DOI BibTeX RDF	multi-cycle interconnect, interconnect, encoding, repeaters
34	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko	Yield enhancements of design-specific FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	design-specific FPGA, interconnect faults, interconnect utilization, yield enhancement, yield prediction, structured ASIC, FPGA interconnect
33	Duo Ding, David Z. Pan	OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture.	SLIP	2009	DBLP DOI BibTeX RDF	photonic networks-on-chip, low power, computer aided design, high performance
33	Alexander V. Mitev, Michael M. Marefat, Dongsheng Ma, Janet Meiling Wang	Principle hessian direction based parameter reduction for interconnect networks with process variation.	SLIP	2007	DBLP DOI BibTeX RDF	principle Hessian directions, process variation, timing analysis
33	Shih-Hsu Huang	An effective low power design methodology based on interconnect prediction.	SLIP	2001	DBLP DOI BibTeX RDF
33	Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu 0001	Interconnect implications of growth-based structural models for VLSI circuits.	SLIP	2001	DBLP DOI BibTeX RDF
33	Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet	Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing
33	Joseph B. Cessna, Thomas R. Bewley	Honeycomb-structured computational interconnects and their scalable extension to spherical domains.	SLIP	2009	DBLP DOI BibTeX RDF	switchless interconnect, graph theory
33	Zhuo Li 0001, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia	Fast interconnect synthesis with layer assignment.	ISPD	2008	DBLP DOI BibTeX RDF	buffer insertion, wire sizing, layer assignment, interconnect synthesis
33	Jin Guo 0001, Antonis Papanikolaou, Michele Stucchi, Kristof Croes, Zsolt Tokei, Francky Catthoor	A tool flow for predicting system level timing failures due to interconnect reliability degradation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	system degradation, system level failures, interconnect reliability
33	Farshad Safaei, Ahmad Khonsari, Mahmood Fathy, Mohamed Ould-Khaoua	Analysis of Circuit Switching for the Torus Interconnect Networks with Hot-Spot Traffic.	ICPP Workshops	2006	DBLP DOI BibTeX RDF	Hot-spot traffic, Queuing theory and Performance evaluation, Parallel computers, Interconnect networks, Torus, Circuit switching
33	W. T. Cheung, N. Wong	Power optimization in a repeater-inserted interconnect via geometric programming.	ISLPED	2006	DBLP DOI BibTeX RDF	optimization, interconnect, power, repeater, geometric programming
33	Haibin Shen, Rongquan You, Yier Jin, Aiming Ji	Interconnect Estimation for Mesh-Based Reconfigurable Computing.	EUC	2006	DBLP DOI BibTeX RDF	mesh-based, probability, Interconnect, reconfigurable computing
33	Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa	Interconnect capacitance extraction for system LCD circuits.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	interconnect capacitance, system LCD, capacitance extraction
33	Ronald P. Luijten, Cyriel Minkenberg, B. Roe Hemenway, Michael Sauer, Richard Grzybowski	Viable opto-electronic HPC interconnect fabrics.	SC	2005	DBLP DOI BibTeX RDF	Interconnect, Switching, HPC, Optical Switching
33	Chiu-Wing Sham, Evangeline F. Y. Young	Congestion prediction in early stages.	SLIP	2005	DBLP DOI BibTeX RDF	placement, floorplanning, interconnect estimation
33	Jason Cong, Yiping Fan, Zhiru Zhang	Architecture-level synthesis for automatic interconnect pipelining.	DAC	2004	DBLP DOI BibTeX RDF	interconnect pipelining, multi-cycle communication, scheduling, high-level synthesis, register binding
33	John F. Croix, D. F. Wong 0001	Blade and razor: cell and interconnect delay analysis using current-based models.	DAC	2003	DBLP DOI BibTeX RDF	blade, current-based model, razor, recursive convolution, timing analysis, interconnect model, cell model
33	Iain Gourlay, Peter M. Dew, Karim Djemame	Bulk Synchronous Parallel Computing Using a High Bandwidth Optical Interconnect.	IPDPS	2002	DBLP DOI BibTeX RDF	Bulk Synchronous Parallelism (BSP), performance evaluation, Parallel architecture, optical interconnect, parallel sorting
33	Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim	Analytical signal integrity verification models for inductance-dominant multi-coupled VLSI interconnects.	SLIP	2002	DBLP DOI BibTeX RDF	TWA, signal integrity verification, delay, crosstalk, ringing, signal integrity, transmission line, glitch, VLSI interconnect, traveling-wave
33	Raymond A. Wildman, Joshua I. Kramer, Daniel S. Weile, Phillip Christie	Wire layer geometry optimization using stochastic wire sampling.	SLIP	2002	DBLP DOI BibTeX RDF	genetic algorithms, optimization, interconnect, Rent's rule
33	Phillip J. Restle, Albert E. Ruehli, Steven G. Walker	Multi-GHz interconnect effects in microprocessors.	ISPD	2001	DBLP DOI BibTeX RDF	full-wave analysis, simulation, interconnect, inductance, extraction, clock distribution, circuit-tuning
33	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for Combinational Cluster Interconnect Testing at Board Level.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	cluster testing, built-in self-test, BIST, boundary scan, interconnect testing
33	Vinay Dabholkar, Sreejit Chakravarty	Computing stress tests for interconnect defects.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	interconnect defects, reliability screens, infant mortality, gate-oxide defects, integrated circuit testing, stress tests
33	Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara	A Test Methodology for Interconnect Structures of LUT-based FPGAs.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	Programmable Interconnect Structures, Cross Point Switch, Configurable Logic Block, FPGA, Test Pattern Generation
33	Mongkol Raksapatcharawong, Timothy Mark Pinkston	An Optical Interconnect Model for k-ary n-cube Wormhole Networks.	IPPS	1996	DBLP DOI BibTeX RDF	free-space optical interconnects, optical interconnect model, performance evaluation, wormhole switching, k-ary n-cube networks
33	Mustafa Celik, Andreas C. Cangellaris	A general dispersive multiconductor transmission line model for interconnect simulation in SPICE.	ICCAD	1996	DBLP DOI BibTeX RDF	multiconductor transmission lines, interconnect simulation, Chebyshev approximation, SPICE, transient analysis
33	Wei-Kang Huang, Xiao-Tao Chen, Fabrizio Lombardi	On the diagnosis of programmable interconnect systems: Theory and application.	VTS	1996	DBLP DOI BibTeX RDF	field programmable interconnect system, switch grid, FPIS, Xilinx 3000, field programmable gate arrays, FPGA, fault diagnosis, logic testing, diagnosis, integrated circuit interconnections
33	Anirudh Devgan, Ronald A. Rohrer	Efficient simulation of interconnect and mixed analog-digital circuits in ACES.	VLSI Design	1995	DBLP DOI BibTeX RDF	adaptively controlled explicit simulation, mixed analog-digital circuits, analog circuit simulation, interconnect circuit simulation, AWE macromodels, nonlinear terminations, variable accuracy device models, circuit topology constraints removal, timing, circuit analysis computing, transient analysis, analogue integrated circuits, integrated circuit interconnections, mixed analogue-digital integrated circuits, ACES, transient simulation, timing simulation