Search results for "VLSI"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
39	Tonia G. Morris, Denise M. Wilson, Stephen P. DeWeerth	Analog VLSI circuits for manufacturing inspection.	ARVLSI	1995	DBLP DOI BibTeX RDF	analog VLSI circuits, manufacturing inspection, programmable structuring elements, oriented edge detection, high speed preprocessors, serial/parallel processing, focal-plane processing, vertical bipolar phototransistors, digital CMOS process, adaptive image threshold, 2.0 micron, computer vision, VLSI, edge detection, mathematical morphology, machine vision, manufacture, morphological operations, selective attention, massively parallel architectures, CMOS analogue integrated circuits, automatic optical inspection, focal planes, analogue processing circuits
38	Pradeep Fernando, Srinivas Katkoori	An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning.	VLSI Design	2008	DBLP DOI BibTeX RDF
38	Qianneng Zhou, Fengchang Lai, Yongsheng Wang	On-Chip Voltage Down Converter Based on Moderate Inversion for Low- Power VLSI Chips.	VLSI Design	2007	DBLP DOI BibTeX RDF
38	Chitranjan K. Singh, Sushma Honnavara Prasad, Poras T. Balsara	VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition.	VLSI Design	2007	DBLP DOI BibTeX RDF
38	Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary	A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes.	VLSI Design	2007	DBLP DOI BibTeX RDF
38	Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan	Area and Power Efficient VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System.	VLSI Design	2006	DBLP DOI BibTeX RDF
38	Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla	Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters.	VLSI Design	2006	DBLP DOI BibTeX RDF
38	Gurpreet Shinh, Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Ihsan Erdin	Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks.	VLSI Design	2006	DBLP DOI BibTeX RDF
38	Naga M. Kosaraju, Murali R. Varanasi, Saraju P. Mohanty	A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm.	VLSI Design	2006	DBLP DOI BibTeX RDF
38	Parthasarathi Dasgupta	Revisiting VLSI Interconnects in Deep Sub-Micron: Some Open Questions.	VLSI Design	2005	DBLP DOI BibTeX RDF
38	Masahiro Fujita	Formal Verification of C Language Based VLSI Designs.	VLSI Design	2004	DBLP DOI BibTeX RDF
38	Gautam Hazari, Madhav P. Desai, Apoorv Gupta, Supratik Chakraborty	A Novel Technique Towards Eliminating the Global Clock in VLSI Circuits.	VLSI Design	2004	DBLP DOI BibTeX RDF
38	Manvendra Singh, B. S. Chauhan, N. K. Sharma	VLSI Architecture of Centroid Tracking Algorithms for Video Tracker.	VLSI Design	2004	DBLP DOI BibTeX RDF
38	Ashis Kumar Mal, Anindya Sundar Dhar	Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors.	VLSI Design	2004	DBLP DOI BibTeX RDF
38	A. Vasudevan	Advances in VLSI Design and Product Development Challenges.	VLSI Design	2003	DBLP DOI BibTeX RDF
38	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi	A Framework for Design Space Exploration of Parameterized VLSI Systems.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
38	P. K. Datta, S. Sanyal, D. Bhattacharya	Losses in Multilevel Crossover in VLSI Interconnects.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
38	Alexander Worm, Holger Lamm, Norbert Wehn	Vlsi Architectures For High-Speed Map Decoders.	VLSI Design	2001	DBLP DOI BibTeX RDF
38	Dilip K. Bhavsar, Rishan Tan	Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits.	VLSI Design	2001	DBLP DOI BibTeX RDF
38	Biplab K. Sikdar, Purnabha Majumder, Parimal Pal Chaudhuri, Niloy Ganguly	Design Of Multiple Attractor Gf (2p) Cellular AutomataFor Diagnosis Of Vlsi Circuits.	VLSI Design	2001	DBLP DOI BibTeX RDF
38	Sabyasachi Dey 0003, Bhargab B. Bhattacharya, Malay Kumar Kundu, Tinku Acharya	A Fast Algorithm for Computing the Euler Number of an Image and its VLSI Implementation.	VLSI Design	2000	DBLP DOI BibTeX RDF
38	Amr G. Wassal, M. Anwarul Hasan	A VLSI Architecture for ATM Algorithm-Agile Encryption.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
38	Aamir A. Farooqui, Vojin G. Oklobdzija	VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
38	Lim Chu Aun, S. M. Rezaul Hasan	An all Digital BiCMOS Phase Lock Loop for VLSI Processors.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
38	José Francisco López, Roberto Sarmiento, Antonio Núñez, Kamran Eshraghian, Stefan Lachowicz, Derek Abbott	Low Power Techniques for Digital GaAs VLSI.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
38	Bulent Basaran, Kiran Ganesh, Raymond Y. K. Lau, Artour Levin, Miles McCoo, Srinivasan Rangarajan, Naresh Sehgal	GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs.	VLSI Design	1999	DBLP DOI BibTeX RDF
38	José G. Delgado-Frias, Jabulani Nyathi	A VLSI High-Performance Encoder with Priority Lookahead.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Priority lookahead, Dynamic circuitry, Priority encoder, Precharge circuitry, Critical path
38	Azman M. Yusof, Lim Chu Aun, S. M. Rezaul Hasan	600 MHz Digitally Controlled BiCMOS Oscillator (DCO) for VLSI Signal Processing & Communication Applications.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF
38	Andreas G. Veneris, Ibrahim N. Hajj	A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
38	Fabio Ancona, Giorgio Oddone, Stefano Rovetta, Gianni Uneddu, Rodolfo Zunino	VLSI Architectures for Programmable Sorting of Analog Quantities with Multiple-Chip Support.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
38	Pinaki Mazumdar	Parallel VLSI-Routing Models for Polymorphic Processors Array.	VLSI Design	1997	DBLP DOI BibTeX RDF
38	Palash Sarkar 0001, Bimal K. Roy, Pabitra Pal Choudhury	VLSI Implementation of Modulo Multiplication Using Carry Free Addition.	VLSI Design	1997	DBLP DOI BibTeX RDF
38	José G. Delgado-Frias, Jabulani Nyathi, Chester L. Miller, Douglas H. Summerville	A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	Content addressable memory (CAM) Router, Hidden refresh circuitry, Parallel matching, Per-entry unique bit masking, Interconnection networks
38	Hormoz Djahanshahi, Majid Ahmadi, Graham A. Jullien, William C. Miller	Design and VLSI Implementation of a Unified Synapse-Neuron Architecture.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
38	Nozar Tabrizi, Michael J. Liebelt, Kamran Eshraghian	Delay Hazards in Complex Gate Based Speed Independent VLSI Circuits.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	isochronic forks, speed independent circuits (SICs), Asynchronous circuits, signal transition graphs (STGs), hazards
38	Paul Shipley, Sherif Sayed, Magdy A. Bayoumi	A High Speed VLSI Architecture for Scaleable ATM Switches.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
38	M. P. Sebastian, P. S. Nagendra Rao, Lawrence Jenkins	VLSI/WSI Designs for Folded Cube-Connected Cycles Architectures.	VLSI Design	1996	DBLP DOI BibTeX RDF	Building block design, fault-tolerance, reliability, parallel architecture, layout, yield
38	Andrew B. Kahng, Kei Masuko, Sudhakar Muddu	Analytical delay models for VLSI interconnects under ramp input.	ICCAD	1996	DBLP DOI BibTeX RDF	SPICE-computed delay, VLSI routing topologies layout, analytical delay models, arbitrary interconnect trees, interconnect transfer function, performance-driven synthesis, ramp input, source-sink delays, VLSI, Elmore delay, interconnect delays, VLSI interconnects, RLC interconnections
38	Bjørn Olstad, Erik Steen, Arne Halaas	Image filtering techniques and VLSI architectures for efficient data extraction in shell rendering.	ICIP	1995	DBLP DOI BibTeX RDF	image filtering techniques, shell rendering, interactive data reduction, real-time data reduction, PCI based search engine, full custom VLSI chip, opacity assignment, multi-spectral voxel data, interactive inspection procedures, 3D imagery, 3D ultrasonics, 3D MRI studies, classification, VLSI, feature extraction, volume rendering, image classification, application specific integrated circuits, medical image processing, search problems, VLSI architectures, filtering theory, data reduction, digital signal processing chips, data extraction, rendering (computer graphics), biomedical NMR, image preprocessing, biomedical ultrasonics
38	Antonio J. Acosta 0001, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas	New CMOS VLSI linear self-timed architectures.	ASYNC	1995	DBLP DOI BibTeX RDF	semiconductor storage, CMOS VLSI linear self-timed architectures, digital signal processor circuits, self-timed techniques, synchronous VLSI circuits, FIFO memories, VLSI, asynchronous circuits, asynchronous circuits, digital signal processing chips, CMOS memory circuits, hardware resources
38	Yang Sun 0001, Joseph R. Cavallaro	High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	mimo detection, VLSI architecture, ASIC design
38	Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman 0001, Dhiraj K. Pradhan	Single Error Correcting Finite Field Multipliers Over GF(2m).	VLSI Design	2008	DBLP DOI BibTeX RDF	Galois Field Multiplier, VLSI, Cryptography, Error Correcting Codes
38	Shen Li, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto	A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for H.264/avc.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	fast intra prediction mode decision, H.264, VLSI architecture
38	Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi	Equidistance routing in high-speed VLSI layout design.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	box routing, equidistance routing, rectilinear route, slant symmetric grid, dynamic programming, VLSI system, channel routing
38	Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin 0001	A memory aware behavioral synthesis tool for real-time VLSI circuits.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	memory aware, behavioral synthesis, VLSI circuits
38	Menahem Lowy, Neal Butler, Rosanne Tinkler	Low power VLSI sequential circuit architecture using critical race control.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	critical races, low-power VLSI circuits, asynchronous circuits
38	Falah R. Awwad, Mohamed Nekili	Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	parallel regeneration, VLSI, repeater, RLC interconnect
38	Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee	Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator.	VLSI Design	2000	DBLP DOI BibTeX RDF	Extension field, BIST structure, Cellular Automata (CA), VLSI design and RTL, Finite field, DFT, Fault coverage, LFSR
38	Dale E. Hocevar, Ching-Yu Hung, Dan Pickens, Sundararajan Sriram	Top-Down Design Using Cycle Based Simulation: an MPEG A/V Decoder Example.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Cycle based simulation, CAD, Performance modeling, MPEG, VLSI Design, Hardware/Software Co-design, System Simulation, Top-Down
38	Wen-Ben Jone, Sunil R. Das	A Stochastic Method for Defect Level Analysis of Pseudorandom Testing.	VLSI Design	1998	DBLP DOI BibTeX RDF	defect level analysis, differential equation, VLSI testing, pseudorandom testing
38	Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee	Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation.	VLSI Design	1997	DBLP DOI BibTeX RDF	simulation-based test generation, distributed memory MIMD machines, shared memory MIMD machines, parallel search strategies, logic testing, fault coverage, NP-complete problems, VLSI circuits, parallel genetic algorithms, sequential circuit test generation
38	Chittaranjan A. Mandal, P. P. Chakrabarti 0001, Sujoy Ghose	Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach.	VLSI Design	1996	DBLP DOI BibTeX RDF	Multi-port Memory, Genetic Algorithm, VLSI, Binding, Data Path Synthesis
37	Haque Mohammad Munirul, Michitaka Kameyama	Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit.	ISMVL	2006	DBLP DOI BibTeX RDF
37	Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata	A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture.	KES	2003	DBLP DOI BibTeX RDF
37	W. A. Dees, K. M. Parmar, A. Goyal, Raymond Y. Tsui, B. D. Rathi, Robert J. Smith 0001	A computer-aided VLSI layout system.	AFIPS National Computer Conference	1981	DBLP DOI BibTeX RDF
36	William J. Dally, Steve Lacy	VLSI Architecture: Past, Present, and Future.	ARVLSI	1999	DBLP DOI BibTeX RDF
36	Shantanu Dutt, Wenyong Deng	Cluster-aware iterative improvement techniques for partitioning large VLSI circuits.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	VLSI circuit partitioning, mincut, physical design/layout, Clusters, iterative-improvement
35	Sheu-Chih Cheng, Hsueh-Ming Hang	The Impact of Rate Control Algorithms on System-Level VLSI Design.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
35	Jinsang Kim, Tom Chen 0001	A VLSI Architecture for Image Sequence Segmentation using Edge Fusion.	CAMP	2000	DBLP DOI BibTeX RDF	image sequence segmentation, edge fusion, VLSI edge fusion architecture, segmentation, image sequences, image sequences, VLSI architecture, complexity analysis, gray level
35	Chih-Wen Lu, Chauchin Su, Chung-Len Lee 0001, Jwu E. Chen	Is IDDQ testing not applicable for deep submicron VLSI in year 2011?	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	deep submicron VLSI, IDDQ current estimation, random process deviations, IDDQ distributions, VLSI, statistical analysis, integrated circuit testing, CMOS integrated circuits, leakage currents, IDDQ testing, statistical approach, standard deviation, input vectors, circuit size
35	Bhaskar Saha, J. Sukarno Mertoguno, Nikolaos G. Bourbakis	The VLSI design and implementation of the array processors of a multilayer vision system architecture.	ASAP	1995	DBLP DOI BibTeX RDF	multilayer vision system architecture, KYDON vision system, multilayered image understanding system, computer vision, parallel processing, VLSI, digital simulation, VLSI design, array processors, timing simulation
35	Andreas G. Andreou, Kwabena A. Boahen	A 590, 000 transistor 48, 000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retina.	ARVLSI	1995	DBLP DOI BibTeX RDF	silicon retina, analog VLSI focal plane processor, phototransduction, local gain control, single chip system, vertebrate distal retina, ultra low power dissipation, n-well double metal double poly digital oriented CMOS technology, current-mode subthreshold CMOS, 48000 pixel, computer vision, VLSI, edge detection, CMOS integrated circuits, image sensors, contrast, edge enhancement, CMOS imager, focal planes, area efficiency, 1.2 micron
34	Ajit Pal, Santanu Chattopadhyay	Synthesis & Testing for Low Power.	VLSI Design	2009	DBLP DOI BibTeX RDF
34	Debasri Saha, Susmita Sur-Kolay	Encoding of Floorplans through Deterministic Perturbation.	VLSI Design	2009	DBLP DOI BibTeX RDF
34	Nikil D. Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha	Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends.	VLSI Design	2007	DBLP DOI BibTeX RDF
34	Se Hun Kim, Vincent John Mooney	Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
34	Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang	High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header.	VLSI Design	2006	DBLP DOI BibTeX RDF
34	Lin Yuan, Gang Qu 0001, Ankur Srivastava 0001	VLSI CAD tool protection by birthmarking design solutions.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	birthmarking, CAD, protection, intellectual property
34	Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal	A novel ultra-fast heuristic for VLSI CAD steiner trees.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	routing, steiner trees, interconnect estimation
34	Rajiv V. Joshi, Kaushik Roy 0001	Design of Deep Sub-Micron CMOS Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF
34	Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji	Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
34	Basant Rajan, R. K. Shyamasundar	Modeling VHDL in Multiclock ESTEREL.	VLSI Design	2000	DBLP DOI BibTeX RDF
34	Swarup Bhunia, Soumya K. Ghosh 0001, Pramod Kumar, Partha Pratim Das, Jayanta Mukherjee 0001	Design, Simulation and Synthesis of an ASIC for Fractal Image Compression.	VLSI Design	1999	DBLP DOI BibTeX RDF
34	C. P. Ravikumar, Ajay Mittal	Hierarchical Delay Fault Simulation.	VLSI Design	1999	DBLP DOI BibTeX RDF
34	Ananta K. Majhi, Vishwani D. Agrawal	Tutorial: Delay Fault Models and Coverage.	VLSI Design	1998	DBLP DOI BibTeX RDF	delay fault models, gate delay model, line delay model, path delay model, segment delay model, transition model, Delay test
34	Fan Xu, Guichang Zhong, Alan N. Willson Jr.	Analysis and VLSI Realization of a Blind Beamforming Algorithm.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	blind beamforming, VLSI architecture, eigenvector, multi-processor, power method
34	Warren J. Gross, Frank R. Kschischang, Ralf Koetter, P. Glenn Gulak	Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	Reed-Solomon decoders, Sudan's algorithm, Guruswami-Sudan algorithm, Koetter-Vardy algorithm, Hasse derivative, VLSI architectures, list decoding, polynomial interpolation, soft-decision decoding
34	Adhir Upadhyay, Syed Rafay Hasan, Mohamed Nekili	Optimal partitioning of globally asychronous locally synchronous processor arrays.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	VLSI, partitioning, power optimization, GALS
34	Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang	Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	multiuser channel estimation, VLSI, DSP, fixed-point, dependence graphs, W-CDMA, real-time implementation
34	Francesco Gregoretti, Roberto Passerone, Leonardo Maria Reyneri, Claudio Sansoè	A High Speed VLSI Architecture for Handwriting Recognition.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	image processing, parallel architectures, artificial neural networks, handwriting recognition, VLSI implementations
34	Anne E. Gattiker, Wojciech Maly	Current signatures [VLSI circuit testing].	VTS	1996	DBLP DOI BibTeX RDF	VLSI circuit testing, current signature, passive defects, active defects, VLSI, integrated circuit testing, CMOS integrated circuits, I/sub DDQ/ testing
34	Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel	Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.	VTS	1996	DBLP DOI BibTeX RDF	GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm
34	Santanu Dutta, Wayne H. Wolf, Andrew Wolfe	VLSI issues in memory-system design for video signal processors.	ICCD	1995	DBLP DOI BibTeX RDF	VLSI issues, video signal processors, memory-system architectures, circuit-level issues, register-cache based hierarchy, general-purpose programmable microprocessors, VLSI, system architecture, utilization, memory architecture, memory architecture, video signal processing, area, cycle time, memory-system design
34	Mohamed Soufi, Yvon Savaria, Bozena Kaminska	On the design of at-speed testable VLSI circuits.	VTS	1995	DBLP DOI BibTeX RDF	at-speed testable circuits, testable VLSI circuits, application test time, parallel vectors, stuck-at test, observability problems, probe observation point, VLSI, logic testing, integrated circuit testing, design for testability, design-for-testability, logic design, sequential circuits, sequential circuits, observability, fault coverages, integrated circuit design, integrated logic circuits, operational speed, DFT technique
34	Tülin Erdim Mangir, Algirdas Avizienis	Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	VLSI fault tolerance, Interconnect area estimates, redundancy partitioning, redundancy placement, regular designs, VLSI yield improvement
34	Daisuke Kobayashi, Kazuyuki Hirose	How Harsh is Space?-Equations That Connect Space and Ground VLSI.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
34	Parthasarathy Ranganathan	A Six-Word Story on the Future of VLSI: AI-driven, Software-defined, and Uncomfortably Exciting.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
34	Swaroop Ghosh	Session details: Session 5B: VLSI Design + VLSI Circuits and Power Aware Design 2.	ACM Great Lakes Symposium on VLSI	2022	DBLP DOI BibTeX RDF
34	Saraju P. Mohanty	Session details: Session 3A: VLSI Design + VLSI Circuits and Power Aware Design 1.	ACM Great Lakes Symposium on VLSI	2022	DBLP DOI BibTeX RDF
34	Tsung-Wei Huang	Programming Systems for Parallelizing VLSI CAD and Beyond.	VLSI-DAT	2020	DBLP DOI BibTeX RDF
34	Chia-Hsiang Yang	Massive MIMO detection VLSI design.	VLSI-DAT	2018	DBLP DOI BibTeX RDF
34	Ricardo Reis 0001, Manfred Glesner	VLSI-SoC: An Enduring Tradition.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
34	Matthias Thiele, Steve Bigalke, Jens Lienig	Electromigration Analysis of VLSI Circuits Using the Finite Element Method.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
34	Ren C. Luo	World megatrend of intelligent robotics and AI: Impact on VLSI-DAT.	VLSI-DAT	2017	DBLP DOI BibTeX RDF
34	Chih-Wei Lee, Hwa-Yi Tseng, Chi-Lien Kuo, Chien-Nan Jimmy Liu, Chin Hsia	Layout placement optimization with isolation rings for high-voltage VLSI circuits.	VLSI-DAT	2017	DBLP DOI BibTeX RDF
34	Hao Yu 0001	Energy efficient VLSI circuits for machine learning on-chip.	VLSI-DAT	2017	DBLP DOI BibTeX RDF
34	Rahul Shrestha	High-speed and low-power VLSI-architecture for inexact speculative adder.	VLSI-DAT	2017	DBLP DOI BibTeX RDF
34	Jheng-Jhan He, Chih-Peng Fan	Design and VLSI implementation of novel pre-screening and simplified sorting based K-best detection for MIMO systems.	VLSI-DAT	2015	DBLP DOI BibTeX RDF
34	Dominik Auras, Uwe Deidersen, Rainer Leupers, Gerd Ascheid	A Parallel MCMC-Based MIMO Detector: VLSI Design and Algorithm.	VLSI-SoC (Selected Papers)	2014	DBLP DOI BibTeX RDF
34	Shen-Fu Hsiao, Wen-Ling Wang, Po-Sheng Wu	VLSI implementations of stereo matching using Dynamic Programming.	VLSI-DAT	2014	DBLP DOI BibTeX RDF