Search results for "circuit"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
27	Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya	A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
27	Takao Konishi, Naohiro Hamada, Hiroshi Saito	A Control Circuit Synthesis Method for Asynchronous Circuits in Bundled-Data Implementation.	CIT	2007	DBLP DOI BibTeX RDF
27	Hanif Fatemi, Shahin Nazarian, Massoud Pedram	A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms.	ASP-DAC	2007	DBLP DOI BibTeX RDF
27	Baohua Wang, Pinaki Mazumder	Optimization of circuit trajectories: an auxiliary network approach.	ASP-DAC	2006	DBLP DOI BibTeX RDF
27	Wang Pengjun, Yu Junjun, Xu Jian	Design of Clocked Transmission Gate Adiabatic Logic Circuit Based on the 3ECEAC.	APCCAS	2006	DBLP DOI BibTeX RDF
27	Seiichi Saito	A novel analysis method of bus signal transmission and a proposal for high-speed low-power bus circuit.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
27	Christofer Toumazou, Costas A. Makris	Analog IC design automation. I. Automated circuit generation: new concepts and methods.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
27	Mary L. Bailey	How circuit size affects parallelism.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
27	Tsutomu Sasao	MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators.	DAC	1986	DBLP DOI BibTeX RDF
27	David Sheldon, Frank Vahid	Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	BRAM, high-throughput design, pattern counting, redesigning circuit, FPGA, design patterns, stream, memory, ASIC
27	D. Dhanasekaran, K. Boopathy Bagan	Fault Tolerant Dynamic Antenna Array in Smart Antenna System Using Evolved Virtual Reconfigurable Circuit.	VLSI Design	2008	DBLP DOI BibTeX RDF	Virtual Reconfigurable circuit, element validation, Evolvable hardware
27	Guijun Gao, Youren Wang, Jiang Cui, Rui Yao	Research on Multi-objective On-Line Evolution Technology of Digital Circuit Based on FPGA Model.	ICES	2007	DBLP DOI BibTeX RDF	On-line Evolution, Multi-objective Evolutionary Method, FPGA Model, Digital Circuit, Evolvable Hardware
27	Zvi Rosberg, Andrew Zalesky, Moshe Zukerman	Packet delay in optical circuit-switched networks.	IEEE/ACM Trans. Netw.	2006	DBLP DOI BibTeX RDF	fixed point approximation, circuit switching, packet delay, WDM network
27	Kaoru Kurosawa, Wakaha Ogata	Bit-Slice Auction Circuit.	ESORICS	2002	DBLP DOI BibTeX RDF	mix and match, auction, circuit, bit-slice, multiparty protocol
27	Atila Alvandpour, Per Larsson-Edefors, Christer Svensson	Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits.	ISLPED	1998	DBLP DOI BibTeX RDF	short-circuit current, power consumption, power estimation
27	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Lossless Transmission Lines, VLSI, Dynamic, Power, CMOS, Inductance, Short-circuit
27	Felipe Machado, Teresa Riesgo, Yago Torroja	Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level.	PATMOS	2008	DBLP DOI BibTeX RDF	activity estimation, CAD, VHDL, BDD, power estimation, RTL, Switching activity, circuit partition, digital circuit design
27	Guoyong Shi, Weiwei Chen, C.-J. Richard Shi	A Graph Reduction Approach to Symbolic Circuit Analysis.	ASP-DAC	2007	DBLP DOI BibTeX RDF	symbolic analog circuit simulator, symbolic circuit analysis, recursive sign determination algorithm, binary decision diagram, graph reduction
27	Minesh B. Amin, Bapiraju Vinnakota	ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator.	VTS	1996	DBLP DOI BibTeX RDF	ZAMBEZI, parallel pattern simulator, parallel fault simulation, sequential circuit fault simulator, multiple faults simulation, multiple vectors, parallel algorithms, VLSI, fault diagnosis, logic testing, sequential circuits, circuit analysis computing, integrated logic circuits
27	Takafumi Hamano, Naofumi Takagi, Shuzo Yajima, Franco P. Preparata	O(n)-depth circuit algorithm for modular exponentiation.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	O(n)-depth circuit algorithm, polynomial-size combinational circuit algorithm, n-bit modular exponentiation, n-bit binary integers, square-and-multiply method, public key cryptography, combinational circuits, digital arithmetic, modular exponentiation
27	Hao Tang, Hung Chang Lin	A Fuzzy Membership Function Circuit Using Hysteretic Resonant Tunneling Diodes.	ISMVL	1995	DBLP DOI BibTeX RDF	switched capacitor networks, signal sampling, fuzzy membership function circuit, hysteretic resonant tunneling diodes, fuzzy logic hardware, hysteretic effect, input sampling, sampled input, intrinsic I-V characteristics, fuzzy logic, integrated logic circuits, membership function, hysteresis, resonant tunnelling diodes, resonant tunneling diodes, circuit performance
26	Susmit Jha, Sumit Kumar Jha 0001	Randomization Based Probabilistic Approach to Detect Trojan Circuits.	HASE	2008	DBLP DOI BibTeX RDF
26	Volkan Kursun, Eby G. Friedman	Domino logic with variable threshold voltage keeper.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
26	Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah, John P. Hayes	Fast and accurate timing characterization using functionalinformation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
26	Peng Gao, Trent McConaghy, Georges G. E. Gielen	ISCLEs: Importance Sampled Circuit Learning Ensembles for Trustworthy Analog Circuit Topology Synthesis.	ICES	2008	DBLP DOI BibTeX RDF
26	Masafumi Yamamoto, Hideaki Matsuzaki, Toshihiro Itoh, Takao Waho, T. Akeyoshi, J. Osaka	Ultrahigh-Speed Circuits Using Resonant Tunneling Devices.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	HEMT, D-FF, optoelectronic circuit, ADC, resonant tunneling diode
26	Qi Wang, Sarma B. K. Vrudhula	Data Driven Power Optimization of Sequential Circuits.	DATE	1998	DBLP DOI BibTeX RDF	logic synthesis low power design sequential circuits digital circuit testing verification
25	Hong Hu 0001, Zhongzhi Shi	Nonlinear Complex Neural Circuits Analysis and Design by q-Value Weighted Bounded Operator.	ISNN (1)	2008	DBLP DOI BibTeX RDF	neural dynamic analysis, neural circuit, fuzzy logical framework of a neural circuit, Fuzzy logic, chaos
25	Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee	Prospect of ballistic CNFET in high performance applications: Modeling and analysis.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	Ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, process variability, circuit performance
25	Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy	A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths.	VLSI Design	1997	DBLP DOI BibTeX RDF	robust dependent path, local circuit analysis, logic circuit testing, functionally unsensitizable path, timing, logic circuits
25	Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham	A novel test generation approach for parametric faults in linear analog circuits .	VTS	1996	DBLP DOI BibTeX RDF	digital test software, time-domain tests, equivalent digital circuit, digital test vectors, test waveform, VLSI, test generation, integrated circuit testing, fault location, stuck-at faults, analogue integrated circuits, parametric faults, linear analog circuits, time-domain analysis, equivalent circuits, analogue processing circuits
25	Mukund Sivaraman, Andrzej J. Strojwas	Diagnosis of parametric path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	parametric path delay faults, chip failure, fabrication process parameter values, path sensitization mechanism, path delay conditions, ISCAS'89 benchmark circuits, path segment, circuit failure, fault diagnosis, logic testing, logic testing, delays, probability, probability, statistical analysis, statistical analysis, integrated circuit testing, failure analysis, diagnosability, delay fault testing, IC testing, production testing
25	Youngmin Hur, Stephen A. Szygenda	Special purpose array processor for digital logic simulation.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	special purpose array processor, digital logic simulation, large VLSI circuits, compute-intensive tasks, digital analysis, time driven array processor, massively parallel processing element, compiled event-driven technology, nominal transport delay timing analysis, delay time order, levelized circuit, massively parallel PE array, MARS accelerator, VLSI, parallel architectures, delays, timing, fault simulation, logic CAD, digital simulation, circuit analysis computing, special purpose computers, SIMD architecture, hardware cost
25	José Monteiro 0001, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh	Optimization of combinational and sequential logic circuits for low power using precomputation.	ARVLSI	1995	DBLP DOI BibTeX RDF	sequential logic circuits, low power optimisation, logic optimization technique, precomputation architectures, logic synthesis methods, transmission gates, transparent latches, switching activity reduction, power dissipation reduction, VLSI, logic design, sequential circuits, combinational circuits, integrated circuit design, CMOS logic circuits, circuit optimisation, precomputation, combinational logic circuits, clock cycle
25	Wei-Yu Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	Test generation for crosstalk-induced faults: framework and computational result.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	2-vector test generation, crosstalk-induced faults, noise effects, design effort, debugging effort, pulses, signal speedup, signal slowdown, digital combinational circuits, mixed-signal test generator, XGEN, static values, dynamic signals, signal arrival times, rise times, fall times, integrated circuit testing, automatic test pattern generation, combinational circuits, accuracy, vectors, circuit analysis computing, crosstalk, transitions, integrated logic circuits, technology scaling, SPICE simulations, gate delay, circuit performance, timing information, clock frequency
25	Michael J. Liebelt, Cheng-Chew Lim	A method for determining whether asynchronous circuits are self-checking.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise
25	Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw	Library-less synthesis for static CMOS combinational logic circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	library-less synthesis, resynthesized circuits, size-wise CMOS circuit optimization, static CMOS combinational logic circuits, structural CMOS circuit optimization, transistor level technique, CMOS logic circuits, design space, optimal design, circuit performance
25	Julien Dunoyer, Nizar Abdallah, Pirouz Bazargan-Sabet	A symbolic simulation approach in resolving signals' correlation.	Annual Simulation Symposium	1996	DBLP DOI BibTeX RDF	signal resolution, signal correlation resolution, symbolic simulation approach, evaluation package, signal transition density, specification levels, first order clue, independent inputs, binary decision diagram concept, algorithms, VLSI, probability, logic CAD, digital simulation, design process, decision theory, circuit analysis computing, integrated circuit design, circuit CAD, digital circuits, subroutines, symbol manipulation, power dissipation, correlation methods, digital integrated circuits, signal probability, probabilistic approach, synthesis tools
25	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Segment delay faults: a new fault model.	VTS	1996	DBLP DOI BibTeX RDF	segment delay faults, delay defect, distributed defect, rising transitions, falling transitions, transition tests, nonrobust tests, VLSI, fault diagnosis, logic testing, delays, integrated circuit testing, fault model, automatic testing, circuit analysis computing, robust tests, integrated circuit modelling, production testing, spot defect, manufacturing defects
25	John W. Sheppard, William R. Simpson	Improving the accuracy of diagnostics provided by fault dictionaries.	VTS	1996	DBLP DOI BibTeX RDF	diagnostics accuracy improvement, digital circuit diagnosis, information flow model, VLSI, fault diagnosis, logic testing, integrated circuit testing, automatic testing, circuit analysis computing, digital integrated circuits, fault dictionaries, nearest neighbor classification
25	Haluk Konuk, F. Joel Ferguson	An unexpected factor in testing for CMOS opens: the die surface.	VTS	1996	DBLP DOI BibTeX RDF	surface phenomena, electric charge, CMOS opens, die surface, RC interconnect, HSPICE simulations, trapped charge, floating gates, VLSI, integrated circuit testing, CMOS integrated circuits, integrated circuit modelling, circuit model
25	Hari Balachandran, D. M. H. Walker	Improvement of SRAM-based failure analysis using calibrated Iddq testing.	VTS	1996	DBLP DOI BibTeX RDF	defect-bitmap dictionary, voltage testing, microprocessor cache memory, integrated circuit testing, calibration, calibration, SRAM, cache storage, failure analysis, failure analysis, IDDQ testing, current testing, defect classification, SRAM chips, integrated circuit yield, integrated circuit yield
25	Sudhir K. Jhajharia, Hua Swee Wang	Training diploma students on ATE-related module.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	electronic equipment testing, tertiary institution, ATE-related module, diploma students, final year students, Microelectronics option, Electronics and Communication Engineering Department, Singapore Polytechnic, Singapore Polytechnic Education Model, automated test equipment, Advanced Diploma, practical training, laboratory session, training, integrated circuit testing, assessment, teaching, teaching, automatic testing, automatic test equipment, test patterns, printed circuit boards, educational courses, printed circuit testing, industry-standard, electronic engineering education
25	Haifang Liao, Wayne Wei-Ming Dai	Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels.	ICCAD	1995	DBLP DOI BibTeX RDF	circuit reduction, scattering parameter, interconnect network, macromodel, Circuit partitioning, circuit synthesis
25	Mike Chou, Jacob K. White 0001	Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect.	ICCAD	1995	DBLP DOI BibTeX RDF	Arnoldi method, SPICE-level simulation, Taylor series terms, surface-volume methods, three-dimensional interconnect, circuit analysis computing, transient analysis, integrated circuit interconnect, integrated circuit interconnections, reduced-order modeling, reduced-order models, transient simulation, series (mathematics)
25	Alessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò	Reliability evaluation of combinational logic circuits by symbolic simulation.	VTS	1995	DBLP DOI BibTeX RDF	mcnc benchmark circuits, fault-tolerant combinational logic circuits, circuit functionality, fault indicators, control variables, BDD-based symbolic simulation, undetectable multiple faults, VLSI, VLSI, combinational circuits, logic CAD, digital simulation, circuit analysis computing, reliability evaluation, integrated circuit reliability
25	Manjit Borah, Mary Jane Irwin, Robert Michael Owens	Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, static CMOS circuits, input reordering, high fan-out gates, power constrained module generator, PowerSizer, logic CAD, circuit layout CAD, CMOS logic circuits, logic circuits, minimisation, arithmetic circuits, circuit optimisation, integrated circuit layout, transistor sizing
25	David B. Shu, Ching-Chung Li, J. F. Mancuso, Yung-Nien Sun	A Line Extraction Method for Automated SEM Inspection of VLSI Resist.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	line extraction method, automated SEM inspection, VLSI resist, precision digital edge-line-detection method, edge contours, submicrometer width, integrated circuit fabrication, computer vision, VLSI, transforms, integrated circuit testing, computerised picture processing, automatic testing, Hough transform, inspection, circuit analysis computing, scanning electron microscopy, scanning electron microscopy
25	Hailong You, Maofeng Yang, Dan Wang, Xinzhang Jia	Kriging Model combined with latin hypercube sampling for surrogate modeling of analog integrated circuit performance.	ISQED	2009	DBLP DOI BibTeX RDF
25	Zhanyuan Jiang, Weiping Shi	Circuit-wise buffer insertion and gate sizing algorithm with scalability.	DAC	2008	DBLP DOI BibTeX RDF	buffer insertion, gate sizing, interconnect synthesis
25	Gang Jin, Lei Wang 0011, Zhiying Wang 0003, Kui Dai	An Optimal Design Method for De-synchronous Circuit Based on Control Graph.	APPT	2007	DBLP DOI BibTeX RDF	de-synchronous, control graph, performance evaluation, algorithm, Petri-net, asynchronous
25	Arun V. Sathanur, Ritochit Chakraborty, Vikram Jandhyala	Statistical analysis of RF circuits using combined circuit simulator-full wave field solver approach.	ICCAD	2007	DBLP DOI BibTeX RDF
25	Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi	Highly Efficient String Matching Circuit for IDS with FPGA.	FCCM	2006	DBLP DOI BibTeX RDF
25	Takao Tsukutani, Yasuaki Sumi, Masami Higashimura, Yutaka Fukui	Current-mode universal biquad circuit using MO-OTAs and DO-CCII.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
25	Hing-mo Lam, Chi-Ying Tsui	High performance and low power completion detection circuit.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
25	Lipeng Cao	Circuit power estimation using pattern recognition techniques.	ICCAD	2002	DBLP DOI BibTeX RDF
25	Faizal Arya Samman, Rhiza S. Sadjad	Analog MOS circuit design for reconfigurable fuzzy logic controller.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
25	Aaron Harwood, Hong Shen 0001	Batched Circuit Switched Routing for Efficient Service of Requests.	ISPAN	2000	DBLP DOI BibTeX RDF
25	Lei Wang 0003, Naresh R. Shanbhag	Noise-tolerant dynamic circuit design.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
25	M. D. Bagewadi, B. G. Fernandes, R. V. S. Subrahmanyam	A novel QRDCL circuit for zero voltage switched inverter.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
25	Subhrajit Bhattacharya, Sujit Dey, Franc Brglez	Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	resorce sharing, high-level synthesis, clock period
25	Orlando Lee, Yoshiko Wakabayashi	Circuit Covers in Series-Parallel Mixed Graphs.	LATIN	1998	DBLP DOI BibTeX RDF
25	Hannah Honghua Yang, Martin D. F. Wong	Circuit clustering for delay minimization under area and pin constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
25	Wen-Ben Jone, Christos A. Papachristou	A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
25	Abhijit Chatterjee, Richard I. Hartley	A New Simultaneous Circuit Partitioning and Chip Placement Approach Based on Simulated Annealing.	DAC	1990	DBLP DOI BibTeX RDF
25	Imrich Chlamtac, Aura Ganz, G. Karmi	Circuit switching in multi-hop lightwave networks.	SIGCOMM	1988	DBLP DOI BibTeX RDF
24	Abdulhadi Shoufan, Zheng Lu 0006, Guido Rößling	A platform for visualizing digital circuit synthesis with VHDL.	ITiCSE	2010	DBLP DOI BibTeX RDF	digital circuit synthesis, visualization, animation, VHDL
24	Kevin Zhang 0001	Circuit design in nano-scale CMOS era: opportunities & challenges.	ISLPED	2009	DBLP DOI BibTeX RDF	VLSI, CMOS, circuit
24	Bin Zhang 0011	Online circuit reliability monitoring.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	reliability, circuit, macromodel, online monitoring
24	Yerbol Sapargaliyev, Tatiana Kalganova	Unconstrained Evolution of Analogue Computational "QR" Circuit with Oscillating Length Representation.	ICES	2008	DBLP DOI BibTeX RDF	Evolutionary hardware design, Evolutionary circuit diagnostics and testing
24	Saravanan Ramamoorthy, Haibo Wang 0005, Sarma B. K. Vrudhula	A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design.	ISQED	2008	DBLP DOI BibTeX RDF	low power, memory, circuit design, FIFO
24	Takushi Tanaka	A Logic Grammar for Circuit Analysis.	KES (2)	2007	DBLP DOI BibTeX RDF	Parsing Circuits, DCG, DCSG, Circuit Analysis, Logic Grammar
24	Viet Hung Nguyen, M. Ben Mamoun, Tülin Atmaca, Daniel Popa, Nicolas Le Sauze, Laurent Ciavaglia	Performance Evaluation of Circuit Emulation Service in a Metropolitan Optical Ring Architecture.	ICT	2004	DBLP DOI BibTeX RDF	Circuit Emulation Service, Metropolitan Networks, Optical Ethernet Ring, Quality of Service, Performance Evaluation, TDM
24	Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David T. Blaauw, Trevor N. Mudge	Circuit-aware architectural simulation.	DAC	2004	DBLP DOI BibTeX RDF	circuit simulation, architectural simulation, high-performance simulation, computer system simulation
24	Ming-Dou Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo	ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process.	ISQED	2002	DBLP DOI BibTeX RDF	ESD, ESD protection circuit, substrate-triggered technique
24	David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska	Circuit partitioning with logic perturbation.	ICCAD	1995	DBLP DOI BibTeX RDF	alternative wires, circuit partitioning
24	Toru Yukimatsu, Takeshi Furuhashi, Yoshiki Uchikawa	A Fuzzy Expert System for Hierarchical Placement of Parts on Printed Circuit Board.	ANNES	1995	DBLP DOI BibTeX RDF	Fuzzy Logic, CAD, Expert System, Printed Circuit Board
24	Yoichi Sasaki 0001, Kazuteru Namba, Hideo Ito	Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Masking circuit, Pass transistor, Schmitt trigger circuit, Soft error, Latch
24	Chantal Ykman-Couvreur, Bill Lin 0001	Optimised state assignment for asynchronous circuit synthesis.	ASYNC	1995	DBLP DOI BibTeX RDF	optimised state assignment, asynchronous circuit synthesis, complete state coding, state graph level, asynchronous benchmarks, circuit area, logic design, encoding, asynchronous circuits, computation time, state assignment
24	Fadi Y. Busaba, Parag K. Lala	A graph coloring based approach for self-checking logic circuit design.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	logic circuit design, bidirectional error, residue weights assignments, output lines, errors identification, graph theory, logic testing, integrated circuit testing, logic design, error detection, error detection, automatic testing, graph coloring, fault location, integrated logic circuits, graph colouring, self-checking, residue codes, single stuck-at fault
24	Issam S. Abu-Khater, Abdellatif Bellaouar, Mohamed I. Elmasry, Ran-Hong Yan	Circuit/architecture for low-power high-performance 32-bit adder.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	conditional sum architecture, CPL-like logic implementation, power supply voltage, minimum size, optimized speed, 1 to 3.3 V, logic design, CMOS, integrated circuit design, adders, adder, CMOS logic circuits, circuit optimisation, 32 bit
24	Goutam Debnath, Kathy Debnath, Roshan Fernando	The Pentium processor-90/100, microarchitecture and low power circuit design.	VLSI Design	1995	DBLP DOI BibTeX RDF	BIMOS integrated circuits, Pentium processor-90/100, low power circuit design, BiNMOS process, power consumption reduction, symmetric dual processing feature, multithreaded operating systems, 0.6 micron, 3.3 V, computer architecture, microarchitecture, integrated circuit design, microprocessor chips, 100 MHz
24	Qin-Zhong Ye, Per-Erik Danielsson	Inspection of Printed Circuit Boards by Connectivity Preserving Shrinking.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	PCB manufacture, connectivity preserving shrinking, edge irregularities, printed circuit manufacture, computer vision, computer vision, computerised pattern recognition, computerised pattern recognition, inspection, sensitivity, quality control, quality control, visual inspection, printed circuit boards, pipelined structure
24	Stanley E. Lass	Automated printed circuit routing with a stepping aperture.	Commun. ACM	1969	DBLP DOI BibTeX RDF	circuit board, printed circuit, stepping aperture, routing, interconnections, lines, computer program, vias, pins, aperture
24	Souma Jinno, Shuji Kitora, Hiroshi Toki, Masayuki Abe	Origin of common-mode noise in two-dimensional finite-size circuit and reduction of the noise using a symmetric three-line circuit.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
24	Kenji Murao, Tohru Kohda	Switched capacitor circuit for 1/f noise generation using a power-law circuit.	Int. J. Circuit Theory Appl.	1994	DBLP DOI BibTeX RDF
24	Yuri L. Maistrenko, Volodymyr L. Maistrenko, Leon O. Chua	Cycles of Chaotic Intervals in a Time-delayed Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	K. Sean Halle, Chai-Wah Wu, Makoto Itoh, Leon O. Chua	Spread spectrum Communication through modulation of Chaos in Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Tomasz Kapitaniak	Targeting unstable stationary States of Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Aleksandr Nikolayevich Sharkovsky, Yuri L. Maistrenko, Philippe Deregel, Leon O. Chua	Dry turbulence from a Time-delayed Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Manuel Delgado-Restituto, Arturo Rodríguez Vázquez	A CMOS monolithic Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Steve Elgar, Michael Peter Kennedy	Bispectral Analysis of Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Ulrich Parlitz	Lyapunov exponents from Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Mario Biey, Silvano Chialina, Martin Hasler, Amedeo Premoli	Piecewise-linear Analysis for Chua's Circuit family, including the Computation of Lyapunov exponents.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Krishnamurthy Murali, M. Lakshmanan 0001	Controlling of Chaos in the Driven Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Leon O. Chua, Makoto Itoh, Ljupco Kocarev, Kevin Eckert	Chaos Synchronization in Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Vladimir N. Belykh, Leon O. Chua	A New Type of Strange Attractor Related to the Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	A. A. A. Nasser, E. E. Hosny, Mohamed I. Sobhy	Maximum Dynamic Range of bifurcations of Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Erik Lindberg	Modelling and simulation of Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Guanrong Chen, Xiaoning Dong	Controlling Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF