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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3674 occurrences of 1433 keywords
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Results
Found 5812 publication records. Showing 5812 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
39 | Mike Chou, Jacob K. White 0001 |
Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 40-44, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Arnoldi method, SPICE-level simulation, Taylor series terms, surface-volume methods, three-dimensional interconnect, circuit analysis computing, transient analysis, integrated circuit interconnect, integrated circuit interconnections, reduced-order modeling, reduced-order models, transient simulation, series (mathematics) |
39 | Amit Singh 0001, Malgorzata Marek-Sadowska |
FPGA interconnect planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 23-30, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
39 | Dirk Stroobandt |
A priori system-level interconnect prediction: Rent's rule and wire length distribution models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 3-21, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Basab Datta, Wayne P. Burleson |
Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 341-346, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
tunable buffer, variability, NBTI, global-interconnect |
39 | Xiaoxia Wu, Guangyu Sun 0003, Xiangyu Dong, Reetuparna Das, Yuan Xie 0001, Chita R. Das, Jian Li 0059 |
Cost-driven 3D integration with interconnect layers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 150-155, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
interconnect service layer, three-dimensional integrated circuit, network-on-chip |
39 | Wenyi Feng, Sinan Kaptanoglu |
Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(1), pp. 6:1-6:28, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
cluster, FPGAs, entropy, interconnect, counting, PLDs, LUT |
39 | DiaaEldin Khalil, Yehea I. Ismail |
A global interconnect link design for many-core microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFMT ![In: Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, IFMT 2008, Cairo, Egypt, November 24-25, 2008, pp. 14, 2008, ACM, 978-1-60558-407-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
interconnect, link, bus, repeater insertion |
39 | Basab Datta, Wayne P. Burleson |
Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 41-46, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
sensor, interconnect, temperature, oscillator |
39 | Wenyi Feng, Sinan Kaptanoglu |
Designing efficient input interconnect blocks for LUT clusters using counting and entropy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 23-32, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
cluster, FPGAs, entropy, interconnect, counting, PLDs, LUT |
39 | Naveen Muralimanohar, Rajeev Balasubramonian |
Interconnect design considerations for large NUCA caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 369-380, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
non-uniform cache architecture, network-on-chip, interconnect, memory hierarchies, cache models |
39 | Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh |
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(8), pp. 1025-1040, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
system-on-chip, Network-on-chip, interconnect architecture, MP-SoC, infrastructure IP |
39 | Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen |
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 904-907, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect pipelining, statistical timing analysis |
39 | Magdy A. El-Moursy, Eby G. Friedman |
Shielding effect of on-chip interconnect inductance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 165-170, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
on-chip inductance, shielding effect, propagation delay, interconnect modeling, gate delay |
39 | Xiaoling Sun, A. Alimohammad, Pieter M. Trouborst |
Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test Configurations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 284-292, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
global/local interconnect testing, modeling, graph coloring, greedy algorithms, FPGA testing |
39 | Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang |
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 523-528, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Interconnect-Driven Floorplanning, Performance Optimization |
39 | Tao Lin, Lawrence T. Pileggi |
RC(L) interconnect sizing with second order considerations via posynomial programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001, pp. 16-21, 2001, ACM, 1-58113-347-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
RC trees, VLSI design automation, central moments, posynomiality, convex programming, interconnect optimization |
39 | Abby A. Ilumoka |
Efficient prediction of interconnect crosstalk using neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTAI ![In: 12th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2000), 13-15 November 2000, Vancouver, BC, Canada, pp. 122-125, 2000, IEEE Computer Society, 0-7695-0909-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
interconnect crosstalk prediction, deep submicron downscaling, wirecells, modular artificial neural networks, multiparadigm prototyping system, equicoupling contours, isocouples, transconductance amplifier, neural networks, delays, delay, finite element method, neural nets, crosstalk, experimental results, circuit CAD, finite element analysis, circuit simulation, circuit simulator, integrated circuit interconnections, wafer-scale integration, wafer scale integration |
39 | Nuno Alexandre Marques, Mattan Kamon, Jacob K. White 0001, Luís Miguel Silveira |
An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 538-543, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Passive Model Order Reduction, Modified Nodal Analysis, PEEC, Extraction, Interconnect Modeling |
39 | Lizyamma Kurian, Daniel Brewer, Eugene John |
Design of a highly reconfigurable interconnect for array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 321-325, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
reconfigurable interconnect, static-RAM programming technology, faulty elements, fault-tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, network topology, reconfigurable architectures, array processors, interconnection topologies, mesh topologies |
39 | Jung-Cheun Lien, Melvin A. Breuer |
An optimal scheduling algorithm for testing interconnect using boundary scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(1), pp. 117-130, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
Boundary scan, test scheduling, interconnect test |
38 | Manuel Sellier, Jean-Michel Portal, Bertrand Borot, Steve Colquhoun, Richard Ferrant, Frédéric Boeuf, Alexis Farcy |
Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 492-497, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Predictive SPICE Modeling, Interconnect Resistance, Buffer Insertion, Interconnect Delay |
38 | Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De |
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 79-84, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
intra-die variations, multi-cycle interconnect, parameter fluctuations, time borrowing, interconnect, parameter variations, within-die variations, variation tolerant |
38 | Jifeng Chen, Jin Sun 0006, Janet Meiling Wang |
Robust interconnect communication capacity algorithm by geometric programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 19-26, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
communication capacity, optimization, robust, uncertainty, process variation, geometric programming, ellipsoid |
38 | Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton |
Practical Asynchronous Interconnect Network Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(5), pp. 579-588, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Andrew Labun, Karan Jagjitkumar |
Rapid Detailed Temperature Estimation for Highly Coupled IC Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10), pp. 1840-1851, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Md. Sajjad Rahaman, Masud H. Chowdhury |
Time diversity approach for intra-chip RF/wireless interconnect systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2434-2437, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown |
Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(8), pp. 895-903, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Ian O'Connor, Faress Tissafi-Drissi, Frédéric Gaffiot, Joni Dambre, Michiel De Wilde, Jan Van Campenhout, Dries Van Thourhout, Dirk Stroobandt |
Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(8), pp. 927-940, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud |
Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 516-517, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong |
Interconnect Power Optimization Based on Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 119-124, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Zhipeng Liu, Jinian Bian, Qiang Zhou 0001, Hui Dai |
Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 279-284, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Vineet Agarwal, Jin Sun 0006, Alexander V. Mitev, Janet Meiling Wang |
Delay Uncertainty Reduction by Interconnect and Gate Splitting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 690-695, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Ethiopia Nigussie, Juha Plosila, Jouni Isoaho |
Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 649-652, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Arthur Nieuwoudt, Yehia Massoud |
Assessing the Implications of Process Variations on Future Carbon Nanotube Bundle Interconnect Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 119-126, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Navneeth Kankani, Vineet Agarwal, Janet Meiling Wang |
A probabilistic analysis of pipelined global interconnect under process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 724-729, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Krishnamoorthy Natarajan, S. J. Nagalakshmi |
Repeater Sizing and Insertion Length of Interconnect to Minimize the Overall Time Delay using a Truncated Fourier Series Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 789-792, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Lin Zhong 0001, Niraj K. Jha |
Interconnect-aware low-power high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3), pp. 336-351, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Rohini Krishnan, R. I. M. P. Meijer, Durand Guillaume |
Energy-efficient FPGA interconnect architecture design (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 268, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Yan Lin 0001, Fei Li 0003, Lei He 0001 |
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 645-650, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen |
Wave-pipelined on-chip global interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 127-132, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton |
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 267-274, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Andres Teene, Bob Davis, Ruggero Castagnetti, Jeff Brown, S. Ramesh 0004 |
Impact of Interconnect Process Variations on Memory Performance and Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 694-699, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | John Shalf, Shoaib Kamil 0001, Leonid Oliker, David Skinner |
Analyzing Ultra-Scale Application Communication Requirements for a Reconfigurable Hybrid Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, November 12-18, 2005, Seattle, WA, USA, CD-Rom, pp. 17, 2005, IEEE Computer Society, 1-59593-061-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Francky Catthoor, Andrea Cuomo, Grant Martin, Patrick Groeneveld, Rudy Lauwereins, Karen Maex, Patrick van de Steeg, Ron Wilson |
How Can System-Level Design Solve the Interconnect Technology Scaling Problem? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 332-339, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara |
Interconnect Modeling for Copper/Low-k Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 425-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick |
Encoded-Low Swing Technique for Ultra Low Power Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 240-251, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
38 | PariVallal Kannan, Dinesh Bhatia |
Interconnect Estimation for FPGAs under Timing Driven Domains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 344-349, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Payman Zarkesh-Ha, S. Lakshminarayann, Ken Doniger, William Loh, Peter Wright |
Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 405-409, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Martijn T. Bennebroek |
Validation of wire length distribution models on commercial designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 41, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Ankireddy Nalamalpu, Sriram Srinivasan, Wayne P. Burleson |
Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1), pp. 50-62, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
38 | Ian G. Harris, Russell Tessier |
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11), pp. 1337-1343, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
38 | Lin Zhong 0001, Niraj K. Jha |
Interconnect-aware high-level synthesis for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 110-117, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
38 | Vikas Mehrotra, Shiou Lin Sam, Duane S. Boning, Anantha P. Chandrakasan, Rakesh Vallishayee, Sani R. Nassif |
A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 172-175, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
38 | Jason Cong, Lei He 0001 |
Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4), pp. 406-420, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
38 | Anirudh Devgan, Peter R. O'Brien |
Realizable reduction for RC interconnect circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 204-207, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
38 | Lizy Kurian John, E. John |
A dynamically reconfigurable interconnect for array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(1), pp. 150-157, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
38 | Wolf-Dietrich Weber, Stephen Gold, Pat Helland, Takeshi Shimizu, Thomas Wicki, Winfried W. Wilcke |
The Mercury Interconnect Architecture: A Cost-effective Infrastructure for High-performance Servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997, pp. 98-107, 1997, ACM, 0-89791-901-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
38 | Curtis L. Ratzlaff, Lawrence T. Pillage |
RICE: rapid interconnect circuit evaluation using AWE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6), pp. 763-776, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
38 | Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai |
Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007, pp. 259-266, 2007, ACM, 978-1-59593-683-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
interconnect, power, SMP, cache coherence protocol |
37 | Ajay Joshi, Gerald G. Lopez, Jeffrey A. Davis |
Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(9), pp. 990-1002, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Qi Zhu 0002, Hai Zhou 0001, Tong Jing, Xianlong Hong, Yang Yang 0040 |
Spanning graph-based nonrectilinear steiner tree algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7), pp. 1066-1075, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl |
Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings, pp. 147-148, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Jason Cong, Mau-Chung Frank Chang, Glenn Reinman, Sai-Wang Tam |
Multiband RF-interconnect for reconfigurable network-on-chip communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 107-108, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fdma, morfic, rf-interconnect, network-on-chip, reconfigurable, chip multiprocessor |
34 | Dae Hyun Kim 0004, Saibal Mukhopadhyay, Sung Kyu Lim |
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 85-92, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
wirelength distribution, rent's rule, 3d ic, tsv, interconnect prediction, through silicon via |
34 | Prashant Saxena |
The scaling of interconnect buffer needs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 109-112, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
interconnect, scaling, buffers, repeaters |
34 | J. Balachandran, Steven Brebels, Geert Carchon, Maarten Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne |
Constant impedance scaling paradigm for interconnect synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 99-105, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
transmission lines, interconnect optimization, global interconnects |
34 | Tao Wan, Malgorzata Chrzanowska-Jeske |
Prediction of interconnect net-degree distribution based on Rent's rule. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 107-114, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
net-degree distribution, Rent's rule, interconnect prediction |
34 | Ganapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee 0001, Amit Singh 0001 |
Interconnect complexity-aware FPGA placement using Rent's rule. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 115-121, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Rent's exponent, interconnect, placement |
34 | Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl |
Prediction of interconnect fan-out distribution using Rent's rule. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings, pp. 107-112, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fan-out distribution, interconnect network prediction, Rent's rule |
34 | Louis Scheffer, Eric Nequist |
Why interconnect prediction doesn't work. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings, pp. 139-144, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
constructive estimation, wire load model, interconnect prediction |
34 | Sunghoon Chun, YongJoon Kim, Sungho Kang 0001 |
MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(4), pp. 357-362, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
RLC interconnect model, fault modeling, signal integrity, interconnect test |
34 | Jae-sun Seo, Dennis Sylvester, David T. Blaauw, Himanshu Kaul, Ram Krishnamurthy 0001 |
A robust edge encoding technique for energy-efficient multi-cycle interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 68-73, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multi-cycle interconnect, interconnect, encoding, repeaters |
34 | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko |
Yield enhancements of design-specific FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 93-100, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
design-specific FPGA, interconnect faults, interconnect utilization, yield enhancement, yield prediction, structured ASIC, FPGA interconnect |
33 | Duo Ding, David Z. Pan |
OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 11-18, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
photonic networks-on-chip, low power, computer aided design, high performance |
33 | Alexander V. Mitev, Michael M. Marefat, Dongsheng Ma, Janet Meiling Wang |
Principle hessian direction based parameter reduction for interconnect networks with process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 41-46, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
principle Hessian directions, process variation, timing analysis |
33 | Shih-Hsu Huang |
An effective low power design methodology based on interconnect prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 189-194, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu 0001 |
Interconnect implications of growth-based structural models for VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 99-106, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet |
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 43-52, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing |
33 | Joseph B. Cessna, Thomas R. Bewley |
Honeycomb-structured computational interconnects and their scalable extension to spherical domains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 27-36, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
switchless interconnect, graph theory |
33 | Zhuo Li 0001, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia |
Fast interconnect synthesis with layer assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 71-77, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
buffer insertion, wire sizing, layer assignment, interconnect synthesis |
33 | Jin Guo 0001, Antonis Papanikolaou, Michele Stucchi, Kristof Croes, Zsolt Tokei, Francky Catthoor |
A tool flow for predicting system level timing failures due to interconnect reliability degradation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 291-296, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
system degradation, system level failures, interconnect reliability |
33 | Farshad Safaei, Ahmad Khonsari, Mahmood Fathy, Mohamed Ould-Khaoua |
Analysis of Circuit Switching for the Torus Interconnect Networks with Hot-Spot Traffic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: 2006 International Conference on Parallel Processing Workshops (ICPP Workshops 2006), 14-18 August 2006, Columbus, Ohio, USA, pp. 142-150, 2006, IEEE Computer Society, 0-7695-2637-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Hot-spot traffic, Queuing theory and Performance evaluation, Parallel computers, Interconnect networks, Torus, Circuit switching |
33 | W. T. Cheung, N. Wong |
Power optimization in a repeater-inserted interconnect via geometric programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 226-231, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
optimization, interconnect, power, repeater, geometric programming |
33 | Haibin Shen, Rongquan You, Yier Jin, Aiming Ji |
Interconnect Estimation for Mesh-Based Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference, EUC 2006, Seoul, Korea, August 1-4, 2006, Proceedings, pp. 766-775, 2006, Springer, 3-540-36679-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
mesh-based, probability, Interconnect, reconfigurable computing |
33 | Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa |
Interconnect capacitance extraction for system LCD circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 160-163, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
interconnect capacitance, system LCD, capacitance extraction |
33 | Ronald P. Luijten, Cyriel Minkenberg, B. Roe Hemenway, Michael Sauer, Richard Grzybowski |
Viable opto-electronic HPC interconnect fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, November 12-18, 2005, Seattle, WA, USA, CD-Rom, pp. 18, 2005, IEEE Computer Society, 1-59593-061-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Interconnect, Switching, HPC, Optical Switching |
33 | Chiu-Wing Sham, Evangeline F. Y. Young |
Congestion prediction in early stages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 91-98, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
placement, floorplanning, interconnect estimation |
33 | Jason Cong, Yiping Fan, Zhiru Zhang |
Architecture-level synthesis for automatic interconnect pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 602-607, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect pipelining, multi-cycle communication, scheduling, high-level synthesis, register binding |
33 | John F. Croix, D. F. Wong 0001 |
Blade and razor: cell and interconnect delay analysis using current-based models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 386-389, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
blade, current-based model, razor, recursive convolution, timing analysis, interconnect model, cell model |
33 | Iain Gourlay, Peter M. Dew, Karim Djemame |
Bulk Synchronous Parallel Computing Using a High Bandwidth Optical Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Bulk Synchronous Parallelism (BSP), performance evaluation, Parallel architecture, optical interconnect, parallel sorting |
33 | Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim |
Analytical signal integrity verification models for inductance-dominant multi-coupled VLSI interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 61-68, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
TWA, signal integrity verification, delay, crosstalk, ringing, signal integrity, transmission line, glitch, VLSI interconnect, traveling-wave |
33 | Raymond A. Wildman, Joshua I. Kramer, Daniel S. Weile, Phillip Christie |
Wire layer geometry optimization using stochastic wire sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 97-102, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
genetic algorithms, optimization, interconnect, Rent's rule |
33 | Phillip J. Restle, Albert E. Ruehli, Steven G. Walker |
Multi-GHz interconnect effects in microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001, pp. 93-97, 2001, ACM, 1-58113-347-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
full-wave analysis, simulation, interconnect, inductance, extraction, clock distribution, circuit-tuning |
33 | Chen-Huan Chiang, Sandeep K. Gupta 0001 |
BIST TPG for Combinational Cluster Interconnect Testing at Board Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 427-442, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
cluster testing, built-in self-test, BIST, boundary scan, interconnect testing |
33 | Vinay Dabholkar, Sreejit Chakravarty |
Computing stress tests for interconnect defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 143-148, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
interconnect defects, reliability screens, infant mortality, gate-oxide defects, integrated circuit testing, stress tests |
33 | Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara |
A Test Methodology for Interconnect Structures of LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 68-74, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Programmable Interconnect Structures, Cross Point Switch, Configurable Logic Block, FPGA, Test Pattern Generation |
33 | Mongkol Raksapatcharawong, Timothy Mark Pinkston |
An Optical Interconnect Model for k-ary n-cube Wormhole Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 666-672, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
free-space optical interconnects, optical interconnect model, performance evaluation, wormhole switching, k-ary n-cube networks |
33 | Mustafa Celik, Andreas C. Cangellaris |
A general dispersive multiconductor transmission line model for interconnect simulation in SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 563-568, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multiconductor transmission lines, interconnect simulation, Chebyshev approximation, SPICE, transient analysis |
33 | Wei-Kang Huang, Xiao-Tao Chen, Fabrizio Lombardi |
On the diagnosis of programmable interconnect systems: Theory and application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 204-211, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
field programmable interconnect system, switch grid, FPIS, Xilinx 3000, field programmable gate arrays, FPGA, fault diagnosis, logic testing, diagnosis, integrated circuit interconnections |
33 | Anirudh Devgan, Ronald A. Rohrer |
Efficient simulation of interconnect and mixed analog-digital circuits in ACES. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 229-233, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
adaptively controlled explicit simulation, mixed analog-digital circuits, analog circuit simulation, interconnect circuit simulation, AWE macromodels, nonlinear terminations, variable accuracy device models, circuit topology constraints removal, timing, circuit analysis computing, transient analysis, analogue integrated circuits, integrated circuit interconnections, mixed analogue-digital integrated circuits, ACES, transient simulation, timing simulation |
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