Search results for "CMOS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Luiz Carlos Moreira, Wilhelmus A. M. Van Noije, Armando Ayala Pabón, Andrés Farfán-Peláez	Comparison of small cross inductors and rectangular inductors designed in 0.35um CMOS technology.	SBCCI	2009	DBLP DOI BibTeX RDF	cross inductors, rectangular inductors, RF CMOS
20	Hussain A. Alzaher, Noman Tasadduq	A CMOS low power current-mode polyphase filter.	ISLPED	2009	DBLP DOI BibTeX RDF	CMOS analog integrated circuits, low power current mode circuit, polyphase filter
20	Kaushik Roy 0001	Ultra low voltage CMOS.	ISLPED	2009	DBLP DOI BibTeX RDF	adaptive supply scaling, nano-scale cmos system, ultra low voltage design, ultra-dynamic voltage scaling
20	Kelin J. Kuhn	CMOS scaling beyond 32nm: challenges and opportunities.	DAC	2009	DBLP DOI BibTeX RDF	high-k, CMOS, orientation, strain, metal-gate
20	Shekhar Borkar	Design perspectives on 22nm CMOS and beyond.	DAC	2009	DBLP DOI BibTeX RDF	nano, power, CMOS, variability
20	Kristian Granhaug, Snorre Aunet	Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Subthreshold CMOS, Output-wired redundancy, Yield and defect tolerance
20	Bangli Liang, Tad A. Kwasniewski, Dianyong Chen	A 42-Gb/s Decision Circuit in 0.13µm CMOS.	CNSR	2008	DBLP DOI BibTeX RDF	CMOS CML, Shunt peaking, Split-resistor, Optical communication
20	Pablo Aguirre, Fernando Silveira	CMOS op-amp power optimization in all regions of inversion using geometric programming.	SBCCI	2008	DBLP DOI BibTeX RDF	optimization, CMOS, analog, geometric programming, automatic design
20	Victor Ariel Leal Sobral, Roberto Espinheira da Costa Bomfim, Robson Nunes de Lima, Ana Isabela Araújo Cunha	Systematic methodology for the design of Seevinck's CMOS log-domain integrators.	SBCCI	2008	DBLP DOI BibTeX RDF	CMOS integrators, companding circuits, log-domain integrators
20	Tadashi Ikeuchi, Tszshing Cheung, Hiroshi Onaka	The Latest Trend of Low Power High-Speed CMOS I/O Technology for Photonic Network.	SAINT	2008	DBLP DOI BibTeX RDF	High-speed input/output interfaces, low power, CMOS
20	Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas	Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	leakage estimation, logic design, cmos gates
20	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed
20	Wonseok Oh 0003, Kang-Yeob Park, J.-C. Choi, C. J. Kim, S. I. Lee, J. K. Moon	Design of a 12-Channel 120-Gbs Optical Receiver Array in 0.18-µm CMOS Technology.	DELTA	2008	DBLP DOI BibTeX RDF	CMOS, OPTIC, RECEIVER, LA, TIA
20	Mikaël Cimino, Hervé Lapuyade, M. De Matos, Thierry Taris, Yann Deval, Jean-Baptiste Bégueret	A Robust 130 nm-CMOS Built-In Current Sensor Dedicated to RF Applications.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Analog and mixed-signal integrated circuits, Robustness, Design for testability, CMOS technology, Built-in current sensor
20	Garrett S. Rose, Yuxing Yao, James M. Tour, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, John C. Bean, Lloyd R. Harriott, Mircea R. Stan	Designing CMOS/molecular memories while considering device parameter variations.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	CMOS, nanotechnology, molecular electronics
20	Luca Benini, Carlotta Guiducci, Christian Paulus	Electronic Detection of DNA Hybridization: Toward CMOS Microarrays.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	CMOS microarrays, label-based DNA chip, label-free DNA chip, DNA hybridization
20	Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park	Leakage Minimization Technique for Nanoscale CMOS VLSI.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	nanometer CMOS, cell characterization, gate-tunneling current, input pattern generation, leakage power, subthreshold leakage current
20	Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi 0001, Masao Hotta	A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOS.	ASP-DAC	2007	DBLP DOI BibTeX RDF	2.8 V, bandpass delta-sigma AD modulator, second-order AD modulator, multibit switched-capacitor AD modulator, low-IF receivers, wireless communication systems, signal-to-noise-and-distortion, complex bandpass filter, dynamic matching, data-weighted averaging algorithm, 78 kHz, 28.4 mW, CMOS process, 0.18 micron
20	Minoru Watanabe, Fuminori Kobayashi	A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.35 micron, zero-overhead dynamic optically reconfigurable gate array VLSI, ZO-DORGA-VLSI, junction capacitance, photodiodes, load capacitance, configuration memory, CMOS process chip
20	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm
20	Leo Huf Campos Braga, Suzana Domingues, Milton F. Rocha, Leonardo Bruno de Sá, Fernando de Souza Campos, Filipe V. Santos, Antonio Carneiro de Mesquita Filho, Mário Vaz Silva, Jacobus W. Swart	Layout techniques for radiation hardening of standard CMOS active pixel sensors.	SBCCI	2007	DBLP DOI BibTeX RDF	radiation hardeness, CMOS, active pixel sensor
20	Ahmed A. Youssef	RF architectures in CMOS for the emerging wireless technologies: challenges and opportunities.	SBCCI	2007	DBLP DOI BibTeX RDF	integrated mobile communication systems, wireless, CMOS, RF
20	Walter J. Lancioni, Pablo A. Petrashin, Luis E. Toledo, Carlos Dualibe	A 9.6 kb/s CMOS FSK modem for data transmission through power lines.	SBCCI	2007	DBLP DOI BibTeX RDF	analog CMOS, power line transceiver, switched capacitor amplifier
20	Olivier Aubreton, Lew Fock Chong Lew Yan Voon, Bernard Lamalle, Guy Cathébras	A new method for implementing moment functions in a CMOS retina.	Mach. Vis. Appl.	2006	DBLP DOI BibTeX RDF	Moment function, CMOS retina, Dithering
20	Mikaël Cimino, Hervé Lapuyade, M. De Matos, Thierry Taris, Yann Deval, Jean-Baptiste Bégueret	A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications.	ETS	2006	DBLP DOI BibTeX RDF	Analog and mixed-signal integrated circuits, Robustness, Design for testability, CMOS technology, Built-In current sensor
20	Ana Isabela Araújo Cunha, Ali M. Niknejad	A general domain CMOS companding integrator.	SBCCI	2006	DBLP DOI BibTeX RDF	CMOS integrators, companding circuits, log-domain integrators, square-root domain integrators
20	Zhiyuan Li, Fengchang Lai, Mingyan Yu	Low-noise high-precision operational amplifier using vertical NPN transistor in CMOS technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	V-NPN transistor, deep n-well CMOS process, high-precision, input bias current cancellation, operational amplifier, low-noise
20	Jyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh, Hong-Ching Chen, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan Liu, Lily Huang, Chang-Long Wu, Meng-Hsueh Lin, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Hsiu-Chen Peng, Peng-Chuan Huang, Benjamin Chiu, Alex Ho	A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications.	DAC	2006	DBLP DOI BibTeX RDF	DVD-RAM, SATA, WSR, CMOS, optical storage
20	Pradip Bose	Presilicon modeling: challenges in the late CMOS era.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Integrated microarchitectures, special purpose accelerators, scalable on-chip interconnection network, presilicon modeling, CMOS
20	Edson P. Santana, N. R. Ferreira, Carlos Eduardo Trabuco Dórea, Ana Isabela Araújo Cunha	On the adequate transistor modeling for optimal design of CMOS OTA.	SBCCI	2005	DBLP DOI BibTeX RDF	ACM model, CMOS integrated circuits, operational transconductance amplifiers
20	Douglas Mercer	A low power current steering digital to analog converter in 0.18 Micron CMOS.	ISLPED	2005	DBLP DOI BibTeX RDF	CMOS, DAC, converter, current mode
20	Xinhua Chen, Qiuting Huang	A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13µm CMOS.	ISLPED	2005	DBLP DOI BibTeX RDF	low power, CMOS, WCDMA, phase-locked loop, frequency synthesizer
20	Saurabh Kumar Singh, T. K. Bhattacharyya, Ashudeb Dutta	Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications.	VLSI Design	2005	DBLP DOI BibTeX RDF	CMOS RF, ZigBee, Phase locked loop, Analog integrated circuits, Frequency synthesizer
20	Arun Natarajan 0001, Abbas Komijani, Ali Hajimiri	A 24 GHz phased-array transmitter in 0.18µm CMOS.	DAC	2005	DBLP DOI BibTeX RDF	24GHz, phased-array, wireless, CMOS, IC, transmitters
20	Luiz Alberto Pasini Melek, Márcio C. Schneider, Carlos Galup-Montoro	Body-bias compensation technique for SubThreshold CMOS static logic gates.	SBCCI	2004	DBLP DOI BibTeX RDF	body-bias compensation, static logic, low-power, CMOS, logic circuits, subthreshold
20	Virgínia Helena Varotto Baroncini, Oscar da Costa Gouveia-Filho	Design of RF CMOS low noise amplifiers using a current based MOSFET model.	SBCCI	2004	DBLP DOI BibTeX RDF	noise, CMOS, RF, LNA
20	Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez	Technology exploration for adaptive power and frequency scaling in 90nm CMOS.	ISLPED	2004	DBLP DOI BibTeX RDF	adaptive body bias, low power, CMOS, performance optimization, leakage, adaptive voltage scaling
20	H. C. Srinivasaiah, Navakanta Bhat	Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment.	VLSI Design	2004	DBLP DOI BibTeX RDF	Disposable spacer, Transmission of moments technique, Plackett-Burman design, Sensitivity analysis, Statistical modeling, CMOS technology, Response surface methodology, Monte carlo analysis
20	Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Robert Trzcinski, Mohamed Talbi, John Safran, Asit Ray, Lawrence F. Wagner	A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate.	ISLPED	2003	DBLP DOI BibTeX RDF	SOI CMOS, high resistivity substrate, phase NoiseFOM, low power, VCO, RF design
20	Jiwei Chen, Bingxue Shi	New approach to CMOS current reference with very low temperature coefficient.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	temperature coefficient, CMOS, current reference
20	Jiwei Chen, Bingxue Shi	Circuit design of a wide tuning range CMOS VCO with automatic amplitude control.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	automatic amplitude control, tuning range, CMOS, VCO
20	Carl De Ranter, Michiel Steyaert	Design techniques for low power high bandwidth upconversion in CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	upconversion, low power, CMOS, analog, oscillators, RF design
20	Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu	Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits.	DELTA	2002	DBLP DOI BibTeX RDF	Test generation, Fault simulation, Power dissipation, CMOS circuit
20	Michiel Steyaert, Peter J. Vancorenland	CMOS: a paradigm for low power wireless?	DAC	2002	DBLP DOI BibTeX RDF	low-power, wireless, CMOS, receivers
20	Avaneendra Gupta, John P. Hayes	CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	CMOS networks, circuit clustering, diffusion sharing, leaf cell synthesis, transistor chains, two-dimensional layout, integer programming, integer linear programming, layout optimization, module generation
20	Francesco Svelto, Stefano Deantoni, Giampiero Montagna, Rinaldo Castello	An 8mA, 3.8dB NF, 40dB gain CMOS front-end for GPS applications.	ISLPED	2000	DBLP DOI BibTeX RDF	circuit-analog, low-power dissipation, design, communication, low-power design, CMOS, performances trade-off
20	Carl James Debono, Franco Maloberti, Joseph Micallef	A low-voltage CMOS multiplier for RF applications (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF	CMOS, low-voltage, RF, analog multiplier
20	Alain-Serge Porret, Thierry Melly, Eric A. Vittoz, Christian C. Enz	Tradeoffs and design of an ultra low power UHF transceiver integrated in a standard digital CMOS process.	ISLPED	2000	DBLP DOI BibTeX RDF	low-power, CMOS, low-voltage, RF, transceiver
20	José Antonio Sainz, R. Muñoz, J. A. Maiz, L. A. Aguado, Miquel Roca 0001	A Crosstalk Sensor Implementation for Measuring Interferences in Digital CMOS VLSI Circuits.	IOLTW	2000	DBLP DOI BibTeX RDF	VLSI, Sensor, CMOS, Crosstalk, Digital
20	V. S. Gierenz, Oliver Weiss, Tobias G. Noll, I. Carew, Jonathan J. Ashley, Razmik Karabed	A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder.	ASAP	2000	DBLP DOI BibTeX RDF	disk-drive read channels, high-speed Viterbi decoder, radix-4 add-compare-select, bit-level pipelining, full-custom macros, datapath generator assisted design, 0.25 micron, 550 MHz, CMOS technology, redundant number representations
20	Takayasu Sakurai	Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control.	ISQED	2000	DBLP DOI BibTeX RDF	VDD, VTH, VLSI, Low-power, CMOS
20	Bedabrata Pain, Guang Yang 0003, Monico Ortiz, Kenneth McCarty, Julie Heynssens, Bruce Hancock, Thomas Cunningham, Chris Wrigley, Charlie Ho	A Single-Chip Programmable Digital CMOS Imager with Enhanced Low-Light Detection Capability.	VLSI Design	2000	DBLP DOI BibTeX RDF	low-power VLSI, camera-on-a-chip, digital imager, CMOS imager, APS, active pixel sensor
20	Rong Lin, Kevin E. Kerr, André S. Botha	A Novel Approach for CMOS Parallel Counter Design.	EUROMICRO	1999	DBLP DOI BibTeX RDF	parallel counter and compressor, low power high speed CMOS circuit design, VLSI design, Arithmetic circuit, partial product reduction
20	Eugenio García-Moreno, Benjamín Iñíguez, Miquel Roca 0001, Jaume Segura 0001, Eugeni Isern 0001	Clocked Dosimeter Compatible with Digital CMOS Technology.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	radiation dosimeter, radiation effects, digital circuits, CMOS technology
20	Labros Bisdounis, Odysseas G. Koufopavlou, Constantinos E. Goutis, Spiridon Nikolaidis 0001	Switching Response Modeling of the CMOS Inverter for Sub-micron Devices.	DATE	1998	DBLP DOI BibTeX RDF	CMOS circuits timing analysis, Propagation delay modeling, Sub-micron devices
20	Dhamin Al-Khalili, Saman Adham, Côme Rozon, Moazzem Hossain, Douglas Racz	Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits.	DFT	1998	DBLP DOI BibTeX RDF	CMOS Defect Modeling, Defect Analysis
20	Jacob J. Rael, Ahmadreza Rofougaran, Asad A. Abidi	Design Methodology Used in a Single-Chip CMOS 900 MHz Spread-Spectrum Wireless Transceiver.	DAC	1998	DBLP DOI BibTeX RDF	transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band
20	Jean-Paul Theis, Harald Schlimper	Ultrafast compact CMOS dividers.	ICPADS	1997	DBLP DOI BibTeX RDF	CMOS dividers, ultrafast, restoring division, floating-point division, 0.3 mum, parallelization, timing, layout, compact, dividing circuits, divider circuits
20	Rosa Rodríguez-Montañés, E. M. J. G. Bruls, Joan Figueras	Bridging defects resistance in the metal layer of a CMOS process.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	resistance of the bridge, defect modelling, bridging defects, CMOS process
20	Avaneendra Gupta, John P. Hayes	Width minimization of two-dimensional CMOS cells using integer programming.	ICCAD	1996	DBLP DOI BibTeX RDF	leaf cell synthesis, two-dimensional layout, diffusion sharing, transistor chains, CMOS networks, Layout optimization, module generation
20	Dennis J. Ciplickas, Ronald A. Rohrer	Expected current distributions for CMOS circuits.	ICCAD	1996	DBLP DOI BibTeX RDF	switching current, expected waveform, mean estimation, static analysis, statistical analysis, CMOS, autocorrelation, random processes, power spectral density
20	Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò	Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	CMOS, testability, Bridging fault, self-checking circuits, checker
20	Joan Figueras, Michel Renovell	Current testing in dynamic CMOS circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	dynamic CMOS, test technique, integrated circuit, Current testing
20	Rene David, S. Rahal, J. L. Rainard	Some relationships between delay testing and stuck-open testing in CMOS circuits.	EURO-DAC	1990	DBLP DOI BibTeX RDF	stuck-open, combinational circuits, CMOS, Delay testing, robust test
20	Michael Walter Payton, Fat Duen Ho	A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR gate and the CMOS NAND gate.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
20	Shrutin Ulman	Macromodel for short circuit power dissipation of submicron CMOS inverters and its application to design CMOS buffers.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
20	E. Shen, J. B. Kuo	0.8 V CMOS content-addressable-memory (CAM) cell circuit with a fast tag-compare capability using bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology for low-voltage VLSI systems.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
19	Lakshmi N. Chakrapani, Pinar Korkmaz, Bilge Saglam Akgul, Krishna V. Palem	Probabilistic system-on-a-chip architectures.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Embedded systems, probabilistic computing
19	Mohammad Tehranipoor, Reza M. Rad	Fine-grained island style architecture for molecular electronic devices.	FPGA	2006	DBLP DOI BibTeX RDF
19	Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang	Energy-efficient skewed static logic with dual Vt: design and synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
19	Jérôme Goy	Etude, conception, et réalisation d'un capteur d'image APS en technologie standard CMOS pour des applications faible flux de type viseur d'étoiles = Study, conception and fabrication of an APS image sensor in standard CMOS technology for low light level applications such as star trackers. (Study, conception and fabrication of an APS image sensor in standard CMOS technology for low light level applications such as star trackers).		2002	RDF
18	Chen Chen 0018, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Efficient FPGAs using nanoelectromechanical relays.	FPGA	2010	DBLP DOI BibTeX RDF	CMOS-NEM FPGA, nanoelectromechanical relay
18	Ruchir Puri	Will 22nm be our catch 22!: design and cad challenges.	ISPD	2009	DBLP DOI BibTeX RDF	22nm cmos, design productivity, vlsi cad challenges, vlsi design challenges, vlsi physical design, 3d ics, automated synthesis
18	Yang Liu, Ashok Kumar Srivastava, Yao Xu	A switchable PLL frequency synthesizer and hot carrier effects.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	cmos phase-locked loop, hot carrier effects, jitter, voltage-controlled oscillator, phase noise
18	Fernando da Rocha Paixão Cortes, Sergio Bampi	A 40mhz 70db gain variable gain amplifier design using the gm/id design method.	SBCCI	2008	DBLP DOI BibTeX RDF	Variable Gain Amplifier (VGA), cmos analog design, rf front-end, amplifier
18	Emilia Sipos, Lelia Festila, Gabriel Oltean	Towards Reconfigurable Circuits Based on Ternary Controlled Analog Multiplexers/Demultiplexers.	KES (3)	2008	DBLP DOI BibTeX RDF	Analog multiplexer, reconfigurable circuit, transmission gate, CMOS transistors, SUS-LOC
18	Jaeyong Lee, Sungil Cho, Kwangsub Yoon	12bits 40mhz pipelined ADC with duty-correction circuit.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	adc(analog-to-digital converter), pipeline, cmos, dll
18	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process
18	Zhiyu Liu, Volkan Kursun	Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS.	ISQED	2007	DBLP DOI BibTeX RDF	Multi-threshold voltage CMOS, gated power, gated ground, sleep switch, subthreshold leakage, charge recycling
18	Hsing-Wen Wang	Identification of Characteristics After Soft Breakdown with GA-Based Neural Networks.	IEA/AIE	2006	DBLP DOI BibTeX RDF	Low-frequency noise, soft breakdown, degraded characteristics, CMOS, evolutionary neural networks
18	Mohammad H. Rahimi, Shaun Ahmadian, David Zats, Rick Baer, Deborah Estrin, Mani B. Srivastava	Network of cyclops; image inference and interpretation in sensor network.	SenSys	2005	DBLP DOI BibTeX RDF	sensor network, imaging, object detection, vision, power efficiency, CMOS imaging
18	Mohammad H. Rahimi, Rick Baer, Obimdinachi I. Iroezi, Juan C. García, Jay Warrior, Deborah Estrin, Mani B. Srivastava	Cyclops: in situ image sensing and interpretation in wireless sensor networks.	SenSys	2005	DBLP DOI BibTeX RDF	sensor network, imaging, vision, power efficiency, CMOS imaging
18	Carlos Dualibe, Pablo A. Petrashin, Luis E. Toledo, Walter J. Lancioni	New low-voltage electrically tunable triode-MOSFET transconductor and its application to low-frequency Gm-C filtering.	SBCCI	2005	DBLP DOI BibTeX RDF	Gm-C filter, analog CMOS, low-frequency, transconductor, low-power, low-voltage, instrumentation amplifier
18	Manmohan Krishna Chandraker, Christoph Stock, Axel Pinz	Real-Time Camera Pose in a Room.	ICVS	2003	DBLP DOI BibTeX RDF	CMOS camera, sparse 3D modeling, Tracking, camera pose
18	Qi Wang, Sarma B. K. Vrudhula, Gary K. H. Yeap, Shantanu Ganguly	Power reduction and power-delay trade-offs using logic transformations.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF	CMOS logic, low power, logic synthesis, power estimation, logic optimization
18	Qi Wang, Sarma B. K. Vrudhula	Multi-level logic optimization for low power using local logic transformations.	ICCAD	1996	DBLP DOI BibTeX RDF	Logic Optimization Digital Circuits, CMOS combinatinal circuits, Low Power, Logic Synthesis
18	Jerry M. Soden, Charles F. Hawkins, Ravi K. Gulati, Weiwei Mao	IDDQ testing: A review.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	IC quality, fault models, defects, Current testing, CMOS IC, I DDQ
18	Josep Rius 0001, Joan Figueras	Proportional BIC sensor for current testing.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	Built-in integrated sensor, CMOS lateral BJT, gate controlled BJT, I DDQ measure, current test
18	Wei Zhang 0012, Niraj K. Jha, Li Shang	A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	design optimization flow, logic folding, Dynamic reconfiguration, NATURE
18	Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha	A hybrid nano-CMOS architecture for defect and fault tolerance.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	nanotechnology, Defect tolerance, nanowires
18	Eduardo José Solteiro Pires, Luís Mendes, Paulo B. de Moura Oliveira, José António Tenreiro Machado, João Caldinhas Vaz, Maria João Rosário	Design of Radio-Frequency Integrated CMOS Discrete Tuning Varactors Using the Particle Swarm Optimization Algorithm.	IWANN (2)	2009	DBLP DOI BibTeX RDF	automated circuit synthesis and radio-frequency integrated circuits, Particle swarm optimization, analog circuit design
18	Karthik Rajagopal, Aatmesh, Vinod Menezes	An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process.	ISQED	2009	DBLP DOI BibTeX RDF
18	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments.	ISQED	2009	DBLP DOI BibTeX RDF
18	S. Ramasamy, B. Venkataramani, R. Niranjini, K. Suganya	100KHz-20MHz Programmable Subthreshold Gm-C Low-Pass Filter in 0.18µ-m CMOS.	VLSI Design	2009	DBLP DOI BibTeX RDF
18	J.-C. Guo, Y.-M. Lin	A Compact RF CMOS Modeling for Accurate High-Frequency Noise Simulation in Sub-100-nm MOSFETs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
18	James Alfred Walker, James A. Hilder, Andy M. Tyrrell	Evolving Variability-Tolerant CMOS Designs.	ICES	2008	DBLP DOI BibTeX RDF
18	Wen-Chieh Wang, Chang-Ping Liao, Yi-Kai Lo, Zue-Der Huang, Fadi Riad Shahroury, Chung-Yu Wu	The design of integrated 3-GHz to 11-GHz CMOS transmitter for full-band ultra-wideband (UWB) applications.	ISCAS	2008	DBLP DOI BibTeX RDF
18	Kumar Yelamarthi, Chien-In Henry Chen	Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic.	ISQED	2008	DBLP DOI BibTeX RDF	binary-to-thermometer decoder, process variations, timing optimization, transistor sizing, dynamic circuits, binary adders
18	S. Ramasamy, B. Venkataramani, K. Anbugeetha	VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair.	VLSI Design	2008	DBLP DOI BibTeX RDF
18	Kazuhiro Shimizu, Shinichi Hirai	Realtime and Robust Motion Tracking by Matched Filter on CMOS+FPGA Vision System.	ICRA	2007	DBLP DOI BibTeX RDF