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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5098 occurrences of 1721 keywords
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Results
Found 24872 publication records. Showing 24872 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
20 | Luiz Carlos Moreira, Wilhelmus A. M. Van Noije, Armando Ayala Pabón, Andrés Farfán-Peláez |
Comparison of small cross inductors and rectangular inductors designed in 0.35um CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
cross inductors, rectangular inductors, RF CMOS |
20 | Hussain A. Alzaher, Noman Tasadduq |
A CMOS low power current-mode polyphase filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 75-80, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CMOS analog integrated circuits, low power current mode circuit, polyphase filter |
20 | Kaushik Roy 0001 |
Ultra low voltage CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 425-426, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
adaptive supply scaling, nano-scale cmos system, ultra low voltage design, ultra-dynamic voltage scaling |
20 | Kelin J. Kuhn |
CMOS scaling beyond 32nm: challenges and opportunities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 310-313, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
high-k, CMOS, orientation, strain, metal-gate |
20 | Shekhar Borkar |
Design perspectives on 22nm CMOS and beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 93-94, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
nano, power, CMOS, variability |
20 | Kristian Granhaug, Snorre Aunet |
Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 157-163, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Subthreshold CMOS, Output-wired redundancy, Yield and defect tolerance |
20 | Bangli Liang, Tad A. Kwasniewski, Dianyong Chen |
A 42-Gb/s Decision Circuit in 0.13µm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CNSR ![In: Sixth Annual Conference on Communication Networks and Services Research (CNSR 2008), 5-8 May 2008, Halifax, Nova Scotia, Canada, pp. 339-342, 2008, IEEE Computer Society, 978-0-7695-3135-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CMOS CML, Shunt peaking, Split-resistor, Optical communication |
20 | Pablo Aguirre, Fernando Silveira |
CMOS op-amp power optimization in all regions of inversion using geometric programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 152-157, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
optimization, CMOS, analog, geometric programming, automatic design |
20 | Victor Ariel Leal Sobral, Roberto Espinheira da Costa Bomfim, Robson Nunes de Lima, Ana Isabela Araújo Cunha |
Systematic methodology for the design of Seevinck's CMOS log-domain integrators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 158-163, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CMOS integrators, companding circuits, log-domain integrators |
20 | Tadashi Ikeuchi, Tszshing Cheung, Hiroshi Onaka |
The Latest Trend of Low Power High-Speed CMOS I/O Technology for Photonic Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAINT ![In: Proceedings of the 2008 International Symposium on Applications and the Internet, SAINT 2008, 28 July - 1 August 2008, Turku, Finland, pp. 397-400, 2008, IEEE Computer Society, 978-0-7695-3297-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
High-speed input/output interfaces, low power, CMOS |
20 | Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas |
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 407-410, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
leakage estimation, logic design, cmos gates |
20 | Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos |
A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 47-52, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed |
20 | Wonseok Oh 0003, Kang-Yeob Park, J.-C. Choi, C. J. Kim, S. I. Lee, J. K. Moon |
Design of a 12-Channel 120-Gbs Optical Receiver Array in 0.18-µm CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 71-74, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CMOS, OPTIC, RECEIVER, LA, TIA |
20 | Mikaël Cimino, Hervé Lapuyade, M. De Matos, Thierry Taris, Yann Deval, Jean-Baptiste Bégueret |
A Robust 130 nm-CMOS Built-In Current Sensor Dedicated to RF Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(6), pp. 593-603, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Analog and mixed-signal integrated circuits, Robustness, Design for testability, CMOS technology, Built-in current sensor |
20 | Garrett S. Rose, Yuxing Yao, James M. Tour, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, John C. Bean, Lloyd R. Harriott, Mircea R. Stan |
Designing CMOS/molecular memories while considering device parameter variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 3(1), pp. 3, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
CMOS, nanotechnology, molecular electronics |
20 | Luca Benini, Carlotta Guiducci, Christian Paulus |
Electronic Detection of DNA Hybridization: Toward CMOS Microarrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(1), pp. 38-48, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
CMOS microarrays, label-based DNA chip, label-free DNA chip, DNA hybridization |
20 | Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park |
Leakage Minimization Technique for Nanoscale CMOS VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(4), pp. 322-330, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
nanometer CMOS, cell characterization, gate-tunneling current, input pattern generation, leakage power, subthreshold leakage current |
20 | Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi 0001, Masao Hotta |
A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 96-97, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
2.8 V, bandpass delta-sigma AD modulator, second-order AD modulator, multibit switched-capacitor AD modulator, low-IF receivers, wireless communication systems, signal-to-noise-and-distortion, complex bandpass filter, dynamic matching, data-weighted averaging algorithm, 78 kHz, 28.4 mW, CMOS process, 0.18 micron |
20 | Minoru Watanabe, Fuminori Kobayashi |
A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 124-125, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
0.35 micron, zero-overhead dynamic optically reconfigurable gate array VLSI, ZO-DORGA-VLSI, junction capacitance, photodiodes, load capacitance, configuration memory, CMOS process chip |
20 | Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi |
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 654-659, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm |
20 | Leo Huf Campos Braga, Suzana Domingues, Milton F. Rocha, Leonardo Bruno de Sá, Fernando de Souza Campos, Filipe V. Santos, Antonio Carneiro de Mesquita Filho, Mário Vaz Silva, Jacobus W. Swart |
Layout techniques for radiation hardening of standard CMOS active pixel sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 257-262, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
radiation hardeness, CMOS, active pixel sensor |
20 | Ahmed A. Youssef |
RF architectures in CMOS for the emerging wireless technologies: challenges and opportunities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 6, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
integrated mobile communication systems, wireless, CMOS, RF |
20 | Walter J. Lancioni, Pablo A. Petrashin, Luis E. Toledo, Carlos Dualibe |
A 9.6 kb/s CMOS FSK modem for data transmission through power lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 117-122, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
analog CMOS, power line transceiver, switched capacitor amplifier |
20 | Olivier Aubreton, Lew Fock Chong Lew Yan Voon, Bernard Lamalle, Guy Cathébras |
A new method for implementing moment functions in a CMOS retina. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mach. Vis. Appl. ![In: Mach. Vis. Appl. 16(6), pp. 384-392, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Moment function, CMOS retina, Dithering |
20 | Mikaël Cimino, Hervé Lapuyade, M. De Matos, Thierry Taris, Yann Deval, Jean-Baptiste Bégueret |
A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pp. 151-158, 2006, IEEE Computer Society, 0-7695-2566-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Analog and mixed-signal integrated circuits, Robustness, Design for testability, CMOS technology, Built-In current sensor |
20 | Ana Isabela Araújo Cunha, Ali M. Niknejad |
A general domain CMOS companding integrator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 108-112, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
CMOS integrators, companding circuits, log-domain integrators, square-root domain integrators |
20 | Zhiyuan Li, Fengchang Lai, Mingyan Yu |
Low-noise high-precision operational amplifier using vertical NPN transistor in CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 123-126, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
V-NPN transistor, deep n-well CMOS process, high-precision, input bias current cancellation, operational amplifier, low-noise |
20 | Jyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh, Hong-Ching Chen, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan Liu, Lily Huang, Chang-Long Wu, Meng-Hsueh Lin, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Hsiu-Chen Peng, Peng-Chuan Huang, Benjamin Chiu, Alex Ho |
A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 290-291, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
DVD-RAM, SATA, WSR, CMOS, optical storage |
20 | Pradip Bose |
Presilicon modeling: challenges in the late CMOS era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 25(4), pp. 5-6, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Integrated microarchitectures, special purpose accelerators, scalable on-chip interconnection network, presilicon modeling, CMOS |
20 | Edson P. Santana, N. R. Ferreira, Carlos Eduardo Trabuco Dórea, Ana Isabela Araújo Cunha |
On the adequate transistor modeling for optimal design of CMOS OTA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 27-31, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ACM model, CMOS integrated circuits, operational transconductance amplifiers |
20 | Douglas Mercer |
A low power current steering digital to analog converter in 0.18 Micron CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 72-77, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
CMOS, DAC, converter, current mode |
20 | Xinhua Chen, Qiuting Huang |
A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13µm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 66-71, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low power, CMOS, WCDMA, phase-locked loop, frequency synthesizer |
20 | Saurabh Kumar Singh, T. K. Bhattacharyya, Ashudeb Dutta |
Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 780-783, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
CMOS RF, ZigBee, Phase locked loop, Analog integrated circuits, Frequency synthesizer |
20 | Arun Natarajan 0001, Abbas Komijani, Ali Hajimiri |
A 24 GHz phased-array transmitter in 0.18µm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 551-552, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
24GHz, phased-array, wireless, CMOS, IC, transmitters |
20 | Luiz Alberto Pasini Melek, Márcio C. Schneider, Carlos Galup-Montoro |
Body-bias compensation technique for SubThreshold CMOS static logic gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 267-272, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
body-bias compensation, static logic, low-power, CMOS, logic circuits, subthreshold |
20 | Virgínia Helena Varotto Baroncini, Oscar da Costa Gouveia-Filho |
Design of RF CMOS low noise amplifiers using a current based MOSFET model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 82-87, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
noise, CMOS, RF, LNA |
20 | Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez |
Technology exploration for adaptive power and frequency scaling in 90nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 14-19, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
adaptive body bias, low power, CMOS, performance optimization, leakage, adaptive voltage scaling |
20 | H. C. Srinivasaiah, Navakanta Bhat |
Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 285-290, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Disposable spacer, Transmission of moments technique, Plackett-Burman design, Sensitivity analysis, Statistical modeling, CMOS technology, Response surface methodology, Monte carlo analysis |
20 | Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Robert Trzcinski, Mohamed Talbi, John Safran, Asit Ray, Lawrence F. Wagner |
A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 434-439, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
SOI CMOS, high resistivity substrate, phase NoiseFOM, low power, VCO, RF design |
20 | Jiwei Chen, Bingxue Shi |
New approach to CMOS current reference with very low temperature coefficient. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 281-284, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
temperature coefficient, CMOS, current reference |
20 | Jiwei Chen, Bingxue Shi |
Circuit design of a wide tuning range CMOS VCO with automatic amplitude control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 124-127, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
automatic amplitude control, tuning range, CMOS, VCO |
20 | Carl De Ranter, Michiel Steyaert |
Design techniques for low power high bandwidth upconversion in CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 237-242, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
upconversion, low power, CMOS, analog, oscillators, RF design |
20 | Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu |
Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 431-433, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Test generation, Fault simulation, Power dissipation, CMOS circuit |
20 | Michiel Steyaert, Peter J. Vancorenland |
CMOS: a paradigm for low power wireless? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 836-841, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
low-power, wireless, CMOS, receivers |
20 | Avaneendra Gupta, John P. Hayes |
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(3), pp. 510-547, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
CMOS networks, circuit clustering, diffusion sharing, leaf cell synthesis, transistor chains, two-dimensional layout, integer programming, integer linear programming, layout optimization, module generation |
20 | Francesco Svelto, Stefano Deantoni, Giampiero Montagna, Rinaldo Castello |
An 8mA, 3.8dB NF, 40dB gain CMOS front-end for GPS applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 279-283, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
circuit-analog, low-power dissipation, design, communication, low-power design, CMOS, performances trade-off |
20 | Carl James Debono, Franco Maloberti, Joseph Micallef |
A low-voltage CMOS multiplier for RF applications (poster session). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 225-227, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
CMOS, low-voltage, RF, analog multiplier |
20 | Alain-Serge Porret, Thierry Melly, Eric A. Vittoz, Christian C. Enz |
Tradeoffs and design of an ultra low power UHF transceiver integrated in a standard digital CMOS process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 273-278, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low-power, CMOS, low-voltage, RF, transceiver |
20 | José Antonio Sainz, R. Muñoz, J. A. Maiz, L. A. Aguado, Miquel Roca 0001 |
A Crosstalk Sensor Implementation for Measuring Interferences in Digital CMOS VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 45-51, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
VLSI, Sensor, CMOS, Crosstalk, Digital |
20 | V. S. Gierenz, Oliver Weiss, Tobias G. Noll, I. Carew, Jonathan J. Ashley, Razmik Karabed |
A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 195-, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
disk-drive read channels, high-speed Viterbi decoder, radix-4 add-compare-select, bit-level pipelining, full-custom macros, datapath generator assisted design, 0.25 micron, 550 MHz, CMOS technology, redundant number representations |
20 | Takayasu Sakurai |
Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 417-424, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
VDD, VTH, VLSI, Low-power, CMOS |
20 | Bedabrata Pain, Guang Yang 0003, Monico Ortiz, Kenneth McCarty, Julie Heynssens, Bruce Hancock, Thomas Cunningham, Chris Wrigley, Charlie Ho |
A Single-Chip Programmable Digital CMOS Imager with Enhanced Low-Light Detection Capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 342-349, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low-power VLSI, camera-on-a-chip, digital imager, CMOS imager, APS, active pixel sensor |
20 | Rong Lin, Kevin E. Kerr, André S. Botha |
A Novel Approach for CMOS Parallel Counter Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1112-1119, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
parallel counter and compressor, low power high speed CMOS circuit design, VLSI design, Arithmetic circuit, partial product reduction |
20 | Eugenio García-Moreno, Benjamín Iñíguez, Miquel Roca 0001, Jaume Segura 0001, Eugeni Isern 0001 |
Clocked Dosimeter Compatible with Digital CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(1-2), pp. 101-110, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
radiation dosimeter, radiation effects, digital circuits, CMOS technology |
20 | Labros Bisdounis, Odysseas G. Koufopavlou, Constantinos E. Goutis, Spiridon Nikolaidis 0001 |
Switching Response Modeling of the CMOS Inverter for Sub-micron Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 729-735, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
CMOS circuits timing analysis, Propagation delay modeling, Sub-micron devices |
20 | Dhamin Al-Khalili, Saman Adham, Côme Rozon, Moazzem Hossain, Douglas Racz |
Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 84-92, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
CMOS Defect Modeling, Defect Analysis |
20 | Jacob J. Rael, Ahmadreza Rofougaran, Asad A. Abidi |
Design Methodology Used in a Single-Chip CMOS 900 MHz Spread-Spectrum Wireless Transceiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 44-49, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band |
20 | Jean-Paul Theis, Harald Schlimper |
Ultrafast compact CMOS dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 11-13 December 1997, Seoul, Korea, Proceedings, pp. 116-121, 1997, IEEE Computer Society, 0-8186-8227-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
CMOS dividers, ultrafast, restoring division, floating-point division, 0.3 mum, parallelization, timing, layout, compact, dividing circuits, divider circuits |
20 | Rosa Rodríguez-Montañés, E. M. J. G. Bruls, Joan Figueras |
Bridging defects resistance in the metal layer of a CMOS process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(1), pp. 35-46, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
resistance of the bridge, defect modelling, bridging defects, CMOS process |
20 | Avaneendra Gupta, John P. Hayes |
Width minimization of two-dimensional CMOS cells using integer programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 660-667, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
leaf cell synthesis, two-dimensional layout, diffusion sharing, transistor chains, CMOS networks, Layout optimization, module generation |
20 | Dennis J. Ciplickas, Ronald A. Rohrer |
Expected current distributions for CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 589-592, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
switching current, expected waveform, mean estimation, static analysis, statistical analysis, CMOS, autocorrelation, random processes, power spectral density |
20 | Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò |
Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(1), pp. 7-22, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CMOS, testability, Bridging fault, self-checking circuits, checker |
20 | Joan Figueras, Michel Renovell |
Current testing in dynamic CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(1), pp. 127-131, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
dynamic CMOS, test technique, integrated circuit, Current testing |
20 | Rene David, S. Rahal, J. L. Rainard |
Some relationships between delay testing and stuck-open testing in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 339-343, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
stuck-open, combinational circuits, CMOS, Delay testing, robust test |
20 | Michael Walter Payton, Fat Duen Ho |
A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR gate and the CMOS NAND gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5657-5661, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Shrutin Ulman |
Macromodel for short circuit power dissipation of submicron CMOS inverters and its application to design CMOS buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 269-272, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | E. Shen, J. B. Kuo |
0.8 V CMOS content-addressable-memory (CAM) cell circuit with a fast tag-compare capability using bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology for low-voltage VLSI systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 583-586, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Lakshmi N. Chakrapani, Pinar Korkmaz, Bilge Saglam Akgul, Krishna V. Palem |
Probabilistic system-on-a-chip architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(3), pp. 29:1-29:28, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Embedded systems, probabilistic computing |
19 | Mohammad Tehranipoor, Reza M. Rad |
Fine-grained island style architecture for molecular electronic devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 226, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang |
Energy-efficient skewed static logic with dual Vt: design and synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(1), pp. 64-70, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Jérôme Goy |
Etude, conception, et réalisation d'un capteur d'image APS en technologie standard CMOS pour des applications faible flux de type viseur d'étoiles = Study, conception and fabrication of an APS image sensor in standard CMOS technology for low light level applications such as star trackers. (Study, conception and fabrication of an APS image sensor in standard CMOS technology for low light level applications such as star trackers). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2002 |
RDF |
|
18 | Chen Chen 0018, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra |
Efficient FPGAs using nanoelectromechanical relays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 273-282, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
CMOS-NEM FPGA, nanoelectromechanical relay |
18 | Ruchir Puri |
Will 22nm be our catch 22!: design and cad challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 59-60, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
22nm cmos, design productivity, vlsi cad challenges, vlsi design challenges, vlsi physical design, 3d ics, automated synthesis |
18 | Yang Liu, Ashok Kumar Srivastava, Yao Xu |
A switchable PLL frequency synthesizer and hot carrier effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 481-486, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
cmos phase-locked loop, hot carrier effects, jitter, voltage-controlled oscillator, phase noise |
18 | Fernando da Rocha Paixão Cortes, Sergio Bampi |
A 40mhz 70db gain variable gain amplifier design using the gm/id design method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 76-80, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Variable Gain Amplifier (VGA), cmos analog design, rf front-end, amplifier |
18 | Emilia Sipos, Lelia Festila, Gabriel Oltean |
Towards Reconfigurable Circuits Based on Ternary Controlled Analog Multiplexers/Demultiplexers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (3) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 12th International Conference, KES 2008, Zagreb, Croatia, September 3-5, 2008, Proceedings, Part III, pp. 351-359, 2008, Springer, 978-3-540-85566-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Analog multiplexer, reconfigurable circuit, transmission gate, CMOS transistors, SUS-LOC |
18 | Jaeyong Lee, Sungil Cho, Kwangsub Yoon |
12bits 40mhz pipelined ADC with duty-correction circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 441-444, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
adc(analog-to-digital converter), pipeline, cmos, dll |
18 | Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry |
A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 678-683, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process |
18 | Zhiyu Liu, Volkan Kursun |
Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 239-244, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Multi-threshold voltage CMOS, gated power, gated ground, sleep switch, subthreshold leakage, charge recycling |
18 | Hsing-Wen Wang |
Identification of Characteristics After Soft Breakdown with GA-Based Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEA/AIE ![In: Advances in Applied Artificial Intelligence, 19th International Conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems, IEA/AIE 2006, Annecy, France, June 27-30, 2006, Proceedings, pp. 564-572, 2006, Springer, 3-540-35453-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Low-frequency noise, soft breakdown, degraded characteristics, CMOS, evolutionary neural networks |
18 | Mohammad H. Rahimi, Shaun Ahmadian, David Zats, Rick Baer, Deborah Estrin, Mani B. Srivastava |
Network of cyclops; image inference and interpretation in sensor network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SenSys ![In: Proceedings of the 3rd International Conference on Embedded Networked Sensor Systems, SenSys 2005, San Diego, California, USA, November 2-4, 2005, pp. 310, 2005, ACM, 1-59593-054-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
sensor network, imaging, object detection, vision, power efficiency, CMOS imaging |
18 | Mohammad H. Rahimi, Rick Baer, Obimdinachi I. Iroezi, Juan C. García, Jay Warrior, Deborah Estrin, Mani B. Srivastava |
Cyclops: in situ image sensing and interpretation in wireless sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SenSys ![In: Proceedings of the 3rd International Conference on Embedded Networked Sensor Systems, SenSys 2005, San Diego, California, USA, November 2-4, 2005, pp. 192-204, 2005, ACM, 1-59593-054-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
sensor network, imaging, vision, power efficiency, CMOS imaging |
18 | Carlos Dualibe, Pablo A. Petrashin, Luis E. Toledo, Walter J. Lancioni |
New low-voltage electrically tunable triode-MOSFET transconductor and its application to low-frequency Gm-C filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 207-212, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Gm-C filter, analog CMOS, low-frequency, transconductor, low-power, low-voltage, instrumentation amplifier |
18 | Manmohan Krishna Chandraker, Christoph Stock, Axel Pinz |
Real-Time Camera Pose in a Room. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICVS ![In: Computer Vision Systems, Third International Conference, ICVS 2003, Graz, Austria, April 1-3, 2003, Proceedings, pp. 98-110, 2003, Springer, 3-540-00921-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
CMOS camera, sparse 3D modeling, Tracking, camera pose |
18 | Qi Wang, Sarma B. K. Vrudhula, Gary K. H. Yeap, Shantanu Ganguly |
Power reduction and power-delay trade-offs using logic transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 4(1), pp. 97-121, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
CMOS logic, low power, logic synthesis, power estimation, logic optimization |
18 | Qi Wang, Sarma B. K. Vrudhula |
Multi-level logic optimization for low power using local logic transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 270-277, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Logic Optimization Digital Circuits, CMOS combinatinal circuits, Low Power, Logic Synthesis |
18 | Jerry M. Soden, Charles F. Hawkins, Ravi K. Gulati, Weiwei Mao |
IDDQ testing: A review. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 291-303, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
IC quality, fault models, defects, Current testing, CMOS IC, I DDQ |
18 | Josep Rius 0001, Joan Figueras |
Proportional BIC sensor for current testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 387-396, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
Built-in integrated sensor, CMOS lateral BJT, gate controlled BJT, I DDQ measure, current test |
18 | Wei Zhang 0012, Niraj K. Jha, Li Shang |
A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 5(3), pp. 13:1-13:31, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
design optimization flow, logic folding, Dynamic reconfiguration, NATURE |
18 | Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha |
A hybrid nano-CMOS architecture for defect and fault tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 5(3), pp. 14:1-14:26, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
nanotechnology, Defect tolerance, nanowires |
18 | Eduardo José Solteiro Pires, Luís Mendes, Paulo B. de Moura Oliveira, José António Tenreiro Machado, João Caldinhas Vaz, Maria João Rosário |
Design of Radio-Frequency Integrated CMOS Discrete Tuning Varactors Using the Particle Swarm Optimization Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN (2) ![In: Distributed Computing, Artificial Intelligence, Bioinformatics, Soft Computing, and Ambient Assisted Living, 10th International Work-Conference on Artificial Neural Networks, IWANN 2009 Workshops, Salamanca, Spain, June 10-12, 2009. Proceedings, Part II, pp. 1231-1239, 2009, Springer, 978-3-642-02480-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
automated circuit synthesis and radio-frequency integrated circuits, Particle swarm optimization, analog circuit design |
18 | Karthik Rajagopal, Aatmesh, Vinod Menezes |
An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 103-106, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos |
Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 172-178, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | S. Ramasamy, B. Venkataramani, R. Niranjini, K. Suganya |
100KHz-20MHz Programmable Subthreshold Gm-C Low-Pass Filter in 0.18µ-m CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 105-110, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | J.-C. Guo, Y.-M. Lin |
A Compact RF CMOS Modeling for Accurate High-Frequency Noise Simulation in Sub-100-nm MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9), pp. 1684-1688, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | James Alfred Walker, James A. Hilder, Andy M. Tyrrell |
Evolving Variability-Tolerant CMOS Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 8th International Conference, ICES 2008, Prague, Czech Republic, September 21-24, 2008. Proceedings, pp. 308-319, 2008, Springer, 978-3-540-85856-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Wen-Chieh Wang, Chang-Ping Liao, Yi-Kai Lo, Zue-Der Huang, Fadi Riad Shahroury, Chung-Yu Wu |
The design of integrated 3-GHz to 11-GHz CMOS transmitter for full-band ultra-wideband (UWB) applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2709-2712, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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18 | Kumar Yelamarthi, Chien-In Henry Chen |
Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 143-147, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
binary-to-thermometer decoder, process variations, timing optimization, transistor sizing, dynamic circuits, binary adders |
18 | S. Ramasamy, B. Venkataramani, K. Anbugeetha |
VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 317-322, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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18 | Kazuhiro Shimizu, Shinichi Hirai |
Realtime and Robust Motion Tracking by Matched Filter on CMOS+FPGA Vision System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 2007 IEEE International Conference on Robotics and Automation, ICRA 2007, 10-14 April 2007, Roma, Italy, pp. 788-793, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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