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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 897 occurrences of 542 keywords
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Results
Found 1809 publication records. Showing 1806 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
31 | Chennian Di, Jochen A. G. Jess |
An efficient CMOS bridging fault simulator: with SPICE accuracy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9), pp. 1071-1080, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
31 | Michael M. Green, Alan N. Willson Jr. |
An algorithm for identifying unstable operating points using SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3), pp. 360-370, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
31 | Hong June Park, Ping Keung Ko, Chenming Hu |
A non-quasi-static MOSFET model for SPICE-AC analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(10), pp. 1247-1257, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
31 | Hong June Park, Ping Keung Ko, Chenming Hu |
A charge sheet capacitance model of short channel MOSFETs for SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(3), pp. 376-389, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
31 | R. J. McDonald, Jerry G. Fossum |
High-voltage device modeling for SPICE simulation of HVIC's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(3), pp. 425-432, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
30 | Ning Lu, Judy H. McCullen |
Enablement of Variation-Aware Timing: Treatment of Parasitic Resistance and Capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 743-748, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu |
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 583-588, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Jun Chen 0008, Lei He 0001 |
Piecewise linear model for transmission line with capacitive loading and ramp input. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6), pp. 928-937, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Gregory Munson Yeric, A. F. Tasch Jr., Sanjay K. Banerjee |
A universal MOSFET mobility degradation model for circuit simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(10), pp. 1123-1126, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
30 | Chung-Ping Wan, Bing J. Sheu, Shih-Lien Lu |
Device and circuit simulation interface for an integrated VLSI design environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(9), pp. 998-1004, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
24 | Ning Li, Huaxiang Lu |
Single-electron tunneling depressing synapse for cellular neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. Appl. ![In: Neural Comput. Appl. 17(2), pp. 111-118, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Cellular non-linear networks (CNN), Depressing synapses, Single-electron tunneling (SET), Tunneling junction, SPICE |
24 | Marcus Ciolkowski, Martín Soto |
Towards a Process Maturity Model for Open Source Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPSAC ![In: Proceedings of the 32nd Annual IEEE International Computer Software and Applications Conference, COMPSAC 2008, 28 July - 1 August 2008, Turku, Finland, pp. 1213-1214, 2008, IEEE Computer Society, 978-0-7695-3262-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Process Maturity Model, Open Source Software, SPICE, CMMI, Process Assessment |
24 | Ning Lu |
Statistical Models and Frequency-Dependent Corner Models for Passive Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 543-548, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SPICE models, corner models, RF models, passive devices, statistical models |
24 | Fergal McCaffery, Minna Pikkarainen, Ita Richardson |
Ahaa --agile, hybrid assessment method for automotive, safety critical smes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE ![In: 30th International Conference on Software Engineering (ICSE 2008), Leipzig, Germany, May 10-18, 2008, pp. 551-560, 2008, ACM, 978-1-60558-079-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
assessment methods, automotive spice, software process improvement, cmmi, safety-critical, agile practices |
24 | Tien-Hsiung Weng, Ruey-Kuen Perng, Barbara M. Chapman |
OpenMP Implementation of SPICE3 Circuit Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 35(5), pp. 493-505, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
OpenMP SPICE circuit simulator, Shared-memory programming model |
24 | Claudia Villalonga, Martin Strohbach, Niels Snoeck, Michael Sutterer, Mariano Belaunde, Ernö Kovacs, Anna V. Zhdanova, Laurent-Walter Goix, Olaf Droegehorn |
Mobile Ontology: Towards a Standardized Semantic Model for the Mobile Domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSOC Workshops ![In: Service-Oriented Computing - ICSOC 2007 Workshops, International Workshops, Vienna, Austria, September 17, 2007, Revised Selected Papers, pp. 248-257, 2007, Springer, 978-3-540-93850-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
SPICE platform, Ontology, mobile communications, Next Generation Networks, Service Delivery Platform |
24 | Yu-Shiang Lin, Dennis Sylvester |
Runtime leakage power estimation technique for combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 660-665, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
subthreshold leakage analysis, runtime leakage power estimation technique, dynamic estimation methods, static estimation methods, combinational circuits, error estimation, SPICE simulations |
24 | S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury |
Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 361-366, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates |
24 | Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ismail |
Modeling and Characterizing Power Variability in Multicore Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 146-157, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
mal-fabricated chip, VariPower, project power variability, microarchitectural block, power variability characterization, statistical analysis, multicore processor, multicore architecture, technology scaling, parameter variation, SPICE simulation |
24 | J. V. R. Ravindra, Srinivas Bala Mandalika |
Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 207-211, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
RC, distributed RLC, interconnect, SPICE, circuit, RL |
24 | Edwin M. Gray, Alberto Sampaio, Oddur Benediktsson |
An Incremental Approach to Software Process Assessment and Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Qual. J. ![In: Softw. Qual. J. 13(1), pp. 7-16, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
EFQM, improvement path, software process improvement, SPICE, software process assessment |
24 | Saurabh K. Tiwary, Rob A. Rutenbar |
Scalable trajectory methods for on-demand analog macromodel extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 403-408, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
trajectory method, analog, SPICE, circuit, macromodel |
24 | Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor |
Effects of Bit Line Coupling on the Faulty Behavior of DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 117-122, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
bit line coupling, DRAMs, Spice simulation, data backgrounds, faulty behavior |
24 | Wei-Yu Chen, Sandeep K. Gupta 0001, Melvin A. Breuer |
Test generation for crosstalk-induced faults: framework and computational result. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 305-310, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
2-vector test generation, crosstalk-induced faults, noise effects, design effort, debugging effort, pulses, signal speedup, signal slowdown, digital combinational circuits, mixed-signal test generator, XGEN, static values, dynamic signals, signal arrival times, rise times, fall times, integrated circuit testing, automatic test pattern generation, combinational circuits, accuracy, vectors, circuit analysis computing, crosstalk, transitions, integrated logic circuits, technology scaling, SPICE simulations, gate delay, circuit performance, timing information, clock frequency |
24 | Fran O'Hara |
European experiences with software process improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE ![In: Proceedings of the 22nd International Conference on on Software Engineering, ICSE 2000, Limerick Ireland, June 4-11, 2000., pp. 635-640, 2000, ACM, 1-58113-206-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
software process improvement, CMM, SPICE |
24 | Carsten Trinitis, Wolfgang Karl, Markus Leberecht |
Electrical phenomena during Hot Swap events. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), 18-20 December 2000, Los Angeles, CA, USA, pp. 19-26, 2000, IEEE Computer Society, 0-7695-0975-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
computer maintenance, Hot Swap events, maintenance purposes, CompactPCI, H-SPICE program, live insertion |
24 | Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels, Ivo Bolsens |
High-level simulation of substrate noise generation including power supply noise coupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 446-451, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SPICE |
24 | Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar |
Convex delay models for transistor sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 655-660, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SPICE |
24 | Robert L. Ewing |
Blending Symbolic Matrix and Dimensional Numerical Simulation Methodology for Mechatronics Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 270-273, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
simulation, spice, symbolic analysis, mechatronics, dimensional analysis |
24 | Dirk Stelzer, Werner Mellis, Georg Herzwurm |
A critical look at ISO 9000 for software quality management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Qual. J. ![In: Softw. Qual. J. 6(2), pp. 65-79, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
ISO 9004, quality systems, software process improvement, certification, CMM, SPICE, quality management, criticism, ISO 9001, software quality management, ISO 9000, ISO 9000-3 |
24 | Paul Grünbacher |
A software assessment process for small software enterprises. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 123-128, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
software assessment process, small software enterprises, quality software products, customer expectations, market success, mature development process, ISO 15504 standard, Software Process Improvement Capability Determination, external consultants, structured interviews, software process improvement, BOOTSTRAP, Capability Maturity Model, SPICE, software houses, self-evaluation |
24 | Kuen-Jong Lee, Jing-Jou Tang |
Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 165-171, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
efficient modeling techniques, enhanced test generation performance, fault modeling technique, inter-gate faults, threshold determination method, SPICE like accuracy, digital logic gates, logic testing, fault simulation, CMOS logic circuits, bridging faults, IDDQ testing, CMOS circuits |
24 | Steven D. Corey, Andrew T. Yang |
Automatic netlist extraction for measurement-based characterization of off-chip interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 24-29, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
MCM substrate-level interconnect circuitry, SPICE netlist, automatic netlist extraction, linear circuits, measured time domain refectometry data, measurement-based characterization, microstrip circuits, multiport system, off-chip interconnect, reflection transmission, time-domain scattering parameters, user-specified cutoff frequency, delay, crosstalk, circuit simulator, multichip modules, nonlinear circuits |
24 | Salvador Manich, Michael Nicolaidis, Joan Figueras |
Enhancing realistic fault secureness in parity prediction array arithmetic operators by IDDQ monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 124-129, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
mathematical operators, parity prediction array arithmetic operators, IDDQ current monitoring, fault diagnosis, logic testing, fault detection, stuck-at faults, bridging faults, multiplying circuits, multiplier circuit, arithmetic circuits, logic arrays, stuck-open faults, topological design, SPICE simulation, fault secureness |
24 | Jason Cong, Lei He 0001 |
Optimal wiresizing for interconnects with multiple sources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 1(4), pp. 478-511, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
bundled refinement, decomposition of multi-source routing tree, dominance property, multi-source net, multi-source routing tree, optimal wiresizing, variable segment-division, high performance, SPICE, fidelity, interconnect optimization, Elmore delay, local refinement, layout optimization |
24 | D. K. Arvind 0001, Robert D. Mullins, Vinod E. F. Rebello |
Micronets: a model for decentralising control in asynchronous processor architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 190-199, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
decentralising control, asynchronous processor architectures, micronets, communicating resources, four-phase protocol, hazard avoidance mechanisms, SPICE-level simulations, computer architecture, computer architecture, pipeline processing, processor architectures, fine-grain concurrency |
24 | Mike Chou, Jacob K. White 0001 |
Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 40-44, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Arnoldi method, SPICE-level simulation, Taylor series terms, surface-volume methods, three-dimensional interconnect, circuit analysis computing, transient analysis, integrated circuit interconnect, integrated circuit interconnections, reduced-order modeling, reduced-order models, transient simulation, series (mathematics) |
24 | Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs |
Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 360-365, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
MOS integrated circuits, bipolar integrated circuits, BiCMOS integrated circuits, layout-to-circuit extraction, high-speed MOS integrated circuits, bipolar/BiCMOS integrated circuits, device recognition, equivalent network, layout parasitics, interconnects, circuit analysis computing, circuit layout CAD, Space, Spice, device modeling |
24 | David M. Lewis |
A hardware engine for analogue mode simulation of MOS digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 345-351, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
SPICE |
24 | Tracey Y. Zhou, Dian Zhou, Hua Zhang 0019, Xinyue Niu |
Foundational-circuit-based spice simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 876-879, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Arun V. Sathanur, Ritochit Chakraborty, Vikram Jandhyala |
Accurate statistical analysis of a differential low noise amplifier using a combined SPICE-field solver approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 884-887, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Rakesh Vattikonda, Yansheng Luo, Alex Gyure, Xiaoning Qi, Sam C. Lo, Mahmoud Shahram, Yu Cao 0001, Kishore Singhal, Dino Toffolon |
A New Simulation Method for NBTI Analysis in SPICE Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 41-46, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Kiyotaka Yamamura, Wataru Kuroki |
An efficient homotopy method that can be easily implemented on SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney |
Spice-oriented iterative technique for distortion analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Rong Jiang 0002, Wenyin Fu, Charlie Chung-Ping Chen |
EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(10), pp. 1562-1571, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Anestis Dounavis |
Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1082-1085, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Takayuki Watanabe, Hideki Asai |
Modeling of power distribution networks with signal lines for SPICE simulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5774-5777, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Xiaojun Li 0001, Bing Huang, J. Qin, X. Zhang, Michael Talmor, Z. Gur, Joseph B. Bernstein |
Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 382-389, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Sun-Myung Hwang, Hye-Mee Kim |
A Study on Metrics for Supporting the Software Process Improvement Based on SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SERA ![In: Software Engineering Research, Management and Applications, Second International Conference, SERA 2004, Los Angeles, CA, USA, May 5-7, 2004, Selected Revised Papers, pp. 71-80, 2004, Springer, 3-540-32133-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Alfio Zanchi, Ioannis Papantonopoulos, Frank (Ching-Yuh) Tsay |
Measurement and SPICE prediction of sub-picosecond clock jitter in A/D converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 557-560, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Akio Ushida, Yoshihiro Yamagami, Yoshifumi Nishio, Ikkei Kinouchi, Yasuaki Inoue |
An efficient algorithm for finding multiple DC solutions based onthe SPICE-oriented Newton homotopy method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3), pp. 337-348, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Xiaofang Gao, Juin J. Liou, Joe Bernier, Gregg D. Croft, Adelmo Ortiz-Conde |
Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12), pp. 1497-1502, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Junlin Zhou, Mengzhang Cheng, Leonard Forbes |
SPICE models for flicker noise in p-MOSFETs in the saturationregion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6), pp. 763-767, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Janusz Zarebski |
A new electrothermal dynamic macromodel of the power Darlington transistor for SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 305-308, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Akio Ushida, Yoshihiro Yamagami, Ikkei Kinouchi, Yoshifumi Nishio, Yasuaki Inoue |
An efficient algorithm for finding multiple DC solutions based on Spice oriented Newton homotopy method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 447-450, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Tae-Jin Kwon, Sang-Hoon Lee, Tae-Seon Kim, Hoe-Jin Lee, Young-Kwan Park, Taek-Soo Kim, Seok-Jin Kim, Jeong-Taek Kong |
Performance Improvement for High Speed Devices Using E-tests and the SPICE Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 443-447, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Mohamed A. Imam, Mohamed A. Osman, Ashraf A. Osman |
MOSFET global modeling for deep submicron devices with a modified BSIM1 SPICE model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(4), pp. 446-451, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
24 | Kazuki Yasumatsu, Norihisa Doi |
SPiCE: A System for Translating Smalltalk Programs Into a C Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 21(11), pp. 902-912, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Application delivery, interoperability, garbage collection, translation, Smalltalk, object-oriented languages |
24 | W. W. Wong, Juin J. Liou |
JFET circuit simulation using SPICE implemented with an improved model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(1), pp. 105-109, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
24 | James A. Power, W. A. Lane |
An enhanced SPICE MOSFET model suitable for analog applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(11), pp. 1418-1425, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
24 | J. Gregory Rollins, John Choma Jr. |
Mixed-mode PISCES-SPICE coupled circuit and device solver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8), pp. 862-867, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
23 | Peng Sun, Rong Luo |
Closed-form solution for timing analysis of process variations on SWCNT interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 19-26, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
interconnect, process variation, timing analysis, carbon nanotube, closed-form |
23 | Anand Ramalingam, Giri Devarayanadurg, David Z. Pan |
Accurate power grid analysis with behavioral transistor network modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 43-50, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
RC model of transistor, behavioral modeling of switch, power grid |
23 | Anand Rajaram, David Z. Pan |
Variation tolerant buffered clock network synthesis with cross links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 157-164, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
non-tree clocks, physical design, VLSI CAD, clock network |
23 | Won-Ok Kwon, Kyoung Park |
Effective Digital IO Pin Modeling Methodology Based on IBIS Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AsiaSim ![In: Systems Modeling and Simulation: Theory and Applications, Third Asian Simulation Conference, AsiaSim 2004, Jeju Island, Korea, October 4-6, 2004, Revised Selected Papers, pp. 721-730, 2004, Springer, 3-540-24477-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Janusz Zarebski, Krzysztof Górecki |
The electrothermal model of the linear power supplies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 369-372, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Pin Su, Samel K. H. Fung, Weidong Liu 0002, Chenming Hu |
Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 487-491, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Andrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani |
Noise Model for Multiple Segmented Coupled RC Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 145-150, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Andrew B. Kahng, Sudhakar Muddu |
An analytical delay model for RLC interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(12), pp. 1507-1514, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
23 | Andrew T. Yang, Yu Liu, Jack T. Yao |
An efficient nonquasi-static diode model for circuit simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(2), pp. 231-239, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Colin C. McAndrew, Xin Li, Ivica Stevanovic, Gennady Gildenblat |
Extensions to Backward Propagation of Variance for Statistical Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 27(2), pp. 36-43, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
backward propagation of variance, PSP model, Spice modeling, statistical modeling, design and test |
16 | B. K. Mishra 0001, Sandhya Save |
Novel CAD Design Methodology for Two Stage Opamp with Noise-Power Balance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAP ![In: 2010 International Conference on Signal Acquisition and Processing, ICSAP 2010, Bangalore, India, February 9-10, 2010, pp. 287-290, 2010, IEEE Computer Society, 978-0-7695-3960-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Analog circuit designs methodologies, Analog design automation, Op-amps, AMS, Simulated Annealing, CAD, SoC, ASIC, SPICE, EDA tools |
16 | Vinayak Honkote, Baris Taskin |
Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 218-223, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Resonant clocking, Capacitive load balancing, Optimization, Low power, Spice |
16 | Luigi Buglione |
Leveraging People-Related Maturity Issues for Achieving Higher Maturity and Capability Levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSM/Mensura ![In: Software Process and Product Measurement, International Conferences IWSM 2009 and Mensura 2009, Amsterdam, The Netherlands, November 4-6, 2009. Proceedings, pp. 35-47, 2009, Springer, 978-3-642-05414-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
People-related issues, Communication, SPICE, CMMI, Maturity Models |
16 | Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O'Leary, Sandeep Tare, Warren Wong |
Guess, solder, measure, repeat: how do I get my mixed-signal chip right? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 520-521, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Verilog-AMS, analog behavioral modeling, low power verification, mixed-signal verification, VHDL, SPICE, functional verification, Verilog, performance verification |
16 | James A. Hilder, Andy M. Tyrrell |
An evolutionary platform for developing next-generation electronic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO (Companion) ![In: Genetic and Evolutionary Computation Conference, GECCO 2007, Proceedings, London, England, UK, July 7-11, 2007, Companion Material, pp. 2483-2488, 2007, ACM, 978-1-59593-698-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
analogue circuit design, genetic algorithms, genetic programming, CMOS, SPICE |
16 | Henrik Lipskoch, Karsten Albers, Frank Slomka |
Battery discharge aware energy feasibility analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 22-27, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
demand bound function, energy bound function, power consumption, spice, battery modeling, event stream |
16 | Cesar Gonzalez-Perez, Tom McBride, Brian Henderson-Sellers |
A Metamodel for Assessable Software Development Methodologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Qual. J. ![In: Softw. Qual. J. 13(2), pp. 195-214, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
capability assessment, SPICE/OOSPICE, metamodelling, software development methodologies, process assessment |
16 | Zhao Li, C.-J. Richard Shi |
SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 793-800, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
SPICE |
16 | Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy 0001 |
Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 487-490, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
SPICE |
16 | Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R. Suresh |
Transistor Flaring in Deep Submicron-Design Considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 299-304, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Deep Submicron (DSM), pullback, photolithography, Subwavelength-lithography, Optical Proximity Correction (OPC), SPICE-models, standard-ce1l library, Design for Manufacturability (DFM) |
16 | Michael S. Shur, Tor A. Fjeldly, Trond Ytterdal |
Transistor Modeling for the VDSM Era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 37-44, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
field effect transistors, parameter extraction, SPICE, device modeling |
16 | Carlo Guardiani, Sharad Saxena, Patrick McNamara, Phillip Schumaker, Dale Coder |
An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 15-18, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SPICE |
16 | Amir Attarha, Mehrdad Nourani, Caro Lucas |
Modeling and simulation of real defects using fuzzy logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 631-636, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SPICE |
16 | Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy 0001, Yibin Ye, Vivek De |
Dynamic noise analysis in precharge-evaluate circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 243, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SPICE |
16 | Andrew B. Kahng, Sudhakar Muddu, Egino Sarto |
On switch factor based analysis of coupled RC interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 79-84, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SPICE |
16 | Chandramouli V. Kashyap, Byron Krauter |
A realizable driving point model for on-chip interconnect with inductance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 190-195, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SPICE |
16 | Ad J. van de Goor, J. E. Simonse |
Defining SRAM Resistive Defects and Their Simulation Stimuli. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 33-40, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Resistive defects, simulation stimuli, SRAM functional faults, SPICE simulation |
16 | Pat Halloran |
Organisational Learning from the Perspective of a Software Process Assessment and Improvement Program. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 32nd Annual Hawaii International Conference on System Sciences (HICSS-32), January 5-8, 1999, Maui, Hawaii, USA, 1999, IEEE Computer Society, 0-7695-0001-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Software Process Assessment and Improvement, Organizational learning, SPICE, Continuous Improvement, Learning organizations |
16 | Bharath Ramasubramanian, Herman Schmit, L. Richard Carley |
Mixed-swing quadrail for low power dual-rail domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999, pp. 82-84, 1999, ACM, 1-58113-133-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
SPICE |
16 | Peter A. Beerel, Sangyun Kim 0001, Pei-Chuan Yeh, Kyeounsoo Kim |
Statistically optimized asynchronous barrel shifters for variable length codecs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999, pp. 261-263, 1999, ACM, 1-58113-133-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
SPICE |
16 | Nestoras Tzartzanis, William C. Athas |
Retractile clock-powered logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999, pp. 18-23, 1999, ACM, 1-58113-133-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
SPICE |
16 | Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari |
An architectural solution for the inductive noise problem due to clock-gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999, pp. 255-257, 1999, ACM, 1-58113-133-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
SPICE |
16 | Charles E. Molnar, Ian W. Jones, William S. Coates, Jon K. Lexau |
A FIFO Ring Performance Experiment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 279-289, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
FIFO ring performance experiment, high-speed FIFO circuit, asynchronous FIFO, clocked shift register, pulse-like protocol, two-phase clocked design, MOSIS, internal FIFO stages, 3.3 V, 1.67 to 4.8 V, 0.6 micron, pipeline, SPICE, data path, hSpice, circuit delays |
16 | Sang-Hoon Lee, Chang-hoon Choi, Jeong-Taek Kong, Wong-Seong Lee, Jei-Hwan Yoo |
An efficient statistical analysis methodology and its application to high-density DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 678-683, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
statistical SPICE modeling, High-Density DRAMs, Principal Component Analysis, Design for Manufacturing, Gradient Method |
16 | Marilyn W. Bush |
European and American Software Process Maturity Models and Assessments (Tutorial). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE ![In: Pulling Together, Proceedings of the 19th International Conference on Software Engineering, Boston, Massachusetts, USA, May 17-23, 1997., pp. 671-672, 1997, ACM, 0-89791-914-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
software process improvement models, software quality, software process improvement, bootstrap, capability maturity model (CMM), SPICE, ISO 9000 |
16 | Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska |
Design and performance of CMOS TSPC cells for high speed pseudo random testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 368-373, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists |
16 | R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili |
Energy delay analysis of partial product reduction methods for parallel multiplier implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996, Monterey, California, USA, August 12-14, 1996, pp. 201-204, 1996, IEEE, 0-7803-3571-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
SPICE |
16 | Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang |
On Designing of 4-Valued Memory with Double-Gate TFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 187-193, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit |
16 | Samy Makar, Edward J. McCluskey |
Checking experiments to test latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 196-201, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults |
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