Search results for "SPICE"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Chennian Di, Jochen A. G. Jess	An efficient CMOS bridging fault simulator: with SPICE accuracy.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
31	Michael M. Green, Alan N. Willson Jr.	An algorithm for identifying unstable operating points using SPICE.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
31	Hong June Park, Ping Keung Ko, Chenming Hu	A non-quasi-static MOSFET model for SPICE-AC analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
31	Hong June Park, Ping Keung Ko, Chenming Hu	A charge sheet capacitance model of short channel MOSFETs for SPICE.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
31	R. J. McDonald, Jerry G. Fossum	High-voltage device modeling for SPICE simulation of HVIC's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
30	Ning Lu, Judy H. McCullen	Enablement of Variation-Aware Timing: Treatment of Parasitic Resistance and Capacitance.	ISQED	2007	DBLP DOI BibTeX RDF
30	Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu	An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect.	VLSI Design	2007	DBLP DOI BibTeX RDF
30	Jun Chen 0008, Lei He 0001	Piecewise linear model for transmission line with capacitive loading and ramp input.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
30	Gregory Munson Yeric, A. F. Tasch Jr., Sanjay K. Banerjee	A universal MOSFET mobility degradation model for circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
30	Chung-Ping Wan, Bing J. Sheu, Shih-Lien Lu	Device and circuit simulation interface for an integrated VLSI design environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
24	Ning Li, Huaxiang Lu	Single-electron tunneling depressing synapse for cellular neural networks.	Neural Comput. Appl.	2008	DBLP DOI BibTeX RDF	Cellular non-linear networks (CNN), Depressing synapses, Single-electron tunneling (SET), Tunneling junction, SPICE
24	Marcus Ciolkowski, Martín Soto	Towards a Process Maturity Model for Open Source Software.	COMPSAC	2008	DBLP DOI BibTeX RDF	Process Maturity Model, Open Source Software, SPICE, CMMI, Process Assessment
24	Ning Lu	Statistical Models and Frequency-Dependent Corner Models for Passive Devices.	ISQED	2008	DBLP DOI BibTeX RDF	SPICE models, corner models, RF models, passive devices, statistical models
24	Fergal McCaffery, Minna Pikkarainen, Ita Richardson	Ahaa --agile, hybrid assessment method for automotive, safety critical smes.	ICSE	2008	DBLP DOI BibTeX RDF	assessment methods, automotive spice, software process improvement, cmmi, safety-critical, agile practices
24	Tien-Hsiung Weng, Ruey-Kuen Perng, Barbara M. Chapman	OpenMP Implementation of SPICE3 Circuit Simulator.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	OpenMP SPICE circuit simulator, Shared-memory programming model
24	Claudia Villalonga, Martin Strohbach, Niels Snoeck, Michael Sutterer, Mariano Belaunde, Ernö Kovacs, Anna V. Zhdanova, Laurent-Walter Goix, Olaf Droegehorn	Mobile Ontology: Towards a Standardized Semantic Model for the Mobile Domain.	ICSOC Workshops	2007	DBLP DOI BibTeX RDF	SPICE platform, Ontology, mobile communications, Next Generation Networks, Service Delivery Platform
24	Yu-Shiang Lin, Dennis Sylvester	Runtime leakage power estimation technique for combinational circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	subthreshold leakage analysis, runtime leakage power estimation technique, dynamic estimation methods, static estimation methods, combinational circuits, error estimation, SPICE simulations
24	S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury	Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates
24	Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ismail	Modeling and Characterizing Power Variability in Multicore Architectures.	ISPASS	2007	DBLP DOI BibTeX RDF	mal-fabricated chip, VariPower, project power variability, microarchitectural block, power variability characterization, statistical analysis, multicore processor, multicore architecture, technology scaling, parameter variation, SPICE simulation
24	J. V. R. Ravindra, Srinivas Bala Mandalika	Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach.	SBCCI	2007	DBLP DOI BibTeX RDF	RC, distributed RLC, interconnect, SPICE, circuit, RL
24	Edwin M. Gray, Alberto Sampaio, Oddur Benediktsson	An Incremental Approach to Software Process Assessment and Improvement.	Softw. Qual. J.	2005	DBLP DOI BibTeX RDF	EFQM, improvement path, software process improvement, SPICE, software process assessment
24	Saurabh K. Tiwary, Rob A. Rutenbar	Scalable trajectory methods for on-demand analog macromodel extraction.	DAC	2005	DBLP DOI BibTeX RDF	trajectory method, analog, SPICE, circuit, macromodel
24	Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor	Effects of Bit Line Coupling on the Faulty Behavior of DRAMs.	VTS	2004	DBLP DOI BibTeX RDF	bit line coupling, DRAMs, Spice simulation, data backgrounds, faulty behavior
24	Wei-Yu Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	Test generation for crosstalk-induced faults: framework and computational result.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	2-vector test generation, crosstalk-induced faults, noise effects, design effort, debugging effort, pulses, signal speedup, signal slowdown, digital combinational circuits, mixed-signal test generator, XGEN, static values, dynamic signals, signal arrival times, rise times, fall times, integrated circuit testing, automatic test pattern generation, combinational circuits, accuracy, vectors, circuit analysis computing, crosstalk, transitions, integrated logic circuits, technology scaling, SPICE simulations, gate delay, circuit performance, timing information, clock frequency
24	Fran O'Hara	European experiences with software process improvement.	ICSE	2000	DBLP DOI BibTeX RDF	software process improvement, CMM, SPICE
24	Carsten Trinitis, Wolfgang Karl, Markus Leberecht	Electrical phenomena during Hot Swap events.	PRDC	2000	DBLP DOI BibTeX RDF	computer maintenance, Hot Swap events, maintenance purposes, CompactPCI, H-SPICE program, live insertion
24	Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels, Ivo Bolsens	High-level simulation of substrate noise generation including power supply noise coupling.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
24	Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar	Convex delay models for transistor sizing.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
24	Robert L. Ewing	Blending Symbolic Matrix and Dimensional Numerical Simulation Methodology for Mechatronics Systems.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	simulation, spice, symbolic analysis, mechatronics, dimensional analysis
24	Dirk Stelzer, Werner Mellis, Georg Herzwurm	A critical look at ISO 9000 for software quality management.	Softw. Qual. J.	1997	DBLP DOI BibTeX RDF	ISO 9004, quality systems, software process improvement, certification, CMM, SPICE, quality management, criticism, ISO 9001, software quality management, ISO 9000, ISO 9000-3
24	Paul Grünbacher	A software assessment process for small software enterprises.	EUROMICRO	1997	DBLP DOI BibTeX RDF	software assessment process, small software enterprises, quality software products, customer expectations, market success, mature development process, ISO 15504 standard, Software Process Improvement Capability Determination, external consultants, structured interviews, software process improvement, BOOTSTRAP, Capability Maturity Model, SPICE, software houses, self-evaluation
24	Kuen-Jong Lee, Jing-Jou Tang	Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	efficient modeling techniques, enhanced test generation performance, fault modeling technique, inter-gate faults, threshold determination method, SPICE like accuracy, digital logic gates, logic testing, fault simulation, CMOS logic circuits, bridging faults, IDDQ testing, CMOS circuits
24	Steven D. Corey, Andrew T. Yang	Automatic netlist extraction for measurement-based characterization of off-chip interconnect.	ICCAD	1996	DBLP DOI BibTeX RDF	MCM substrate-level interconnect circuitry, SPICE netlist, automatic netlist extraction, linear circuits, measured time domain refectometry data, measurement-based characterization, microstrip circuits, multiport system, off-chip interconnect, reflection transmission, time-domain scattering parameters, user-specified cutoff frequency, delay, crosstalk, circuit simulator, multichip modules, nonlinear circuits
24	Salvador Manich, Michael Nicolaidis, Joan Figueras	Enhancing realistic fault secureness in parity prediction array arithmetic operators by IDDQ monitoring.	VTS	1996	DBLP DOI BibTeX RDF	mathematical operators, parity prediction array arithmetic operators, IDDQ current monitoring, fault diagnosis, logic testing, fault detection, stuck-at faults, bridging faults, multiplying circuits, multiplier circuit, arithmetic circuits, logic arrays, stuck-open faults, topological design, SPICE simulation, fault secureness
24	Jason Cong, Lei He 0001	Optimal wiresizing for interconnects with multiple sources.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	bundled refinement, decomposition of multi-source routing tree, dominance property, multi-source net, multi-source routing tree, optimal wiresizing, variable segment-division, high performance, SPICE, fidelity, interconnect optimization, Elmore delay, local refinement, layout optimization
24	D. K. Arvind 0001, Robert D. Mullins, Vinod E. F. Rebello	Micronets: a model for decentralising control in asynchronous processor architectures.	ASYNC	1995	DBLP DOI BibTeX RDF	decentralising control, asynchronous processor architectures, micronets, communicating resources, four-phase protocol, hazard avoidance mechanisms, SPICE-level simulations, computer architecture, computer architecture, pipeline processing, processor architectures, fine-grain concurrency
24	Mike Chou, Jacob K. White 0001	Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect.	ICCAD	1995	DBLP DOI BibTeX RDF	Arnoldi method, SPICE-level simulation, Taylor series terms, surface-volume methods, three-dimensional interconnect, circuit analysis computing, transient analysis, integrated circuit interconnect, integrated circuit interconnections, reduced-order modeling, reduced-order models, transient simulation, series (mathematics)
24	Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs	Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits.	ICCD	1995	DBLP DOI BibTeX RDF	MOS integrated circuits, bipolar integrated circuits, BiCMOS integrated circuits, layout-to-circuit extraction, high-speed MOS integrated circuits, bipolar/BiCMOS integrated circuits, device recognition, equivalent network, layout parasitics, interconnects, circuit analysis computing, circuit layout CAD, Space, Spice, device modeling
24	David M. Lewis	A hardware engine for analogue mode simulation of MOS digital circuits.	DAC	1985	DBLP DOI BibTeX RDF	SPICE
24	Tracey Y. Zhou, Dian Zhou, Hua Zhang 0019, Xinyue Niu	Foundational-circuit-based spice simulation.	ISCAS	2008	DBLP DOI BibTeX RDF
24	Arun V. Sathanur, Ritochit Chakraborty, Vikram Jandhyala	Accurate statistical analysis of a differential low noise amplifier using a combined SPICE-field solver approach.	ISCAS	2008	DBLP DOI BibTeX RDF
24	Rakesh Vattikonda, Yansheng Luo, Alex Gyure, Xiaoning Qi, Sam C. Lo, Mahmoud Shahram, Yu Cao 0001, Kishore Singhal, Dino Toffolon	A New Simulation Method for NBTI Analysis in SPICE Environment.	ISQED	2007	DBLP DOI BibTeX RDF
24	Kiyotaka Yamamura, Wataru Kuroki	An efficient homotopy method that can be easily implemented on SPICE.	ISCAS	2006	DBLP DOI BibTeX RDF
24	Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney	Spice-oriented iterative technique for distortion analysis.	ISCAS	2006	DBLP DOI BibTeX RDF
24	Rong Jiang 0002, Wenyin Fu, Charlie Chung-Ping Chen	EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
24	Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Anestis Dounavis	Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects.	ASP-DAC	2005	DBLP DOI BibTeX RDF
24	Takayuki Watanabe, Hideki Asai	Modeling of power distribution networks with signal lines for SPICE simulators.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
24	Xiaojun Li 0001, Bing Huang, J. Qin, X. Zhang, Michael Talmor, Z. Gur, Joseph B. Bernstein	Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE.	ISQED	2005	DBLP DOI BibTeX RDF
24	Sun-Myung Hwang, Hye-Mee Kim	A Study on Metrics for Supporting the Software Process Improvement Based on SPICE.	SERA	2004	DBLP DOI BibTeX RDF
24	Alfio Zanchi, Ioannis Papantonopoulos, Frank (Ching-Yuh) Tsay	Measurement and SPICE prediction of sub-picosecond clock jitter in A/D converters.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
24	Akio Ushida, Yoshihiro Yamagami, Yoshifumi Nishio, Ikkei Kinouchi, Yasuaki Inoue	An efficient algorithm for finding multiple DC solutions based onthe SPICE-oriented Newton homotopy method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
24	Xiaofang Gao, Juin J. Liou, Joe Bernier, Gregg D. Croft, Adelmo Ortiz-Conde	Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
24	Junlin Zhou, Mengzhang Cheng, Leonard Forbes	SPICE models for flicker noise in p-MOSFETs in the saturationregion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
24	Janusz Zarebski	A new electrothermal dynamic macromodel of the power Darlington transistor for SPICE.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
24	Akio Ushida, Yoshihiro Yamagami, Ikkei Kinouchi, Yoshifumi Nishio, Yasuaki Inoue	An efficient algorithm for finding multiple DC solutions based on Spice oriented Newton homotopy method.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
24	Tae-Jin Kwon, Sang-Hoon Lee, Tae-Seon Kim, Hoe-Jin Lee, Young-Kwan Park, Taek-Soo Kim, Seok-Jin Kim, Jeong-Taek Kong	Performance Improvement for High Speed Devices Using E-tests and the SPICE Model.	ISQED	2001	DBLP DOI BibTeX RDF
24	Mohamed A. Imam, Mohamed A. Osman, Ashraf A. Osman	MOSFET global modeling for deep submicron devices with a modified BSIM1 SPICE model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
24	Kazuki Yasumatsu, Norihisa Doi	SPiCE: A System for Translating Smalltalk Programs Into a C Environment.	IEEE Trans. Software Eng.	1995	DBLP DOI BibTeX RDF	Application delivery, interoperability, garbage collection, translation, Smalltalk, object-oriented languages
24	W. W. Wong, Juin J. Liou	JFET circuit simulation using SPICE implemented with an improved model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
24	James A. Power, W. A. Lane	An enhanced SPICE MOSFET model suitable for analog applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
24	J. Gregory Rollins, John Choma Jr.	Mixed-mode PISCES-SPICE coupled circuit and device solver.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
23	Peng Sun, Rong Luo	Closed-form solution for timing analysis of process variations on SWCNT interconnect.	SLIP	2009	DBLP DOI BibTeX RDF	interconnect, process variation, timing analysis, carbon nanotube, closed-form
23	Anand Ramalingam, Giri Devarayanadurg, David Z. Pan	Accurate power grid analysis with behavioral transistor network modeling.	ISPD	2007	DBLP DOI BibTeX RDF	RC model of transistor, behavioral modeling of switch, power grid
23	Anand Rajaram, David Z. Pan	Variation tolerant buffered clock network synthesis with cross links.	ISPD	2006	DBLP DOI BibTeX RDF	non-tree clocks, physical design, VLSI CAD, clock network
23	Won-Ok Kwon, Kyoung Park	Effective Digital IO Pin Modeling Methodology Based on IBIS Model.	AsiaSim	2004	DBLP DOI BibTeX RDF
23	Janusz Zarebski, Krzysztof Górecki	The electrothermal model of the linear power supplies.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
23	Pin Su, Samel K. H. Fung, Weidong Liu 0002, Chenming Hu	Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD.	ISQED	2002	DBLP DOI BibTeX RDF
23	Andrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani	Noise Model for Multiple Segmented Coupled RC Interconnects.	ISQED	2001	DBLP DOI BibTeX RDF
23	Andrew B. Kahng, Sudhakar Muddu	An analytical delay model for RLC interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
23	Andrew T. Yang, Yu Liu, Jack T. Yao	An efficient nonquasi-static diode model for circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
16	Colin C. McAndrew, Xin Li, Ivica Stevanovic, Gennady Gildenblat	Extensions to Backward Propagation of Variance for Statistical Modeling.	IEEE Des. Test Comput.	2010	DBLP DOI BibTeX RDF	backward propagation of variance, PSP model, Spice modeling, statistical modeling, design and test
16	B. K. Mishra 0001, Sandhya Save	Novel CAD Design Methodology for Two Stage Opamp with Noise-Power Balance.	ICSAP	2010	DBLP DOI BibTeX RDF	Analog circuit designs methodologies, Analog design automation, Op-amps, AMS, Simulated Annealing, CAD, SoC, ASIC, SPICE, EDA tools
16	Vinayak Honkote, Baris Taskin	Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array.	VLSI Design	2010	DBLP DOI BibTeX RDF	Resonant clocking, Capacitive load balancing, Optimization, Low power, Spice
16	Luigi Buglione	Leveraging People-Related Maturity Issues for Achieving Higher Maturity and Capability Levels.	IWSM/Mensura	2009	DBLP DOI BibTeX RDF	People-related issues, Communication, SPICE, CMMI, Maturity Models
16	Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O'Leary, Sandeep Tare, Warren Wong	Guess, solder, measure, repeat: how do I get my mixed-signal chip right?	DAC	2009	DBLP DOI BibTeX RDF	Verilog-AMS, analog behavioral modeling, low power verification, mixed-signal verification, VHDL, SPICE, functional verification, Verilog, performance verification
16	James A. Hilder, Andy M. Tyrrell	An evolutionary platform for developing next-generation electronic circuits.	GECCO (Companion)	2007	DBLP DOI BibTeX RDF	analogue circuit design, genetic algorithms, genetic programming, CMOS, SPICE
16	Henrik Lipskoch, Karsten Albers, Frank Slomka	Battery discharge aware energy feasibility analysis.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	demand bound function, energy bound function, power consumption, spice, battery modeling, event stream
16	Cesar Gonzalez-Perez, Tom McBride, Brian Henderson-Sellers	A Metamodel for Assessable Software Development Methodologies.	Softw. Qual. J.	2005	DBLP DOI BibTeX RDF	capability assessment, SPICE/OOSPICE, metamodelling, software development methodologies, process assessment
16	Zhao Li, C.-J. Richard Shi	SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects.	ICCAD	2003	DBLP DOI BibTeX RDF	SPICE
16	Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy 0001	Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation.	ICCAD	2003	DBLP DOI BibTeX RDF	SPICE
16	Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R. Suresh	Transistor Flaring in Deep Submicron-Design Considerations.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Deep Submicron (DSM), pullback, photolithography, Subwavelength-lithography, Optical Proximity Correction (OPC), SPICE-models, standard-ce1l library, Design for Manufacturability (DFM)
16	Michael S. Shur, Tor A. Fjeldly, Trond Ytterdal	Transistor Modeling for the VDSM Era.	ISQED	2000	DBLP DOI BibTeX RDF	field effect transistors, parameter extraction, SPICE, device modeling
16	Carlo Guardiani, Sharad Saxena, Patrick McNamara, Phillip Schumaker, Dale Coder	An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
16	Amir Attarha, Mehrdad Nourani, Caro Lucas	Modeling and simulation of real defects using fuzzy logic.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
16	Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy 0001, Yibin Ye, Vivek De	Dynamic noise analysis in precharge-evaluate circuits.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
16	Andrew B. Kahng, Sudhakar Muddu, Egino Sarto	On switch factor based analysis of coupled RC interconnects.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
16	Chandramouli V. Kashyap, Byron Krauter	A realizable driving point model for on-chip interconnect with inductance.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
16	Ad J. van de Goor, J. E. Simonse	Defining SRAM Resistive Defects and Their Simulation Stimuli.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Resistive defects, simulation stimuli, SRAM functional faults, SPICE simulation
16	Pat Halloran	Organisational Learning from the Perspective of a Software Process Assessment and Improvement Program.	HICSS	1999	DBLP DOI BibTeX RDF	Software Process Assessment and Improvement, Organizational learning, SPICE, Continuous Improvement, Learning organizations
16	Bharath Ramasubramanian, Herman Schmit, L. Richard Carley	Mixed-swing quadrail for low power dual-rail domino logic.	ISLPED	1999	DBLP DOI BibTeX RDF	SPICE
16	Peter A. Beerel, Sangyun Kim 0001, Pei-Chuan Yeh, Kyeounsoo Kim	Statistically optimized asynchronous barrel shifters for variable length codecs.	ISLPED	1999	DBLP DOI BibTeX RDF	SPICE
16	Nestoras Tzartzanis, William C. Athas	Retractile clock-powered logic.	ISLPED	1999	DBLP DOI BibTeX RDF	SPICE
16	Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari	An architectural solution for the inductive noise problem due to clock-gating.	ISLPED	1999	DBLP DOI BibTeX RDF	SPICE
16	Charles E. Molnar, Ian W. Jones, William S. Coates, Jon K. Lexau	A FIFO Ring Performance Experiment.	ASYNC	1997	DBLP DOI BibTeX RDF	FIFO ring performance experiment, high-speed FIFO circuit, asynchronous FIFO, clocked shift register, pulse-like protocol, two-phase clocked design, MOSIS, internal FIFO stages, 3.3 V, 1.67 to 4.8 V, 0.6 micron, pipeline, SPICE, data path, hSpice, circuit delays
16	Sang-Hoon Lee, Chang-hoon Choi, Jeong-Taek Kong, Wong-Seong Lee, Jei-Hwan Yoo	An efficient statistical analysis methodology and its application to high-density DRAMs.	ICCAD	1997	DBLP DOI BibTeX RDF	statistical SPICE modeling, High-Density DRAMs, Principal Component Analysis, Design for Manufacturing, Gradient Method
16	Marilyn W. Bush	European and American Software Process Maturity Models and Assessments (Tutorial).	ICSE	1997	DBLP DOI BibTeX RDF	software process improvement models, software quality, software process improvement, bootstrap, capability maturity model (CMM), SPICE, ISO 9000
16	Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska	Design and performance of CMOS TSPC cells for high speed pseudo random testing.	VTS	1996	DBLP DOI BibTeX RDF	CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
16	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili	Energy delay analysis of partial product reduction methods for parallel multiplier implementation.	ISLPED	1996	DBLP DOI BibTeX RDF	SPICE
16	Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang	On Designing of 4-Valued Memory with Double-Gate TFT.	ISMVL	1995	DBLP DOI BibTeX RDF	thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit
16	Samy Makar, Edward J. McCluskey	Checking experiments to test latches.	VTS	1995	DBLP DOI BibTeX RDF	exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults