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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6589 occurrences of 2604 keywords
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Results
Found 18593 publication records. Showing 18593 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
22 | Mani B. Srivastava, Anantha P. Chandrakasan, Robert W. Brodersen |
Predictive system shutdown and other architectural techniques for energy efficient programmable computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(1), pp. 42-55, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
22 | H. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask |
An SBus Monitor Board. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995, pp. 160-166, 1995, ACM, 0-89791-743-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
22 | Jianmin Li, Chung-Kuan Cheng |
Routability improvement using dynamic interconnect architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 3rd IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '95), 19-21 April 1995, Napa Valley, CA, USA, pp. 61-67, 1995, IEEE Computer Society, 0-8186-7086-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
22 | Robert P. Collins, William J. Ketelhut |
The impact of technological advances on programmable controller s(tutorial session). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 498-502, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
22 | Mingjie Lin, Yaling Ma |
Scalable architecture for programmable quantum gate array (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 290, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
reconfigurable, computing, quantum |
22 | Yee Jern Chong, Sri Parameswaran |
Flexible multi-mode embedded floating-point unit for field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 171-180, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture |
22 | Theepan Moorthy, Andy Ye |
A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 83-88, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | James W. Crouch, Hiren J. Patel, Yong C. Kim, Robert W. Bennington |
Creating unique identifiers on field programmable gate arrays using natural processing variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 579-582, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Ping Chen, Andy Ye |
The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 427-430, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig |
Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA, pp. 306-309, 2008, IEEE Computer Society, 978-0-7695-3307-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Hendrik Eeckhaut, Mark Christiaens, Dirk Stroobandt |
Improving External Memory Access for Avalon Systems on Programmable Chips.. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 311-316, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Bradley R. Quinton, Steven J. E. Wilton |
Embedded Programmable Logic Core Enhancements for System Bus Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 202-209, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Garrett S. Rose, Mircea R. Stan |
A programmable majority logic array using molecular scale electronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 225, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | David J. Lau, Orion Pritchard |
Rapid System-on-a-Programmable-Chip Development and Hardware Acceleration Of ANSI C Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-6, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Pedro C. Diniz, Gokul Govindu |
Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Julien Lamoureux, Steven J. E. Wilton |
Activity Estimation for Field-Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-8, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Reid B. Porter, Jan R. Frigo, Maya B. Gokhale, Christophe Wolinski, François Charot, Charles Wagner |
A Programmable, Maximal Throughput Architecture for Neighborhood Image Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings, pp. 279-280, 2006, IEEE Computer Society, 0-7695-2661-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle |
A Field Programmable RFID Tag and Associated Design Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings, pp. 165-174, 2006, IEEE Computer Society, 0-7695-2661-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Andy Gean Ye, Jonathan Rose |
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 3-13, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
datapath regularity, reconfigurable fabric, FPGA architecture, routing architecture, area efficiency |
22 | Arifur Rahman, Vijay Polavarapuv |
Evaluation of low-leakage design techniques for field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 23-30, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, leakage power, multiplexer |
22 | Haoyu Song 0001, Jing Lu, John W. Lockwood, James Moscola |
Secure Remote Control of Field-programmable Network Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 334-335, 2004, IEEE Computer Society, 0-7695-2230-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Pak K. Chan, Martine D. F. Schlag |
Parallel placement for field-programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 43-50, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
parallel placement, FPGAs, timing-driven placement, analytical placement |
22 | Peter Suaris, Dongsheng Wang 0012, Pei-Ning Guo, Nan-Chi Chou |
A physical retiming algorithm for field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 247, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | John W. Lockwood, Christopher E. Neely, Christopher K. Zuver, James Moscola, Sarang Dharmapurikar, David Lim |
An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 859-868, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Andrzej Krasniewski |
Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 828-838, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Aneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit |
Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 426-436, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti 0001 |
Testable Clock Routing Architecture for Field Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 1044-1047, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Deshanand P. Singh, Stephen Dean Brown |
Constrained clock shifting for field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 121-126, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Deshanand P. Singh, Stephen Dean Brown |
Integrated retiming and placement for field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 67-76, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. Vissers |
Field-Programmable Custom Computing Machines - A Taxonomy -. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 79-88, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic |
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 232-241, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Deshanand P. Singh, Stephen Dean Brown |
The case for registered routing switches in field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 161-169, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Tom Kean |
Secure Configuration of Field Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 142-151, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Stephen J. Melnikoff, Steven F. Quigley, Martin J. Russell |
Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 81-90, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Hea Joung Kim, William H. Mangione-Smith |
Factoring large numbers with programmable hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 41-48, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
configurable computing technologies, number factoring algorithms, sieving, special-purpose factoring hardware, public-key cryptosystems |
22 | Paul M. Heysters, Jaap Smit, Gerard J. M. Smit, Paul J. M. Havinga |
Mapping of DSP Algorithms on Field Programmable Function Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 400-411, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Andrej Trost, Andrej Zemva, Baldomir Zajc |
Educational Programmable Hardware Prototyping and Verification System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 818-821, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Tyler J. Moeller, David R. Martinez |
Field Programmable Gate Array Based Radar Front-End Digital Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 178-187, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Kerry Veenstra, Bruce Pedersen, Jay Schleicher, Chiakang Sung |
Optimizations for a Highly Cost-Efficient Programmable Logic Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998, pp. 20-24, 1998, ACM, 0-89791-978-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Tsutomu Maruyama, Terunobu Funatsu, Tsutomu Hoshino |
A Field-Programmable Gate-Array System for Evolutionary Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings, pp. 356-365, 1998, Springer, 3-540-64948-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Gordon J. Brebner |
Field-Programmable Logic: Catalyst for New Computing Paradigms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings, pp. 49-58, 1998, Springer, 3-540-64948-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Qiang Wang, David M. Lewis |
Automated field-programmable compute accelerator design using partial evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 16-18 April 1997, Napa Valley, CA, USA, pp. 145-154, 1997, IEEE Computer Society, 0-8186-8159-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
22 | Tong Liu 0007, Wei-Kang Huang, Fabrizio Lombardi |
Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995, pp. 125-131, 1995, ACM, 0-89791-743-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
constant testability, FPGA, testing, manufacturing |
22 | Vijayshri Maheshwari, Joel Darnauer, John Ramirez, Wayne Wei-Ming Dai |
Design of FPGAs with Area I/O for Field Programmable MCM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995, pp. 17-23, 1995, ACM, 0-89791-743-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
21 | Ziting Wang, Cunfang Zheng |
Research of Image Capturing and Processing System Based on SOPC Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCM ![In: International Conference on Networked Computing and Advanced Information Management, NCM 2009, Fifth International Joint Conference on INC, IMS and IDC: INC 2009: International Conference on Networked Computing, IMS 2009: International Conference on Advanced Information Management and Service, IDC 2009: International Conference on Digital Content, Multimedia Technology and its Applications, Seoul, Korea, August 25-27, 2009, pp. 1733-1736, 2009, IEEE Computer Society, 978-0-7695-3769-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
System on Programmable Chip, Nios II, Field Programmable Gate Arrays, Image Processing, Image Capturing |
21 | Tsutomu Sasao, Jon T. Butler |
Planar Multiple-Valued Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 28-35, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
planar multiple-valued decision diagrams, monotone increasing functions, binary functions, field programmable gate arrays, programmable logic arrays, multivalued logic circuits, threshold logic, symmetric functions, threshold functions |
21 | Shashidhar Thakur, D. F. Wong 0001 |
Simultaneous area and delay minimum K-LUT mapping for K-exact networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 402-408, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
area/delay minimum K-LUT mapping, K-exact networks, technology mapping problem, lookup table FPGAs, area minimization problem, K-bounded networks, delay minimization problem, flow-map algorithm, field programmable gate arrays, computational complexity, complexity, NP-complete, logic design, polynomial time algorithm, programmable logic arrays, table lookup, minimisation of switching nets |
21 | Aiguo Lu, Erik L. Dagless, Jonathan M. Saul |
DART: delay and routability driven technology mapping for LUT based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 409-414, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
DART, delay driven technology mapping, LUT based FPGAs, two-phased approach, routability directed delay-optimal mapping, stochastic routability analysis, delay-optimal mapping, field programmable gate arrays, delays, logic design, programmable logic arrays, table lookup, minimisation of switching nets |
21 | Yao-Wen Chang, D. F. Wong 0001, C. K. Wong |
FPGA global routing based on a new congestion metric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 372-378, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
FPGA global routing, congestion metric, routing capacity, switch block, switch-block capacity, congestion-control metric, global router, channel densities, field programmable gate arrays, congestion control, logic design, programmable logic arrays, circuit layout CAD, graph modeling |
19 | Viviane Lucy Santos de Souza, Victor Wanderley Costa de Medeiros, Manoel Eusébio de Lima |
Architecture for dense matrix multiplication on a high-performance reconfigurable system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
BRAMs (RAM blocks), MAC (multiplier unit), RASC (reconfigurable application-specific computing), performance, FPGA (field programmable gate array), parallelism, matrix multiplication, data reuse |
19 | XianPing Tao, Xiaoxing Ma, Jian Lu 0001, Ping Yu 0004, Yu Zhou |
Multi-mode interaction middleware for software services. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 51(8), pp. 985-999, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
open environment multi-mode, interaction Mobile Agent, interaction mode programming, programmable coordination media |
19 | Kevin Fan, Hyunchul Park 0001, Manjunath Kudlur, Scott A. Mahlke |
Modulo scheduling for highly customized datapaths to increase hardware reusability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Sixth International Symposium on Code Generation and Optimization (CGO 2008), April 5-9, 2008, Boston, MA, USA, pp. 124-133, 2008, ACM, 978-1-59593-978-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
programmable asic, modulo scheduling, loop accelerator |
19 | Min Xie, Youren Wang, Li Wang, Yuan Zhang |
Design on Operator-Based Reconfigurable Hardware Architecture and Cell Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings, pp. 140-150, 2007, Springer, 978-3-540-74625-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Operator-based programmable cell circuit, FPGA, Reconfigurable computing, Reconfigurable hardware, Information processing |
19 | Adrian Stoica, Didier Keymeulen, Ricardo Salem Zebulum, Mohammad M. Mojarradi, Srinivas Katkoori, Taher Daud |
Adaptive and Evolvable Analog Electronics for Space Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings, pp. 379-390, 2007, Springer, 978-3-540-74625-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Adaptive Hardware, Field Programmable Arrays |
19 | Laurent Lefèvre, Paul Roe |
Improving the flexibility of active grids through web services. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSW ![In: The proceedings of the Fourth Australasian Symposium on Grid Computing and e-Research (AusGrid 2006) and the Fourth Australasian Information Security Workshop (Network Security) (AISW 2006), Hobart, Tasmania, Australia, January 2006, pp. 3-8, 2006, Australian Computer Society, 1-920-68236-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
active and programmable networks, web services, grid computing |
19 | Thomas Gamer, Marcus Schöller, Roland Bless |
An Extensible and Flexible System for Network Anomaly Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Autonomic Networking ![In: Autonomic Networking, First International IFIP TC6 Conference, AN 2006, Paris, France, September 27-29, 2006, Proceedings, pp. 97-108, 2006, Springer, 3-540-45891-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Anomaly Detection, DDoS Attacks, Programmable Networks |
19 | Linda Dailey Paulson |
News Briefs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 38(10), pp. 22-24, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Encryption systems, Local SSL, Programmable mobile chips, Mobile processors, Mobile chips, Security, Internet, Wireless communications, Wireless communications |
19 | Yan Lin 0001, Lei He 0001 |
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 720-725, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
programmable-Vdd, time slack, FPGA, low power |
19 | Michael Brasher, Robert Haimes |
Rendering Planar Cuts Through Quadratic and Cubic Finite Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Visualization ![In: 15th IEEE Visualization Conference, IEEE Vis 2004, Austin, TX, USA, October 10-15, 2004, Proceedings, pp. 409-416, 2004, IEEE Computer Society, 0-7803-8788-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Higher Order Elements, Programmable Shaders, Cutplanes |
19 | John W. Lockwood, Christopher E. Neely, Christopher K. Zuver, David Lim |
Automated tools to implement and test Internet systems in reconfigurable hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Commun. Rev. ![In: Comput. Commun. Rev. 33(3), pp. 103-110, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
network intrusion detection and prevention, Internet, Field Programmable Gate Array (FPGA), networks, tools, firewall, reconfigurable hardware |
19 | Slavek Bulach, Anton Brauchle, Hans-Jörg Pfleiderer, Zdenek Kucerovsky |
Design and Implementation of Discrete Event Control Systems: A Petri Net Based Hardware Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discret. Event Dyn. Syst. ![In: Discret. Event Dyn. Syst. 12(3), pp. 287-309, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Petri nets, ASIC, DES, event-driven, programmable controller |
19 | Anke Speer, Marcus Schöller, Thomas Fuhrmann, Martina Zitterbart |
Aspects of AMnet Signaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NETWORKING ![In: NETWORKING 2002, Networking Technologies, Services, and Protocols; Performance of Computer and Communication Networks; and Mobile and Wireless Communications, Second International IFIP-TC6 Networking Conference, Pisa, Italy, May 19-24, 2002, Proceedings, pp. 1214-1220, 2002, Springer, 3-540-43709-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Multicasting, Signaling, Programmable Networks, Active Nodes |
19 | Danilo Tuler, Waldemar Celes Filho |
A High-Level Abstraction for Graphics Hardware Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIBGRAPI ![In: 15th Brazilian Symposium on Computer Graphics and Image Processing (SIBGRAPI 2002), 7-10 October 2002, Fortaleza-CE, Brazil, pp. 306-312, 2002, IEEE Computer Society, 0-7695-1846-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
programmable pipeline, shading language, rendering |
19 | Kurt Keutzer, Sharad Malik, A. Richard Newton |
From ASIC to ASIP: The Next Design Discontinuity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 84-90, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Programmable platforms, Design methodology, Application Specific Integrated Circuits, ASIC, Application Specific Instruction Set Processors, ASIP |
19 | John Hale, Mauricio Papa, Oliver Bremer, Rodrigo Chandia, Sujeet Shenoi |
Extending Java for Package based Access Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSAC ![In: 16th Annual Computer Security Applications Conference (ACSAC 2000), 11-15 December 2000, New Orleans, Louisiana, USA, pp. 67-76, 2000, IEEE Computer Society, 0-7695-0859-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
package based access control, programmable security, TBAC, primitive ticket, language translation preprocessor, security service library, ticket management, Java, object-oriented programming, RBAC, MAC, source code, software libraries, syntax, authorisation, program interpreters, DAC, Java language, bytecode interpretation |
19 | Enrico Denti, Andrea Omicini |
Designing Multi-agent Systems around an Extensible Communication Abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ModelAge Workshop ![In: Formal Models of Agents, ESPRIT Project ModelAge Final Workshop, Selected Papers, pp. 90-102, 1997, Springer, 3-540-67027-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Programmable Communication Abstraction, Multi-Agent Systems, Coordination Model |
19 | Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee |
Optimized software synthesis for synchronous dataflow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 250-262, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
optimized software synthesis, programmable digital signal processors, off-chip memory, real-time systems, digital signal processing, synchronous dataflow, graphical programs |
19 | Florent Bruguier, Pascal Benoit, Philippe Maurine, Lionel Torres |
A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece, pp. 20-23, 2011, IEEE Computer Society, 978-1-4577-1484-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
ElectroMagnetic Analysis (EMA), Process Characterisation, Field-Programmable Gate Arrays (FPGAs), Ring Oscillator |
19 | Rehan Ahmed, Peter Hallschmid |
Modeling and Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-Based Systems Using Stochastic Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece, pp. 70-75, 2011, IEEE Computer Society, 978-1-4577-1484-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Modeling, Field-Programmable Gate Arrays, Reconfigurable Computing, Queueing Theory, Partial Reconfiguration |
19 | Christos Kyrkou, Christos Ttofis, Theocharis Theocharides |
FPGA-Accelerated Object Detection Using Edge Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece, pp. 167-170, 2011, IEEE Computer Society, 978-1-4577-1484-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Field Programmable Gate Array, Object Detection |
19 | Andreas Loos, Michael Schmidt 0004, Dietmar Fey, Jens Grobel |
Dynamically Programmable Image Processor for Compact Vision Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: 10th IEEE International Conference on Computer and Information Technology, CIT 2010, Bradford, West Yorkshire, UK, June 29-July 1, 2010, pp. 33-40, 2010, IEEE Computer Society, 978-0-7695-4108-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Embedded image processors, dynamically programmable ASIP |
19 | Shijun Ji, Zhiwen Tian |
Research of a Programmable DC Power Supply and its Novel Protection Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVHI ![In: 2010 International Conference on Machine Vision and Human-machine Interface, MVHI 2010, Kaifeng, China, April 24-25, 2010, pp. 688-691, 2010, IEEE Computer Soceity, 978-0-7695-4009-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Programmable DC Power Supply, protection circuits, switch power supply |
19 | Jason Helge Anderson, Chirag Ravishankar |
FPGA power reduction by guarded evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 157-166, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
optimization, field-programmable gate arrays, fpgas, low-power design, power, logic synthesis, technology mapping |
19 | Marc-André Daigneault, Jean-Pierre David |
Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 283, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
time-to-digital converter, vernier method, field programmable gate array, dynamic reconfiguration |
19 | Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Hoi-Jun Yoo |
A Low-Power Multimedia SoC with Fully Programmable 3D Graphics for Mobile Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Computer Graphics and Applications ![In: IEEE Computer Graphics and Applications 29(5), pp. 82-90, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Mobile multimedia SoC, mobile unified shader, low-power design, 3D graphics, programmable |
19 | Ho Fai Ko, Nicola Nicolici |
Resource-Efficient Programmable Trigger Units for Post-Silicon Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 14th IEEE European Test Symposium, ETS 2009, Sevilla, Spain, May 25-29, 2009, pp. 17-22, 2009, IEEE Computer Society, 978-0-7695-3703-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
programmable trigger unit, false trigger analysis, post-silicon validation |
19 | Henrique Cota de Freitas, Philippe Olivier Alexandre Navaux |
On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 129-132, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
adaptable topologies, programmable NoC routers, networks-on-chip, reconfigurable computing, crossbar switch |
19 | Raphael Rubin, André DeHon |
Choose-your-own-adventure routing: lightweight load-time defect avoidance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 23-32, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
bitstream load, in-field repair, defect tolerance, alternatives, programmable interconnect |
19 | Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet |
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 43-52, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing |
19 | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj |
3D configuration caching for 2D FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 286, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
field programmable gate array (fpga), reconfigurable computing, 3d integration, configuration caching |
19 | James Kelly, Wladimir Araujo, Kallol Banerjee |
Rapid service creation using the JUNOS SDK. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRESTO ![In: Proceedings of the ACM SIGCOMM 2009 Workshop on Programmable Routers for Extensible Services of Tomorrow, PRESTO 2009, Barcelona, Spain, August 21, 2009, pp. 7-12, 2009, ACM, 978-1-60558-446-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
JUNOS, internet protocol, network operating system, network services, rapid application development, programmable routers |
19 | Stephen Longfield Jr., Mark L. Chang |
A Parameterized Stereo Vision Core for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: FCCM 2009, 17th IEEE Symposium on Field Programmable Custom Computing Machines, Napa, California, USA, 5-7 April 2009, Proceedings, pp. 263-266, 2009, IEEE Computer Society, 978-0-7695-3716-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Field programmable gate arrays, Reconfigurable computing, Stereo vision |
19 | Suhaib A. Fahmy, Jorg Lotze, Juanjo Noguera, Linda Doyle, Robert Esser |
Generic Software Framework for Adaptive Applications on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: FCCM 2009, 17th IEEE Symposium on Field Programmable Custom Computing Machines, Napa, California, USA, 5-7 April 2009, Proceedings, pp. 55-62, 2009, IEEE Computer Society, 978-0-7695-3716-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
field-programmable gate arrays, adaptive systems, dynamic reconfiguration, software defined radio |
19 | Weiming Wang, Ligang Dong, Bin Zhuge |
Analysis and Implementation of an Open Programmable Router Based on Forwarding and Control Element Separation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 23(5), pp. 769-779, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
open programmable, network element, architecture, protocol, computer network, router, ForCES |
19 | Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal |
Architecture-specific packing for virtex-5 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 5-13, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
optimization, performance, FPGAs, field-programmable gate arrays, power, placement, packing |
19 | Yizheng Zhou, Vijay Lakamraju, Israel Koren, C. M. Krishna 0001 |
Software-Based Failure Detection and Recovery in Programmable Network Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 18(11), pp. 1539-1550, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Programmable Network Interface Card (NIC), Single Event Upset (SEU), radiation induced faults, failure detection, self-testing |
19 | Scott C. Smith |
Design of a logic element for implementing an asynchronous FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 13-22, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
NULL convention logic (NCL), asynchronous logic design, field programmable gate array (FPGA), reconfigurable logic, delay-insensitive circuits |
19 | Yoo-Joo Choi, Young J. Kim, Myoung-Hee Kim |
Rapid pairwise intersection tests using programmable GPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Vis. Comput. ![In: Vis. Comput. 22(2), pp. 80-89, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Programmable shaders, Deformable body simulation, Geometric modeling, Collision detection, Computer animation |
19 | Ian Kuon, Aaron Egier, Jonathan Rose |
Design, layout and verification of an FPGA using automated tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 215-226, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FPGA, programmable logic, PLD, automatic layout |
19 | Song Peng, David Fang, John Teifel, Rajit Manohar |
Automated synthesis for asynchronous FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 163-173, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
asychronous circuits, programmable logic, automated synthesis |
19 | Adrian Stoica, Ricardo Salem Zebulum, Didier Keymeulen, Michael I. Ferguson, Vu Duong, Xin Guo 0002 |
Evolvable hardware techniques for on-chip automated reconfiguration of programmable devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Soft Comput. ![In: Soft Comput. 8(5), pp. 354-365, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Reconfigurable chips, Programmable devices, Genetic algorithms, Evolvable hardware, Automated design |
19 | Martin Koster, Jörg Haber, Hans-Peter Seidel |
Real-Time Rendering of Human Hair Using Programmable Graphics Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer Graphics International ![In: 2004 Computer Graphics International (CGI 2004), 16-19 June 2004, Crete, Greece, pp. 248-256, 2004, IEEE Computer Society, 0-7695-2171-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
opacity maps, programmable graphics hardware, shadow maps, hair rendering, anisotropic reflection |
19 | Katherine Compton, Scott Hauck |
Flexibility measurement of domain-specific reconfigurable hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 155-161, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
programmable hardware, flexibility, reconfigurable hardware |
19 | Jason Helge Anderson, Farid N. Najm, Tim Tuan |
Active leakage power optimization for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 33-41, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
optimization, FPGAs, field-programmable gate arrays, low-power design, power, leakage |
19 | John Teifel, Rajit Manohar |
Highly pipelined asynchronous FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 133-142, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
concurrency, pipelining, asynchronous circuits, programmable logic, correctness by construction |
19 | Kaoru Sugita, Takeshi Naemura, Hiroshi Harashima |
Performance evaluation of programmable graphics hardware for image filtering and stereo matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VRST ![In: Proceedings of the ACM Symposium on Virtual Reality Software and Technology, VRST 2003, Osaka, Japan, October 1-3, 2003, pp. 176-183, 2003, ACM, 1-58113-569-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
stereo matching, programmable graphics hardware, image filtering, real-time image processing |
19 | Timothy J. Purcell, Craig Donner, Mike Cammarano, Henrik Wann Jensen, Pat Hanrahan |
Photon mapping on programmable graphics hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Graphics Hardware ![In: Proceedings of the 2003 ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware, San Diego, California, USA, July 26-27, 2003, pp. 41-50, 2003, Eurographics Association, 1-58113-739-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
global illumination, programmable graphics hardware, photon mapping |
19 | Michael G. Wrighton, André DeHon |
Hardware-assisted simulated annealing with application for fast FPGA placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 33-42, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
field-programmable gate arrays, simulated annealing, placement, reconfigurable computing, design automation |
19 | Wai-Kei Mak |
I/O placement for FPGAs with multiple I/O standards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 51-57, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
I/O placement, I/O standards, field-programmable gate array, placement |
19 | Pedro C. Diniz, Joonseok Park |
Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 8-11 April 2003, Napa, CA, USA, Proceedings, pp. 207-217, 2003, IEEE Computer Society, 0-7695-1979-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Custom Computing, Data search and Data Reorganization Engines, Hardware support for Pointer Operations, Field-Programmable- Gate-Arrays (FPGAs) |
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