Search results for "programmable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Mani B. Srivastava, Anantha P. Chandrakasan, Robert W. Brodersen	Predictive system shutdown and other architectural techniques for energy efficient programmable computation.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
22	H. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask	An SBus Monitor Board.	FPGA	1995	DBLP DOI BibTeX RDF
22	Jianmin Li, Chung-Kuan Cheng	Routability improvement using dynamic interconnect architecture.	FCCM	1995	DBLP DOI BibTeX RDF
22	Robert P. Collins, William J. Ketelhut	The impact of technological advances on programmable controller s(tutorial session).	DAC	1985	DBLP DOI BibTeX RDF
22	Mingjie Lin, Yaling Ma	Scalable architecture for programmable quantum gate array (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	reconfigurable, computing, quantum
22	Yee Jern Chong, Sri Parameswaran	Flexible multi-mode embedded floating-point unit for field programmable gate arrays.	FPGA	2009	DBLP DOI BibTeX RDF	dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture
22	Theepan Moorthy, Andy Ye	A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays.	FPL	2008	DBLP DOI BibTeX RDF
22	James W. Crouch, Hiren J. Patel, Yong C. Kim, Robert W. Bennington	Creating unique identifiers on field programmable gate arrays using natural processing variations.	FPL	2008	DBLP DOI BibTeX RDF
22	Ping Chen, Andy Ye	The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays.	FPL	2008	DBLP DOI BibTeX RDF
22	Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig	Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures.	FCCM	2008	DBLP DOI BibTeX RDF
22	Hendrik Eeckhaut, Mark Christiaens, Dirk Stroobandt	Improving External Memory Access for Avalon Systems on Programmable Chips..	FPL	2007	DBLP DOI BibTeX RDF
22	Bradley R. Quinton, Steven J. E. Wilton	Embedded Programmable Logic Core Enhancements for System Bus Interfaces.	FPL	2007	DBLP DOI BibTeX RDF
22	Garrett S. Rose, Mircea R. Stan	A programmable majority logic array using molecular scale electronics.	FPGA	2006	DBLP DOI BibTeX RDF
22	David J. Lau, Orion Pritchard	Rapid System-on-a-Programmable-Chip Development and Hardware Acceleration Of ANSI C Functions.	FPL	2006	DBLP DOI BibTeX RDF
22	Pedro C. Diniz, Gokul Govindu	Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit.	FPL	2006	DBLP DOI BibTeX RDF
22	Julien Lamoureux, Steven J. E. Wilton	Activity Estimation for Field-Programmable Gate Arrays.	FPL	2006	DBLP DOI BibTeX RDF
22	Reid B. Porter, Jan R. Frigo, Maya B. Gokhale, Christophe Wolinski, François Charot, Charles Wagner	A Programmable, Maximal Throughput Architecture for Neighborhood Image Processing.	FCCM	2006	DBLP DOI BibTeX RDF
22	Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle	A Field Programmable RFID Tag and Associated Design Flow.	FCCM	2006	DBLP DOI BibTeX RDF
22	Andy Gean Ye, Jonathan Rose	Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits.	FPGA	2005	DBLP DOI BibTeX RDF	datapath regularity, reconfigurable fabric, FPGA architecture, routing architecture, area efficiency
22	Arifur Rahman, Vijay Polavarapuv	Evaluation of low-leakage design techniques for field programmable gate arrays.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, leakage power, multiplexer
22	Haoyu Song 0001, Jing Lu, John W. Lockwood, James Moscola	Secure Remote Control of Field-programmable Network Devices.	FCCM	2004	DBLP DOI BibTeX RDF
22	Pak K. Chan, Martine D. F. Schlag	Parallel placement for field-programmable gate arrays.	FPGA	2003	DBLP DOI BibTeX RDF	parallel placement, FPGAs, timing-driven placement, analytical placement
22	Peter Suaris, Dongsheng Wang 0012, Pei-Ning Guo, Nan-Chi Chou	A physical retiming algorithm for field programmable gate arrays.	FPGA	2003	DBLP DOI BibTeX RDF
22	John W. Lockwood, Christopher E. Neely, Christopher K. Zuver, James Moscola, Sarang Dharmapurikar, David Lim	An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall.	FPL	2003	DBLP DOI BibTeX RDF
22	Andrzej Krasniewski	Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices.	FPL	2003	DBLP DOI BibTeX RDF
22	Aneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit	Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics.	FPL	2003	DBLP DOI BibTeX RDF
22	L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti 0001	Testable Clock Routing Architecture for Field Programmable Gate Arrays.	FPL	2003	DBLP DOI BibTeX RDF
22	Deshanand P. Singh, Stephen Dean Brown	Constrained clock shifting for field programmable gate arrays.	FPGA	2002	DBLP DOI BibTeX RDF
22	Deshanand P. Singh, Stephen Dean Brown	Integrated retiming and placement for field programmable gate arrays.	FPGA	2002	DBLP DOI BibTeX RDF
22	Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. Vissers	Field-Programmable Custom Computing Machines - A Taxonomy -.	FPL	2002	DBLP DOI BibTeX RDF
22	Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic	Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices.	FPL	2002	DBLP DOI BibTeX RDF
22	Deshanand P. Singh, Stephen Dean Brown	The case for registered routing switches in field programmable gate arrays.	FPGA	2001	DBLP DOI BibTeX RDF
22	Tom Kean	Secure Configuration of Field Programmable Gate Arrays.	FPL	2001	DBLP DOI BibTeX RDF
22	Stephen J. Melnikoff, Steven F. Quigley, Martin J. Russell	Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic.	FPL	2001	DBLP DOI BibTeX RDF
22	Hea Joung Kim, William H. Mangione-Smith	Factoring large numbers with programmable hardware.	FPGA	2000	DBLP DOI BibTeX RDF	configurable computing technologies, number factoring algorithms, sieving, special-purpose factoring hardware, public-key cryptosystems
22	Paul M. Heysters, Jaap Smit, Gerard J. M. Smit, Paul J. M. Havinga	Mapping of DSP Algorithms on Field Programmable Function Arrays.	FPL	2000	DBLP DOI BibTeX RDF
22	Andrej Trost, Andrej Zemva, Baldomir Zajc	Educational Programmable Hardware Prototyping and Verification System.	FPL	2000	DBLP DOI BibTeX RDF
22	Tyler J. Moeller, David R. Martinez	Field Programmable Gate Array Based Radar Front-End Digital Signal Processing.	FCCM	1999	DBLP DOI BibTeX RDF
22	Kerry Veenstra, Bruce Pedersen, Jay Schleicher, Chiakang Sung	Optimizations for a Highly Cost-Efficient Programmable Logic Architecture.	FPGA	1998	DBLP DOI BibTeX RDF
22	Tsutomu Maruyama, Terunobu Funatsu, Tsutomu Hoshino	A Field-Programmable Gate-Array System for Evolutionary Computation.	FPL	1998	DBLP DOI BibTeX RDF
22	Gordon J. Brebner	Field-Programmable Logic: Catalyst for New Computing Paradigms.	FPL	1998	DBLP DOI BibTeX RDF
22	Qiang Wang, David M. Lewis	Automated field-programmable compute accelerator design using partial evaluation.	FCCM	1997	DBLP DOI BibTeX RDF
22	Tong Liu 0007, Wei-Kang Huang, Fabrizio Lombardi	Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays.	FPGA	1995	DBLP DOI BibTeX RDF	constant testability, FPGA, testing, manufacturing
22	Vijayshri Maheshwari, Joel Darnauer, John Ramirez, Wayne Wei-Ming Dai	Design of FPGAs with Area I/O for Field Programmable MCM.	FPGA	1995	DBLP DOI BibTeX RDF
21	Ziting Wang, Cunfang Zheng	Research of Image Capturing and Processing System Based on SOPC Technology.	NCM	2009	DBLP DOI BibTeX RDF	System on Programmable Chip, Nios II, Field Programmable Gate Arrays, Image Processing, Image Capturing
21	Tsutomu Sasao, Jon T. Butler	Planar Multiple-Valued Decision Diagrams.	ISMVL	1995	DBLP DOI BibTeX RDF	planar multiple-valued decision diagrams, monotone increasing functions, binary functions, field programmable gate arrays, programmable logic arrays, multivalued logic circuits, threshold logic, symmetric functions, threshold functions
21	Shashidhar Thakur, D. F. Wong 0001	Simultaneous area and delay minimum K-LUT mapping for K-exact networks.	ICCD	1995	DBLP DOI BibTeX RDF	area/delay minimum K-LUT mapping, K-exact networks, technology mapping problem, lookup table FPGAs, area minimization problem, K-bounded networks, delay minimization problem, flow-map algorithm, field programmable gate arrays, computational complexity, complexity, NP-complete, logic design, polynomial time algorithm, programmable logic arrays, table lookup, minimisation of switching nets
21	Aiguo Lu, Erik L. Dagless, Jonathan M. Saul	DART: delay and routability driven technology mapping for LUT based FPGAs.	ICCD	1995	DBLP DOI BibTeX RDF	DART, delay driven technology mapping, LUT based FPGAs, two-phased approach, routability directed delay-optimal mapping, stochastic routability analysis, delay-optimal mapping, field programmable gate arrays, delays, logic design, programmable logic arrays, table lookup, minimisation of switching nets
21	Yao-Wen Chang, D. F. Wong 0001, C. K. Wong	FPGA global routing based on a new congestion metric.	ICCD	1995	DBLP DOI BibTeX RDF	FPGA global routing, congestion metric, routing capacity, switch block, switch-block capacity, congestion-control metric, global router, channel densities, field programmable gate arrays, congestion control, logic design, programmable logic arrays, circuit layout CAD, graph modeling
19	Viviane Lucy Santos de Souza, Victor Wanderley Costa de Medeiros, Manoel Eusébio de Lima	Architecture for dense matrix multiplication on a high-performance reconfigurable system.	SBCCI	2009	DBLP DOI BibTeX RDF	BRAMs (RAM blocks), MAC (multiplier unit), RASC (reconfigurable application-specific computing), performance, FPGA (field programmable gate array), parallelism, matrix multiplication, data reuse
19	XianPing Tao, Xiaoxing Ma, Jian Lu 0001, Ping Yu 0004, Yu Zhou	Multi-mode interaction middleware for software services.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	open environment multi-mode, interaction Mobile Agent, interaction mode programming, programmable coordination media
19	Kevin Fan, Hyunchul Park 0001, Manjunath Kudlur, Scott A. Mahlke	Modulo scheduling for highly customized datapaths to increase hardware reusability.	CGO	2008	DBLP DOI BibTeX RDF	programmable asic, modulo scheduling, loop accelerator
19	Min Xie, Youren Wang, Li Wang, Yuan Zhang	Design on Operator-Based Reconfigurable Hardware Architecture and Cell Circuit.	ICES	2007	DBLP DOI BibTeX RDF	Operator-based programmable cell circuit, FPGA, Reconfigurable computing, Reconfigurable hardware, Information processing
19	Adrian Stoica, Didier Keymeulen, Ricardo Salem Zebulum, Mohammad M. Mojarradi, Srinivas Katkoori, Taher Daud	Adaptive and Evolvable Analog Electronics for Space Applications.	ICES	2007	DBLP DOI BibTeX RDF	Adaptive Hardware, Field Programmable Arrays
19	Laurent Lefèvre, Paul Roe	Improving the flexibility of active grids through web services.	ACSW	2006	DBLP BibTeX RDF	active and programmable networks, web services, grid computing
19	Thomas Gamer, Marcus Schöller, Roland Bless	An Extensible and Flexible System for Network Anomaly Detection.	Autonomic Networking	2006	DBLP DOI BibTeX RDF	Anomaly Detection, DDoS Attacks, Programmable Networks
19	Linda Dailey Paulson	News Briefs.	Computer	2005	DBLP DOI BibTeX RDF	Encryption systems, Local SSL, Programmable mobile chips, Mobile processors, Mobile chips, Security, Internet, Wireless communications, Wireless communications
19	Yan Lin 0001, Lei He 0001	Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction.	DAC	2005	DBLP DOI BibTeX RDF	programmable-Vdd, time slack, FPGA, low power
19	Michael Brasher, Robert Haimes	Rendering Planar Cuts Through Quadratic and Cubic Finite Elements.	IEEE Visualization	2004	DBLP DOI BibTeX RDF	Higher Order Elements, Programmable Shaders, Cutplanes
19	John W. Lockwood, Christopher E. Neely, Christopher K. Zuver, David Lim	Automated tools to implement and test Internet systems in reconfigurable hardware.	Comput. Commun. Rev.	2003	DBLP DOI BibTeX RDF	network intrusion detection and prevention, Internet, Field Programmable Gate Array (FPGA), networks, tools, firewall, reconfigurable hardware
19	Slavek Bulach, Anton Brauchle, Hans-Jörg Pfleiderer, Zdenek Kucerovsky	Design and Implementation of Discrete Event Control Systems: A Petri Net Based Hardware Approach.	Discret. Event Dyn. Syst.	2002	DBLP DOI BibTeX RDF	Petri nets, ASIC, DES, event-driven, programmable controller
19	Anke Speer, Marcus Schöller, Thomas Fuhrmann, Martina Zitterbart	Aspects of AMnet Signaling.	NETWORKING	2002	DBLP DOI BibTeX RDF	Multicasting, Signaling, Programmable Networks, Active Nodes
19	Danilo Tuler, Waldemar Celes Filho	A High-Level Abstraction for Graphics Hardware Programming.	SIBGRAPI	2002	DBLP DOI BibTeX RDF	programmable pipeline, shading language, rendering
19	Kurt Keutzer, Sharad Malik, A. Richard Newton	From ASIC to ASIP: The Next Design Discontinuity.	ICCD	2002	DBLP DOI BibTeX RDF	Programmable platforms, Design methodology, Application Specific Integrated Circuits, ASIC, Application Specific Instruction Set Processors, ASIP
19	John Hale, Mauricio Papa, Oliver Bremer, Rodrigo Chandia, Sujeet Shenoi	Extending Java for Package based Access Control.	ACSAC	2000	DBLP DOI BibTeX RDF	package based access control, programmable security, TBAC, primitive ticket, language translation preprocessor, security service library, ticket management, Java, object-oriented programming, RBAC, MAC, source code, software libraries, syntax, authorisation, program interpreters, DAC, Java language, bytecode interpretation
19	Enrico Denti, Andrea Omicini	Designing Multi-agent Systems around an Extensible Communication Abstraction.	ModelAge Workshop	1997	DBLP DOI BibTeX RDF	Programmable Communication Abstraction, Multi-Agent Systems, Coordination Model
19	Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee	Optimized software synthesis for synchronous dataflow.	ASAP	1997	DBLP DOI BibTeX RDF	optimized software synthesis, programmable digital signal processors, off-chip memory, real-time systems, digital signal processing, synchronous dataflow, graphical programs
19	Florent Bruguier, Pascal Benoit, Philippe Maurine, Lionel Torres	A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis.	FPL	2011	DBLP DOI BibTeX RDF	ElectroMagnetic Analysis (EMA), Process Characterisation, Field-Programmable Gate Arrays (FPGAs), Ring Oscillator
19	Rehan Ahmed, Peter Hallschmid	Modeling and Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-Based Systems Using Stochastic Networks.	FPL	2011	DBLP DOI BibTeX RDF	Modeling, Field-Programmable Gate Arrays, Reconfigurable Computing, Queueing Theory, Partial Reconfiguration
19	Christos Kyrkou, Christos Ttofis, Theocharis Theocharides	FPGA-Accelerated Object Detection Using Edge Information.	FPL	2011	DBLP DOI BibTeX RDF	Field Programmable Gate Array, Object Detection
19	Andreas Loos, Michael Schmidt 0004, Dietmar Fey, Jens Grobel	Dynamically Programmable Image Processor for Compact Vision Systems.	CIT	2010	DBLP DOI BibTeX RDF	Embedded image processors, dynamically programmable ASIP
19	Shijun Ji, Zhiwen Tian	Research of a Programmable DC Power Supply and its Novel Protection Circuit.	MVHI	2010	DBLP DOI BibTeX RDF	Programmable DC Power Supply, protection circuits, switch power supply
19	Jason Helge Anderson, Chirag Ravishankar	FPGA power reduction by guarded evaluation.	FPGA	2010	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, logic synthesis, technology mapping
19	Marc-André Daigneault, Jean-Pierre David	Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	time-to-digital converter, vernier method, field programmable gate array, dynamic reconfiguration
19	Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Hoi-Jun Yoo	A Low-Power Multimedia SoC with Fully Programmable 3D Graphics for Mobile Devices.	IEEE Computer Graphics and Applications	2009	DBLP DOI BibTeX RDF	Mobile multimedia SoC, mobile unified shader, low-power design, 3D graphics, programmable
19	Ho Fai Ko, Nicola Nicolici	Resource-Efficient Programmable Trigger Units for Post-Silicon Validation.	ETS	2009	DBLP DOI BibTeX RDF	programmable trigger unit, false trigger analysis, post-silicon validation
19	Henrique Cota de Freitas, Philippe Olivier Alexandre Navaux	On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	adaptable topologies, programmable NoC routers, networks-on-chip, reconfigurable computing, crossbar switch
19	Raphael Rubin, André DeHon	Choose-your-own-adventure routing: lightweight load-time defect avoidance.	FPGA	2009	DBLP DOI BibTeX RDF	bitstream load, in-field repair, defect tolerance, alternatives, programmable interconnect
19	Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet	Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing
19	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj	3D configuration caching for 2D FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	field programmable gate array (fpga), reconfigurable computing, 3d integration, configuration caching
19	James Kelly, Wladimir Araujo, Kallol Banerjee	Rapid service creation using the JUNOS SDK.	PRESTO	2009	DBLP DOI BibTeX RDF	JUNOS, internet protocol, network operating system, network services, rapid application development, programmable routers
19	Stephen Longfield Jr., Mark L. Chang	A Parameterized Stereo Vision Core for FPGAs.	FCCM	2009	DBLP DOI BibTeX RDF	Field programmable gate arrays, Reconfigurable computing, Stereo vision
19	Suhaib A. Fahmy, Jorg Lotze, Juanjo Noguera, Linda Doyle, Robert Esser	Generic Software Framework for Adaptive Applications on FPGAs.	FCCM	2009	DBLP DOI BibTeX RDF	field-programmable gate arrays, adaptive systems, dynamic reconfiguration, software defined radio
19	Weiming Wang, Ligang Dong, Bin Zhuge	Analysis and Implementation of an Open Programmable Router Based on Forwarding and Control Element Separation.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	open programmable, network element, architecture, protocol, computer network, router, ForCES
19	Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal	Architecture-specific packing for virtex-5 FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	optimization, performance, FPGAs, field-programmable gate arrays, power, placement, packing
19	Yizheng Zhou, Vijay Lakamraju, Israel Koren, C. M. Krishna 0001	Software-Based Failure Detection and Recovery in Programmable Network Interfaces.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	Programmable Network Interface Card (NIC), Single Event Upset (SEU), radiation induced faults, failure detection, self-testing
19	Scott C. Smith	Design of a logic element for implementing an asynchronous FPGA.	FPGA	2007	DBLP DOI BibTeX RDF	NULL convention logic (NCL), asynchronous logic design, field programmable gate array (FPGA), reconfigurable logic, delay-insensitive circuits
19	Yoo-Joo Choi, Young J. Kim, Myoung-Hee Kim	Rapid pairwise intersection tests using programmable GPUs.	Vis. Comput.	2006	DBLP DOI BibTeX RDF	Programmable shaders, Deformable body simulation, Geometric modeling, Collision detection, Computer animation
19	Ian Kuon, Aaron Egier, Jonathan Rose	Design, layout and verification of an FPGA using automated tools.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, programmable logic, PLD, automatic layout
19	Song Peng, David Fang, John Teifel, Rajit Manohar	Automated synthesis for asynchronous FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	asychronous circuits, programmable logic, automated synthesis
19	Adrian Stoica, Ricardo Salem Zebulum, Didier Keymeulen, Michael I. Ferguson, Vu Duong, Xin Guo 0002	Evolvable hardware techniques for on-chip automated reconfiguration of programmable devices.	Soft Comput.	2004	DBLP DOI BibTeX RDF	Reconfigurable chips, Programmable devices, Genetic algorithms, Evolvable hardware, Automated design
19	Martin Koster, Jörg Haber, Hans-Peter Seidel	Real-Time Rendering of Human Hair Using Programmable Graphics Hardware.	Computer Graphics International	2004	DBLP DOI BibTeX RDF	opacity maps, programmable graphics hardware, shadow maps, hair rendering, anisotropic reflection
19	Katherine Compton, Scott Hauck	Flexibility measurement of domain-specific reconfigurable hardware.	FPGA	2004	DBLP DOI BibTeX RDF	programmable hardware, flexibility, reconfigurable hardware
19	Jason Helge Anderson, Farid N. Najm, Tim Tuan	Active leakage power optimization for FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF	optimization, FPGAs, field-programmable gate arrays, low-power design, power, leakage
19	John Teifel, Rajit Manohar	Highly pipelined asynchronous FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF	concurrency, pipelining, asynchronous circuits, programmable logic, correctness by construction
19	Kaoru Sugita, Takeshi Naemura, Hiroshi Harashima	Performance evaluation of programmable graphics hardware for image filtering and stereo matching.	VRST	2003	DBLP DOI BibTeX RDF	stereo matching, programmable graphics hardware, image filtering, real-time image processing
19	Timothy J. Purcell, Craig Donner, Mike Cammarano, Henrik Wann Jensen, Pat Hanrahan	Photon mapping on programmable graphics hardware.	Graphics Hardware	2003	DBLP DOI BibTeX RDF	global illumination, programmable graphics hardware, photon mapping
19	Michael G. Wrighton, André DeHon	Hardware-assisted simulated annealing with application for fast FPGA placement.	FPGA	2003	DBLP DOI BibTeX RDF	field-programmable gate arrays, simulated annealing, placement, reconfigurable computing, design automation
19	Wai-Kei Mak	I/O placement for FPGAs with multiple I/O standards.	FPGA	2003	DBLP DOI BibTeX RDF	I/O placement, I/O standards, field-programmable gate array, placement
19	Pedro C. Diniz, Joonseok Park	Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures.	FCCM	2003	DBLP DOI BibTeX RDF	Custom Computing, Data search and Data Reorganization Engines, Hardware support for Pointer Operations, Field-Programmable- Gate-Arrays (FPGAs)