Search results for "Testability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Lionel C. Briand, Yvan Labiche	A UML-Based Approach to System Testing.	Softw. Syst. Model.	2002	DBLP DOI BibTeX RDF	Testing of object-oriented systems, UML, Testability, Sequence Diagrams, System testing, Use Cases
18	Maisaa Khalil, Chantal Robach, Franc Novak	Diagnosis Strategies for Hardware or Software Systems.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	diagnostic strategies, diagnostic tools, system level diagnostics, testability, fault location
18	Frank te Beest, Kees van Berkel 0001, Ad M. G. Peeters	Adding Synchronous and LSSD Modes to Asynchronous Circuits.	ASYNC	2002	DBLP DOI BibTeX RDF	design for testability, asynchronous circuits, scan test, LSSD
18	Sasha Novakovsky, Shy Shyman, Ziyad Hanna	High capacity and automatic functional extraction tool for industrial VLSI circuit designs.	ICCAD	2002	DBLP DOI BibTeX RDF	Formal Equivalence Verification (FEV), Hardware Description Languages (HDL), Switch Level Analysis, functional abstraction, satisfiability procedures, synthesis, Design For Testability (DFT), logic simulation, Binary Decision Diagrams (BDDs)
18	Muhammad Nummer, Manoj Sachdev	A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency.	VTS	2001	DBLP DOI BibTeX RDF	high-performance testing, controlled-delay flip-flop, built-in self test, Delay-fault testing, design for delay testability
18	Mang Li, Axel Rennoch, Ina Schieferdecker, Dorota Witaszek, O. Halabi, Alain Vouffo, Aihong Yin	Experience Report on Conformance Tests for CORBA ORBs.	APAQS	2001	DBLP DOI BibTeX RDF	Static and dynamic analysis, CORBA, Conformance testing, Testability, Testing tools
18	Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi	An Approach for Detecting Multiple Faulty FPGA Logic Blocks.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	fault tolerance, FPGA, multiple faults, C-testability, PLD
18	Hideo Fujiwara	A New Class of Sequential Circuits with Combinational Test Generation Complexity.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	complexity, test generation, design for testability, sequential circuits, reducibility, partial scan, Balanced structure
18	Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara	A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	non-scan design for testability, complete fault efficiency, controllers, at-speed test
18	Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri	CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder.	ASYNC	2000	DBLP DOI BibTeX RDF	pulse logic, switch-level fault simulation, Cellular Automata, BIST, asynchronous circuits, testability, stuck-at faults, domino logic, self-timed circuits, dynamic circuits
18	José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski	Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate
18	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante	A genetic algorithm-based system for generating test programs for microprocessor IP cores.	ICTAI	2000	DBLP DOI BibTeX RDF	industrial property, genetic algorithm based system, test program generation, microprocessor IP cores, digital systems design trend, design-and-reuse paradigm, intellectual property cores, encrypted gate-level netlist, testability problems, automatic approach, processor cores, fault coverage figures, random approach, genetic algorithms, genetic algorithms, microprocessor chips, automatic test software, test program, electronic engineering computing
18	Albrecht P. Stroele	Synthesis for Arithmetic Built-In Self-Tes.	VTS	2000	DBLP DOI BibTeX RDF	test configuration, built-in self-test, high-level synthesis, synthesis for testability, Accumulator
18	Octávio Páscoa Dias, Isabel C. Teixeira, João Paulo Teixeira 0001	Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems Architectures.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	hardware/software, system testability, architecture, metrics, quality assessment
18	Ilker Hamzaoglu, Janak H. Patel	Reducing Test Application Time for Full Scan Embedded Cores.	FTCS	1999	DBLP DOI BibTeX RDF	test generation, design-for-testability, fault simulation, embedded cores, full scan
18	Shiyi Xu, Tukwasibwe Justaf Frank	An Evaluation of Test Generation Algorithms for combinational Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Genetic Algorithm, Test Generation, Forecasting, Testability
18	Li Shen 0002	Genetic Algorithm Based Test Generation for Sequential Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	sequential depth analysis, dynamic testability measure, genetic algorithm, test generation, Sequential testing
18	Rohit Sharma, C. P. Ravikumar	Design Issues in Synthesis of Reusable Cores.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	Deign Reuse, CORDIC Arithmetic and Core Testability, Embedded Cores
18	Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe	Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique.	DATE	1998	DBLP DOI BibTeX RDF	Scan chain selection, RT and gate levels, Partial scan, Synthesis for testability
18	Xiaoming Yu, Yinghua Min	Design of delay-verifiable combinational logic by adding extra inputs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	delay-verifiable combinational logic, delay testability, synthesis, combinational circuits, hardware overhead, temporal behavior
18	Michinobu Nakao, Kazumi Hatayama, Isao Higashi	Accelerated Test Points Selection Method for Scan-Based BIST.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Test points, Optimization, BIST, Testability
18	Cheng-Wen Wu	On energy efficiency of VLSI testing.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test efficiency models, CMOS power consumption model, high testability, high power dissipation, high-power testing, transition activity factor, fabricated chip, testing energy, VLSI, energy efficiency, fault coverage, design optimization, VLSI testing, testing time, test efficiency, testing power
18	Hiroshi Yokoyama, Xiaoqing Wen, Hideo Tamamoto	Random Pattern Testable Design with Partial Circuit Duplication.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Partial circuit duplication, Random testing Built-in self test, Design for testability
18	Christos A. Papachristou, Mikhail Baklashov	A test synthesis technique using redundant register transfers.	ICCAD	1997	DBLP DOI BibTeX RDF	behavioral variables, conditional statements, redundant register transfers, structural signals, test synthesis technique, testability metrics, graph theory, logic testing, controllability, high level synthesis, VHDL, observability, fault coverage, data path, hardware overhead, behavioral descriptions
18	Rolf Drechsler, Martin Keim, Bernd Becker 0001	Fault Simulation in Sequential Multi-Valued Logic Networks.	ISMVL	1997	DBLP DOI BibTeX RDF	sequential multi-valued logic networks, multi-valued logic networks, logic testing, sequential circuits, fault models, fault simulator, random pattern testability
18	Vladimír Székely, Márta Rencz, Bernard Courtois	Integrating on-chip temperature sensors into DfT schemes and BIST architectures.	VTS	1997	DBLP DOI BibTeX RDF	on-chip low-power small-area CMOS temperature sensor, DfTT, design for thermal testability, safety-critical circuit, integrated circuit testing, BIST, CMOS integrated circuits
18	Eduardo J. Peralías, Adoración Rueda, José L. Huertas	A DFT Technique for Analog-to-Digital Converters with digital correction.	VTS	1997	DBLP DOI BibTeX RDF	Design for Testability of Data Converters, Analog and Mixed Signal Test
18	Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta 0001	Fault macromodeling and a testing strategy for opamps.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	catastrophic fault model, operational amplifier design for testability, analog test, macromodeling, parametric faults
18	Cheng-Ping Wang, Chin-Long Wey	Test Generation Of Analog Switched-Current Circuits.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	switched current circuits, analog switched-current circuits, current switches, voltage switches, noncatastrophic faults, transistor switches, full testability, current copiers, stray inductance, CMOS switch, BIST design, fault model, circuit simulation, macromodel, switched-capacitor circuits, test sequence generation, catastrophic faults
18	Wang-Dauh Tseng, Kuochen Wang	Testable Design and Testing of MCMs Based on Multifrequency Scan.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	boundary scan architecture, multifrequency test, smart substrate, technology mixed, design for testability, VHDL, multichip module
18	Ghassan Al Hayek, Yves Le Traon, Chantal Robach	Considering Test Economics in the Process of Hardware/Software Partitioning.	EUROMICRO	1996	DBLP DOI BibTeX RDF	hardware/software testing, specifications, logic testing, estimate, testability, co-design, mutation-test, hardware/software partitioning, test economics
18	Robert B. Norwood, Edward J. McCluskey	Synthesis-for-scan and scan chain ordering.	VTS	1996	DBLP DOI BibTeX RDF	synthesis-for-scan procedure, scan chain ordering, testable circuit design, beneficial scan, VLSI, logic testing, integrated circuit testing, design for testability, logic design, sequential circuits, logic synthesis, flip-flops, integrated circuit design, integrated logic circuits, test strategy, boundary scan testing, functional specifications
18	Michel Renovell, Florence Azaïs, Yves Bertrand	The multi-configuration: A DFT technique for analog circuits.	VTS	1996	DBLP DOI BibTeX RDF	multi-configuration technique, diagnosis facilities, 8/sup th/ order band pass filter, integrated circuit testing, design for testability, integrated circuit design, analog circuits, analogue integrated circuits, band-pass filters, DFT technique
18	Debesh Kumar Das, Bhargab B. Bhattacharya	Does retiming affect redundancy in sequential circuits?	VLSI Design	1996	DBLP DOI BibTeX RDF	combinational redundancy, sequential redundancy, fault diagnosis, logic testing, timing, redundancy, test generation, design for testability, sequential circuits, sequential circuit, fault, retiming, logic optimization, operation speed
18	Claudio Costi, Micaela Serra, Donatella Sciuto	A new DFT methodology for sequential circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	design for testability, ATPG, fault coverage, scan design, test application time
18	Rajesh Gupta 0003, Melvin A. Breuer	Partial scan design of register-transfer level circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	serial scan design, I-paths, design for testability, register-transfer level designs, balanced structures, partial scan design
18	Rolf Drechsler, Rolf Krieger, Bernd Becker 0001	Random Pattern Fault Simulation in Multi-Valued Circuits.	ISMVL	1995	DBLP DOI BibTeX RDF	random pattern fault simulation, multi-valued circuits, multi-valued logic networks, fault diagnosis, logic testing, integrated circuit testing, fault simulator, circuit analysis computing, multivalued logic circuits, random pattern testability
18	Junya Kudoh, Toshiro Takahashi, Yukio Umada, Masaharu Kimura, Shigeru Yamamoto, Youichi Ito	A CMOS gate array with dynamic-termination GTL I/O circuits.	ICCD	1995	DBLP DOI BibTeX RDF	CMOS gate array, dynamic-termination GTL I/O circuits, triple-metal-layer process technology, push-pull output driver, dynamic termination receiver, 250 Mb/s data, stub line, terminated bus line, IDDQ testability, differential receiver, delay time overheads, 0.5 micron, 250 Mbit/s, logic testing, delays, CMOS logic circuits, logic arrays
18	Ted Stanion, Carl Sechen	Quasi-algebraic decompositions of switching functions.	ARVLSI	1995	DBLP DOI BibTeX RDF	quasi-algebraic decompositions, algebraic product, binary Boolean operation, canonical manner, SSL testable, logic testing, testability, switching functions, switching functions, state assignment, minimisation of switching nets, benchmark circuits, circuit size
18	Nilanjan Mukherjee 0001, H. Kassab, Janusz Rajski, Jerzy Tyszer	Arithmetic built-in self test for high-level synthesis.	VTS	1995	DBLP DOI BibTeX RDF	arithmetic built-in self test, data path architectures, arithmetic blocks, compact test responses, testable circuit synthesis, logic testing, built-in self test, high level synthesis, high-level synthesis, integrated circuit testing, logic CAD, testability, abstract level, test vectors, state coverage
18	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	multi-output logic module, cellular automata array, design turn-around time, field programmability, rapid circuit realization, logic blocks, AND-XOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture
18	Enrico Macii, Angelo Raffaele Meo	A test generation program for sequential circuits.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Automatic test pattern generation for sequential circuits, interactive fault simulation, pruning heuristics, circuit partitioning, testability measures
18	Bruce F. Cockburn	Tutorial on semiconductor memory testing.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Design for testability, fault models, functional test, memory testing, memory design
18	Vishwani D. Agrawal	A tale of two designs: the cheapest and the most economic.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Benefit-cost trade-off, economics of design for testability, engineering economics, cost analysis
18	Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal	Finite state machine synthesis with fault tolerant test function.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	Design for combinational test generation, finite state machine synthesis, test function embedding, synthesis for testability, fault-tolerant design
18	Bernhard Eschermann	State Assignment for Hardwired VLSI Control Units.	ACM Comput. Surv.	1993	DBLP DOI BibTeX RDF	coding constraints, VLSI, computer-aided design, synthesis, finite-state machines, logic design, sequential circuits, testability, integrated circuits, built-in tests, state assignment, control design
18	Vishwani D. Agrawal, Kwang-Ting Cheng	Finite state machine synthesis with embedded test function.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	VLSI, Computer-Aided Design, Test Generation, Logic Synthesis, Synthesis for Testability
15	Xiaojun Ma, Jing Huang 0001, Cecilia Metra, Fabrizio Lombardi	Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates.	J. Electron. Test.	2009	DBLP DOI BibTeX RDF	Array testing, Nanotechnology, Emerging technology, Reversible computing, QCA
15	Syed M. Alam, Robert E. Jones, Scott Pozder, Ankur Jain	Die/wafer stacking with reciprocal design symmetry (RDS) for mask reuse in three-dimensional (3D) integration technology.	ISQED	2009	DBLP DOI BibTeX RDF
15	Clemente Izurieta, James M. Bieman	Testing Consequences of Grime Buildup in Object Oriented Design Patterns.	ICST	2008	DBLP DOI BibTeX RDF	Software grime, decay, anti-patterns, testing, object oriented, design patterns
15	Hazem El-Gendy, Nabil El-Kadhi, Narayan C. Debnath	Towards sound development of PIXITP, conformance test suites, and conforming implementations for various Formal Description Techniques.	ISCC	2008	DBLP DOI BibTeX RDF
15	Mukesh Agrawal, Sandip Karmakar, Dhiman Saha, Debdeep Mukhopadhyay	Scan Based Side Channel Attacks on Stream Ciphers and Their Counter-Measures.	INDOCRYPT	2008	DBLP DOI BibTeX RDF
15	Antonio Zenteno Ramírez, Guillermo Espinosa, Víctor H. Champac	Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
15	Jia Di, Parag K. Lala	Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Reed-Muller expression, nanoscale circuit, layout, stuck-at fault, cellular arrays, delay-insensitive circuit
15	Teemu Kanstrén	Towards Trace Based Model Synthesis for Program Understanding and Test Automation.	ICSEA	2007	DBLP DOI BibTeX RDF
15	Tali Kaufman, Madhu Sudan 0001	Sparse Random Linear Codes are Locally Decodable and Testable.	FOCS	2007	DBLP DOI BibTeX RDF
15	Himanshu Thapliyal, A. Prasad Vinod 0001	Designing Efficient Online Testable Reversible Adders With New Reversible Gate.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Francesco Regazzoni 0001, Thomas Eisenbarth 0001, Johann Großschädl, Luca Breveglieri, Paolo Ienne, Israel Koren, Christof Paar	Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits.	DFT	2007	DBLP DOI BibTeX RDF
15	Irith Pomeranz, Sudhakar M. Reddy	Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs.	VTS	2007	DBLP DOI BibTeX RDF
15	Peter Wohl, John A. Waicukauski, Sanjay Patel	Automated Design and Insertion of Optimal One-Hot Bus Encoders.	VTS	2007	DBLP DOI BibTeX RDF
15	Matthias M. Müller	The Effect of Test-Driven Development on Program Code.	XP	2006	DBLP DOI BibTeX RDF
15	David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre	Secure Scan Techniques: A Comparison.	IOLTS	2006	DBLP DOI BibTeX RDF
15	Christian Borgs, Jennifer T. Chayes, László Lovász 0001, Vera T. Sós, Balázs Szegedy, Katalin Vesztergombi	Graph limits and parameter testing.	STOC	2006	DBLP DOI BibTeX RDF	convergence of graphs, distance of graphs, graph limit, property testing, graph homomorphism
15	Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura	Current Testable Design of Resistor String DACs.	DELTA	2006	DBLP DOI BibTeX RDF
15	Shyue-Kung Lu, Ting-Yu Chen, Wei-Yuan Liu	Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits.	PRDC	2006	DBLP DOI BibTeX RDF
15	Irith Pomeranz, Sudhakar M. Reddy	Autoscan: a scan design without external scan inputs or outputs.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
15	Josef Strnadel, Zdenek Kotásek	Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies.	DSD	2005	DBLP DOI BibTeX RDF
15	Paul Valiant	The Tensor Product of Two Codes Is Not Necessarily Robustly Testable.	APPROX-RANDOM	2005	DBLP DOI BibTeX RDF
15	Deepali Koppad, Alexandre V. Bystrov, Alexandre Yakovlev	Off-Line Testing of Asynchronous Circuits.	VLSI Design	2005	DBLP DOI BibTeX RDF
15	José Luis Huertas	Test and design-for-test of mixed-signal integrated circuits.	SBCCI	2004	DBLP DOI BibTeX RDF
15	David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell	Scan Design and Secure Chip.	IOLTS	2004	DBLP DOI BibTeX RDF
15	Sita Ramakrishnan	VISWAS and on Diagnosability with IEEE Std P1522 and UML2.0 Testing Profile.	FATES	2003	DBLP DOI BibTeX RDF
15	Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira 0001	RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	fault modeling, DFT, TPG, RTL
15	Mohammad A. Naal, M. Rakotoar, Emmanuel Simeu, Chouki Aktouf	Using Concurrent and Semi-Concurrent On-Line Testing During HLS: An Adaptable Approach.	IOLTW	2002	DBLP DOI BibTeX RDF
15	Kamalnayan Jayaraman, Vivekananda M. Vedula, Jacob A. Abraham	Native Mode Functional Self-Test Generation for Systems-on-Chip.	ISQED	2002	DBLP DOI BibTeX RDF	functional self-test, native-mode, signature compression, system-on-chip, at-speed
15	Daniela De Venuto, Michael J. Ohletz	On-Chip Test for Mixed-Signal ASICs using Two-Mode Comparators with Bias-Programmable Reference Voltages.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	mixed-signal ASIC, hardware conversion, GO/NOGO test, bias programming, DfT, power consumption, overhead
15	Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou	An efficient design-for-verification technique for HDLs.	ASP-DAC	2001	DBLP DOI BibTeX RDF
15	Dong Xiang, Yi Xu	A Multiple Phase Partial Scan Design Method.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
15	David W. Flater, K. C. Morris 0001	Harmonized Conformance Testing for Product Data Managers.	COMPSAC	2001	DBLP DOI BibTeX RDF	middleware, testing, databases, standards, harmonization, PDM
15	Michael Affenzeller, Franz Pichler, Rudolf Mittelmann	On CAST.FSM Computation of Hierarchical Multi-layer Networks of Automata.	EUROCAST	2001	DBLP DOI BibTeX RDF
15	Richard M. Chou, Kewal K. Saluja	Testable Sequential Circuit Design: A Partition and Resynthesis Approach.	VTS	2001	DBLP DOI BibTeX RDF
15	Sameer Sharma, Michael S. Hsiao	Combination of Structural and State Analysis for Partial Scan.	VLSI Design	2001	DBLP DOI BibTeX RDF
15	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Sequential fault modeling, test pattern generation, robust testing, iterative logic arrays
15	Irith Pomeranz, Sudhakar M. Reddy	On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	irredundant faults, built-in test generation, test generation, synchronous sequential circuits, Initial states
15	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik	A BIST scheme for RTL circuits based on symbolic testabilityanalysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
15	Tong Liu 0007, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi	Testing and testable designs for one-time programmable FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
15	Marcello Dalpasso, Alessandro Bogliolo, Luca Benini, Michele Favalli	Virtual Fault Simulation of Distributed IP-Based Designs.	DATE	2000	DBLP DOI BibTeX RDF
15	A. Bommireddy, Jitendra Khare, Saghir A. Shaikh, S.-T. Su	Test and Debug of Networking SoCs: A Case Study.	VTS	2000	DBLP DOI BibTeX RDF
15	Raghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab	Hierarchical Test Generation for Systems On a Chip.	VLSI Design	2000	DBLP DOI BibTeX RDF
15	Ben Mathew, Daniel G. Saab	Combining multiple DFT schemes with test generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
15	Kenneth M. Butler	Estimating the Economic Benefits of DFT.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF
15	Thomas W. Williams	Testing in Nanometer Technologies.	DATE	1999	DBLP DOI BibTeX RDF
15	Noga Alon, Michael Krivelevich, Ilan Newman, Mario Szegedy	Regular Languages Are Testable with a Constant Number of Queries.	FOCS	1999	DBLP DOI BibTeX RDF	testing, randomized algorithms, regular languages
15	Meghanad D. Wagh, Chien-In Henry Chen	High-level design synthesis with redundancy removal for high speed testable adders.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
15	Majid Sarrafzadeh, Toshihiko Takahashi	A fast algorithm for routability testing.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
15	Xiaowei Li 0001, Paul Y. S. Cheung	Exploiting Test Resource Optimization in Data Path Synthesis for BIST.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
15	Jingjing Xu, Rahul Kundu, F. Joel Ferguson	A Systematic DFT Procedure for Library Cells.	VTS	1999	DBLP DOI BibTeX RDF
15	Wei-Kang Huang, Fred J. Meyer, Xiao-Tao Chen, Fabrizio Lombardi	Testing configurable LUT-based FPGA's.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
15	Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik	Efficient test-point selection for scan-based BIST.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
15	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	cell fault model (CFM), fault simulation, test pattern generation, stuck-at fault model