Search results for "ISCAS85"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
60	Wangqi Qiu, D. M. H. Walker	Testing the Path Delay Faults of ISCAS85 Circuit c6288.	MTV	2003	DBLP DOI BibTeX RDF
47	Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng	Incremental logic rectification.	VTS	1997	DBLP DOI BibTeX RDF	incremental logic rectification, incorrect combinational circuit, symbolic BDD techniques, sequence of partial corrections, circuits with multiple errors, general single-gate correction, structural correspondence, ISCAS85 benchmark circuits, error region pruning, specification, implementation, logic CAD, VLSI design, hybrid approach
47	Yu Fang, Alexander Albicki	Efficient testability enhancement for combinational circuit.	ICCD	1995	DBLP DOI BibTeX RDF	testability enhancement, combinational circuit testing, XOR Chain Structure, insertion points, random pattern resistant node source tracking, ISCAS85, performance evaluation, VLSI, VLSI, logic testing, controllability, built-in self test, combinational circuits, automatic testing, automatic testing, observability, testability analysis, benchmark circuits, hardware overhead, performance penalty
14	Sumanth Amarchinta, Dhireesha Kudithipudi	Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	charge-boosters, subthreshold design, biasing
14	Sheng Wei 0001, Saro Meguerdichian, Miodrag Potkonjak	Gate-level characterization: foundations and hardware security applications.	DAC	2010	DBLP DOI BibTeX RDF	gate-level characterization, hardware Trojan horse, thermal conditioning, manufacturing variability
14	Pratik J. Shah, Jiang Hu	Impact of lithography-friendly circuit layout.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	cd variation, lithography, wirelength, routing congestion
14	Fan Wang, Vishwani D. Agrawal	Soft Error Rates with Inertial and Logical Masking.	VLSI Design	2009	DBLP DOI BibTeX RDF
14	Koustav Bhattacharya, Nagarajan Ranganathan	RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits.	VLSI Design	2009	DBLP DOI BibTeX RDF
14	Munkang Choi, Linda S. Milor	Diagnosis of Optical Lithography Faults With Product Test Sets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
14	Roberto Gómez 0001, Alejandro Girón, Víctor H. Champac	A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Interconnection opens, Boolean testing, Favorable logic conditions, Test generation methodology, Coupling capacitances
14	David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller	Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits.	DATE	2008	DBLP DOI BibTeX RDF
14	Hao Xu 0010, Wen-Ben Jone, Ranga Vemuri	Accurate energy breakeven time estimation for run-time power gating.	ICCAD	2008	DBLP DOI BibTeX RDF
14	Koustav Bhattacharya, Nagarajan Ranganathan	A linear programming formulation for security-aware gate sizing.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	dynamic power variance, linear programming., path balancing, differential power analysis, gate sizing
14	Yi Wang, Xuan Zeng 0001, Jun Tao 0001, Hengliang Zhu, Xu Luo, Changhao Yan, Wei Cai 0003	Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model.	ISQED	2008	DBLP DOI BibTeX RDF	adaptive stochastic collocation method, max, process variations, statistical static timing analysis
14	Zhanyuan Jiang, Weiping Shi	Circuit-wise buffer insertion and gate sizing algorithm with scalability.	DAC	2008	DBLP DOI BibTeX RDF	buffer insertion, gate sizing, interconnect synthesis
14	Animesh Datta, Ashish Goel, R. T. Cakici, Hamid Mahmoodi, Dheepa Lekshmanan, Kaushik Roy 0001	Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
14	Fatih Kocan, Daniel G. Saab	Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Dynamic fault diagnosis, FPGA, Emulation, Stuck-at faults, Circuits, Gate-level
14	Suchismita Roy, P. P. Chakrabarti 0001, Pallab Dasgupta	Event propagation for accurate circuit delay calculation using SAT.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Critical delay, event propagation, SAT
14	Charles Thangaraj, Tom Chen 0001	Power andPerformance Analysis for Early Design Space Exploration.	ISVLSI	2007	DBLP DOI BibTeX RDF	Power-performance tradeoff, What-if analysis
14	Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir	Maximum circuit activity estimation using pseudo-boolean satisfiability.	DATE	2007	DBLP DOI BibTeX RDF
14	Sanjay Pant, David T. Blaauw	Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks.	ASP-DAC	2007	DBLP DOI BibTeX RDF
14	Kyung Ki Kim, Yong-Bin Kim	Optimal Body Biasing for Minimum Leakage Power in Standby Mode.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Hong Luo, Yu Wang 0002, Ku He, Rong Luo, Huazhong Yang, Yuan Xie 0001	Modeling of PMOS NBTI Effect Considering Temperature Variation.	ISQED	2007	DBLP DOI BibTeX RDF
14	Kalyana R. Kantipudi, Vishwani D. Agrawal	A Reduced Complexity Algorithm for Minimizing N-Detect Tests.	VLSI Design	2007	DBLP DOI BibTeX RDF
14	Tao Li, Zhiping Yu	Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage.	DAC	2007	DBLP DOI BibTeX RDF
14	Munkang Choi, Linda S. Milor	Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
14	Kaviraj Chopra, Sarma B. K. Vrudhula	Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
14	Hai Lin, Yu Wang 0002, Rong Luo, Huazhong Yang, Hui Wang 0004	IR-drop Reduction Through Combinational Circuit Partitioning.	PATMOS	2006	DBLP DOI BibTeX RDF	Static Timing Analysis, IR-drop, circuit partitioning
14	Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff	Soft delay error analysis in logic circuits.	DATE	2006	DBLP DOI BibTeX RDF
14	Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy 0001	Speed binning aware design methodology to improve profit under parameter variations.	ASP-DAC	2006	DBLP DOI BibTeX RDF
14	Vishnu C. Vimjam, Michael S. Hsiao	Efficient Fault Collapsing via Generalized Dominance Relations.	VTS	2006	DBLP DOI BibTeX RDF
14	Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky	Gain-based technology mapping for minimum runtime leakage under input vector uncertainty.	DAC	2006	DBLP DOI BibTeX RDF	leakage, technology mapping, logical effort
14	Mandar Waghmode, Zhuo Li 0001, Weiping Shi	Buffer insertion in large circuits with constructive solution search techniques.	DAC	2006	DBLP DOI BibTeX RDF	physical design, buffer insertion, cost optimization, interconnect synthesis
14	Fatih Kocan, Mehmet Hadi Gunes	On the ZBDD-based nonenumerative path delay fault coverage calculation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
14	Yaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark	Statistical Critical Path Analysis Considering Correlations.	PATMOS	2005	DBLP DOI BibTeX RDF
14	Lei Wu 0009, D. M. H. Walker	A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits.	DFT	2005	DBLP DOI BibTeX RDF
14	Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi	Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment.	DFT	2005	DBLP DOI BibTeX RDF
14	Fatih Kocan, Mehmet Hadi Gunes	Acyclic circuit partitioning for path delay fault emulation.	AICCSA	2005	DBLP DOI BibTeX RDF
14	Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne	Performance Metric Based Optimization Protocol.	PATMOS	2004	DBLP DOI BibTeX RDF
14	Arijit Mondal, P. P. Chakrabarti 0001, Chittaranjan A. Mandal	A New Approach to Timing Analysis Using Event Propagation and Temporal Logic.	DATE	2004	DBLP DOI BibTeX RDF
14	Abilio Parreira, João Paulo Teixeira 0001, Marcelino B. Santos	FPGAs BIST Evaluation.	FPL	2004	DBLP DOI BibTeX RDF
14	Srivathsan Krishnamohan, Nihar R. Mahapatra	A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits.	ICCD	2004	DBLP DOI BibTeX RDF
14	Hamidreza Hashempour, Fabrizio Lombardi	Evaluation of heuristic techniques for test vector ordering.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	test vector ordering, compression, SoC, power consumption, ATE, test data
14	Xiang Lu, Zhuo Li 0001, Wangqi Qiu, D. M. H. Walker, Weiping Shi	PARADE: PARAmetric Delay Evaluation under Process Variation.	ISQED	2004	DBLP DOI BibTeX RDF
14	Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj	Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic.	VLSI Design	2004	DBLP DOI BibTeX RDF
14	Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu 0001, S.-M. S. Kang	Coupling delay optimization by temporal decorrelation using dual threshold voltage technique.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
14	Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas	Exact path delay fault coverage with fundamental ZBDD operations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
14	Poul Frederick Williams, Henrik Reif Andersen, Henrik Hulgaard	Satisfiability checking using Boolean Expression Diagrams.	Int. J. Softw. Tools Technol. Transf.	2003	DBLP DOI BibTeX RDF
14	Shi-Yu Huang	A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	diagnosis, symbolic simulation, Byzantine fault
14	Ronald D. Blanton, John P. Hayes	On the properties of the input pattern fault model.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	fault testing, testing digital circuits, ATPG, fault models, faults, defects
14	Yongjun Xu, Zuying Luo, Zhiguo Chen, Xiaowei Li 0001	Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	stack effect, leakage current simulation, propagation of signal probability, macromodeling
14	Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi	The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
14	Zhuo Li 0001, Xiang Lu, Weiping Shi	Process variation dimension reduction based on SVD.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
14	Wangqi Qiu, Xiang Lu, Zhuo Li 0001, D. M. H. Walker, Weiping Shi	CodSim -- A Combined Delay Fault Simulator.	DFT	2003	DBLP DOI BibTeX RDF
14	Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja	Exclusive Test and its Applications to Fault Diagnosis.	VLSI Design	2003	DBLP DOI BibTeX RDF
14	Santanu Chattopadhyay, Naveen Choudhary	Genetic Algorithm based Approach for Low Power Combinational Circuit Testing.	VLSI Design	2003	DBLP DOI BibTeX RDF
14	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Noise constrained transistor sizing and power optimization for dual Vst domino logic.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
14	Seongmoon Wang, Sandeep K. Gupta 0001	DS-LFSR: a BIST TPG for low switching activity.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
14	Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi	Fast and exact transistor sizing based on iterative relaxation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
14	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain.	DATE	2002	DBLP DOI BibTeX RDF
14	Zuying Luo, Xiaowei Li 0001, Huawei Li 0001, Shiyuan Yang, Yinghua Min	Test Power Optimization Techniques for CMOS Circuits.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
14	Shi-Yu Huang	Diagnosis Of Byzantine Open-Segment Faults.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
14	Santanu Chattopadhyay	Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automata.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	cellular automata, Test pattern generators, pseudoexhaustive testing
14	Mahesh Ketkar, Sachin S. Sapatnekar	Standby power optimization via transistor sizing and dual threshold voltage assignment.	ICCAD	2002	DBLP DOI BibTeX RDF
14	Geun Rae Cho, Tom Chen 0001	Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications.	ISQED	2002	DBLP DOI BibTeX RDF	Mixed PTL/Static, Lower-Power Technology Mapping, Logic Synthesis, Pass Transistor Logic
14	Kumar N. Dwarakanath, R. D. (Shawn) Blanton	Exploiting Dominance and Equivalence using Fault Tuples.	VTS	2002	DBLP DOI BibTeX RDF
14	Shi-Yu Huang	Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation.	VTS	2002	DBLP DOI BibTeX RDF
14	Yi-Jong Yeh, Sy-Yen Kuo, Jing-Yang Jou	Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
14	Sudhakar Bobba, Ibrahim N. Hajj	Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
14	Yi-Jong Yeh, Sy-Yen Kuo	An optimization-based low-power voltage scaling technique using multiple supply voltages.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
14	Aiman El-Maleh, Esam Khan, Saif al Zahir	A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip.	VTS	2001	DBLP DOI BibTeX RDF
14	M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana	Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction.	VTS	2001	DBLP DOI BibTeX RDF
14	Shi-Yu Huang	On Improving the Accuracy Of Multiple Defect Diagnosis.	VTS	2001	DBLP DOI BibTeX RDF
14	Ilker Hamzaoglu, Janak H. Patel	Test set compaction algorithms for combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
14	Kabir Gulrajani, Michael S. Hsiao	Multi-Node Static Logic Implications for Redundancy Identification.	DATE	2000	DBLP DOI BibTeX RDF
14	Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh	Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits.	ICCD	2000	DBLP DOI BibTeX RDF
14	Byungwoo Choi, D. M. H. Walker	Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation.	VTS	2000	DBLP DOI BibTeX RDF	interconnect coupling, delay fault model, process variation, timing analysis, delay fault test
14	Ilker Hamzaoglu, Janak H. Patel	Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators.	VTS	2000	DBLP DOI BibTeX RDF	Built-in-Self-Test, Test Generation, Combinational Circuits, Test Application Time, Stuck-at Fault Model
14	Chul Young Lee, D. M. H. Walker	PROBE: A PPSFP Simulator for Resistive Bridging Faults.	VTS	2000	DBLP DOI BibTeX RDF	PPSFP, fault model, fault simulation, bridging fault, resistive bridging faults
14	Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi	MINFLOTRANSIT: min-cost flow based transistor sizing tool.	DAC	2000	DBLP DOI BibTeX RDF
14	Amir Attarha, Mehrdad Nourani, Caro Lucas	Modeling and simulation of real defects using fuzzy logic.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
14	Haluk Konuk	Voltage- and current-based fault simulation for interconnect open defects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
14	Frank Poehl, Walter Anheier	Quality Determination for Gate Delay Fault Tests Considering Three-State Elements.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	ATPG, fault modelling, fault simulation
14	Ilker Hamzaoglu, Janak H. Patel	New Techniques for Deterministic Test Pattern Generation.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	redundancy, stuck-at fault, Boolean satisfiability, automatic test generation, scan design, logic implications
14	Seiichiro Tani, Mitsuo Teramoto, Tomoo Fukazawa, Kazuyoshi Matsuhiro	Efficient Path Selection for Delay Testing Based on Path Clustering.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	clustering, delay testing, delay fault, path delay
14	Dirk W. Hoffmann, Thomas Kropf	Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction.	CHARME	1999	DBLP DOI BibTeX RDF	Automatic error correction, design error diagnosis, formal methods, equivalence checking
14	Vijay Sundararajan, Keshab K. Parhi	Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution.	ARVLSI	1999	DBLP DOI BibTeX RDF	Gate-resizing, Buffer-redistribution, near-optimal, library-specific, optimal, low-power
14	M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana	Implication and Evaluation Techniques for Proving Fault Equivalence.	VTS	1999	DBLP DOI BibTeX RDF
14	Rajeev Murgai, Jawahar Jain, Masahiro Fujita	Efficient Scheduling Techniques for ROBDD Construction.	VLSI Design	1999	DBLP DOI BibTeX RDF
14	Vijay R. Sar-Dessai, D. M. H. Walker	Accurate Fault Modeling and Fault Simulation of Resistive Bridges.	DFT	1998	DBLP DOI BibTeX RDF	realistic bridges, zero-ohm bridges, Resistive bridging faults, low-voltage testing
14	Ilker Hamzaoglu, Janak H. Patel	Compact two-pattern test set generation for combinational and full scan circuits.	ITC	1998	DBLP DOI BibTeX RDF
14	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel	Effects of delay models on peak power estimation of VLSI sequential circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	variable delay, sustainable power, n-cycle power, peak power, genetic optimization
14	Haluk Konuk	Fault simulation of interconnect opens in digital CMOS circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	fault simulation, opens, breaks
14	Jian-Kun Zhao, Elizabeth M. Rudnick, Janak H. Patel	Static logic implication with application to redundancy identification.	VTS	1997	DBLP DOI BibTeX RDF	static logic implication, redundancy identification, set algebra, indirect implications, static learning algorithm, redundancy, iterative method, redundant faults
14	Chennian Di, Jochen A. G. Jess	An efficient CMOS bridging fault simulator: with SPICE accuracy.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
14	Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges	Statistical estimation of delay fault detectabilities and fault grading.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	transition delay and path delay faults, statistical delay fault analysis, fault detectabilities, fault coverage, random patterns
14	Masahiro Fujita	Verification of Arithmetic Circuits by Comparing Two Similar Circuits.	CAV	1996	DBLP DOI BibTeX RDF
14	Dennis J. Ciplickas, Ronald A. Rohrer	Expected current distributions for CMOS circuits.	ICCAD	1996	DBLP DOI BibTeX RDF	switching current, expected waveform, mean estimation, static analysis, statistical analysis, CMOS, autocorrelation, random processes, power spectral density
14	Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel	Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.	VTS	1996	DBLP DOI BibTeX RDF	GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm
14	S. Sundaram, Lalit M. Patnaik	Distributed logic simulation: time-first evaluation vs. event driven algorithms.	VLSI Design	1996	DBLP DOI BibTeX RDF	distributed logic simulation, time-first evaluation algorithm, event driven algorithm, digital circuit simulation, distributed simulation algorithms, parallel algorithms, parallel processing, VLSI, logic CAD, circuit analysis computing, integrated logic circuits, VLSI circuits, parallel logic simulation