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article(3127) book(2) data(1) incollection(27) inproceedings(5401) phdthesis(28)
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Remote. Sens.(274) IEEE Trans. Comput. Aided Des....(196) Comput. Electron. Agric.(167) CoRR(146) DAC(141) ISQED(139) DFT(114) IGARSS(113) ITC(112) DATE(101) ICCAD(101) IEEE Trans. Very Large Scale I...(99) ASP-DAC(77) VTS(76) IEEE Trans. Image Process.(65) Sensors(63) More (+10 of total 1832)
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Found 8586 publication records. Showing 8586 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
90Allan Y. Wong A Statistical Approach To Identify Semiconductor Process Equipment Related Yield Problems. Search on Bibsonomy DFT The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Systematic yield, Random yield, process equipment defect density, Statistical techniques, Yield analysis
82Qing Su, Charles C. Chiang, Jamil Kawa Hotspot Based Yield Prediction with Consideration of Correlations. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Systematic Yield, DFM (design for manufacturing), correlation, Yield, Hotspot, Yield Prediction
71Subarna Sinha, Charles C. Chiang A methodology for fast and accurate yield factor estimation during global routing. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
67Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya, Yuzi Kanazawa Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF analog/mixed-signal, optimization, yield, Pareto-front
62Stuart L. Riley Limitations to Estimating Yield Based on In-Line Defect Measurements. Search on Bibsonomy DFT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Defect-limited yield, Yield estimation, In-line defect measurements, Kill ratio estimation, Defect review sampling, Defect classification, Yield prediction
61M. Zhang, M. Z. Li, Gang Liu, M. H. Wang Yield Mapping in Precision Farming. Search on Bibsonomy CCTA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF yield monitor system, grain flow sensor, yield map, precision agriculture
61Athanasios T. Markinos, Theofanis A. Gemtos, D. Pateras, L. Toulios, G. Zerva, M. Papaeconomou The influence of cotton variety in the calibration factor of a cotton yield monitor. Search on Bibsonomy Oper. Res. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF cotton, yield mapping, yield monitor, calibration, varieties
61Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF FPGA redundancy, interconnect faults, fault tolerance, yield enhancement, interconnect model, yield prediction, catastrophic faults, FPGA interconnect
60Akhil Garg 0001, Prashant Dubey Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost. Search on Bibsonomy DFT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Compression and Yield, Memory, Repair, Fuse
55Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
55Rajnish K. Prasad, Israel Koren The Effect of Placement on Yield for Standard Cell Designs. Search on Bibsonomy DFT The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
49Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko Yield enhancements of design-specific FPGAs. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF design-specific FPGA, interconnect faults, interconnect utilization, yield enhancement, yield prediction, structured ASIC, FPGA interconnect
49Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Timing specifications testing, Test Environment, Tester OTA and yield, High-speed interconnect testing, Yield analysis
49Tom Thomas, Brian W. Anthony Area, Performance, and Yield Implications of Redundancy in On-Chip Caches. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF cache, redundancy, microprocessor, yield, SRAM, yield enhancement, microprocessor design, embedded SRAM
48Jianfeng Luo, Subarna Sinha, Qing Su, Jamil Kawa, Charles C. Chiang An IC manufacturing yield model considering intra-die variations. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF random variation, systematic variation, CMP, spatial correlation, manufacturing yield
47Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47Xiaohong Jiang 0001, Susumu Horiguchi, Yue Hao Predicting the Yield Efficacy of a Defect-Tolerant Embedded Core. Search on Bibsonomy DFT The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
44Fang Gong, Hao Yu 0001, Yiyu Shi 0001, Daesoo Kim, Junyan Ren, Lei He 0001 QuickYield: an efficient global-search based parametric yield estimation with performance constraints. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF circuit simulation, parametric yield
44Parijat Dube, Yezekael Hayel A Real-Time Yield Management Framework for E-Services. Search on Bibsonomy CEC/EEE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF discrete choice model, expected delay, price-delay tradeoff, optimization, queueing theory, Yield management
44Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Stephen W. Director Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF correlation, variability, yield, leakage
44Fred J. Meyer, Nohpill Park Predicting Defect-Tolerant Yield in the Embedded Core Context. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Yield, integrated circuit, defect tolerance, embedded core
44Pascal Bichebois, Pierre Mathery Analysis of Defect to Yield Correlation on Memories: Method, Algorithms and Limits. Search on Bibsonomy DFT The full citation details ... 1997 DBLP  DOI  BibTeX  RDF algorithm, tool, correlation, method, errors, inspection, yield, failure, defect, limits
44Hans T. Heineken, Wojciech Maly Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Standard Cell Designs, Synthesis, Interconnects, Manufacturability, Yield
43Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David T. Blaauw A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
43Martin D. F. Wong Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers. Search on Bibsonomy ICCD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
43Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu Failure Factor Based Yield Enhancement for SRAM Designs. Search on Bibsonomy DFT The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
43Bing Qiu 0003, Yvon Savaria, Meng Lu, Chunyan Wang 0004, Claude Thibeault Yield Modeling of a WSI Telecom Router Architecture. Search on Bibsonomy DFT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
43Arunshankar Venkataraman, Israel Koren Determination of Yield Bounds Prior to Routing. Search on Bibsonomy DFT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
41Sandra Levasseur, Frederic Duvivier Application of a yield model merging critical areas and defectivity to industrial products. Search on Bibsonomy DFT The full citation details ... 1997 DBLP  DOI  BibTeX  RDF industrial products, survey sampling based estimation tool, fabrication process, SGS-Thomson Crolles plant, multiple products, process versions, 0.5 micron, robustness, defectivity, EYES, critical areas, yield model, integrated circuit yield
40Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu Behavior-level yield enhancement approach for large-scaled analog circuits. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF process variation, analog circuits, yield enhancement
40Costas Argyrides, Giorgos Dimosthenous, Dhiraj K. Pradhan, Carlos Arthur Lang Lisbôa, Luigi Carro Reliability aware yield improvement technique for nanotechnology based circuits. Search on Bibsonomy SBCCI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF reliability, nanotechnology, yield improvement
40Cesare Ferri, Sherief Reda, R. Iris Bahar Parametric yield management for 3D ICs: Models and strategies for improvement. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF performance, process variations, leakage, 3D integration, yield management
40Sachin S. Sapatnekar Building your yield of dreams. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF nanoscale, modeling variations, CMOS, yield, design for manufacturability, DFM
40Love Singhal, Sejong Oh, Eli Bozorgzadeh Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors. Search on Bibsonomy CODES+ISSS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF configuration selection, delay budgeting, process variation, task allocation, within-die variation, timing yield
40Antonis Papanikolaou, T. Grabner, Miguel Miranda, Philippe Roussel, Francky Catthoor Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations. Search on Bibsonomy CODES+ISSS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF system exploration, process variability, parametric yield
40Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF pareto surfaces, performance space, optimization, yield
40Azharul Karim, Saman K. Halgamuge, A. J. R. Smith, Arthur L. Hsu Manufacturing Yield Improvement by Clustering. Search on Bibsonomy ICONIP (3) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Clustering quality, Filtration of noisy data, Data mining, Self-organising map, Yield improvement
40Marco Ottavi, Xiaopeng Wang, Fred J. Meyer, Fabrizio Lombardi Simulation of reconfigurable memory core yield. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Markov chain, manufacturability, yield, defect tolerance
40Tianxu Zhao, Yue Hao, Peijun Ma, Taifeng Chen Relation between Reliability and Yield of IC's Based on Discrete Defect Distribution Model. Search on Bibsonomy DFT The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Distribution of the defect size, Reliability, Yield
40Israel Koren, Zahava Koren Incorporating Yield Enhancement into the Floorplanning Process. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF memory ICs, routing complexity, redundancy, microprocessor, Floorplanning, yield
40Israel Koren Should Yield be a Design Objective? Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF routing, floorplanning, yield, compaction, critical area
40Zhan Chen, Israel Koren Techniques for Yield Enhancement of VLSI Adders. Search on Bibsonomy ASAP The full citation details ... 1995 DBLP  DOI  BibTeX  RDF VLSI yield, VLSI adder, defect tolerance, VLSI layout
40Bruno Ciciani Redundancy effect on yield of binary tree RAMs. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF semiconductor memory design, VLSI chip design, yield evaluation, Fault-tolerant memories
39Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
39Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada Timing-driven cell layout de-compaction for yield optimization by critical area minimization. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
39Azadeh Davoodi, Ankur Srivastava 0001 Variability driven gate sizing for binning yield optimization. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF speed binning, process variations, gate sizing
39Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy 0001 A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Zhaojun Wo, Israel Koren, Maciej J. Ciesielski An ILP Formulation for Yield-driven Architectural Synthesis. Search on Bibsonomy DFT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Joseph A. Reynick Investment vs. Yield Relationship for Memories and IP in SOC. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
38Zhaoliang Pan, Melvin A. Breuer Estimating Error Rate in Defective Logic Using Signature Analysis. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Binning integrated circuits, effective yield, signature testing, error rate, error tolerance, yield loss
38Shishpal Rawat, Raul Camposano, Andrew B. Kahng, Joseph Sawicki, Mike Gianfagna, Naeem Zafar, Atul Sharan DFM: where's the proof of value? Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF ROI, DFM, design for manufacture, OPC, RET, yield optimization, design for yield
38Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices. Search on Bibsonomy J. Electron. Test. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF timing specifications testing, test environment, tester OTA and yield, high-speed interconnect testing, yield analysis
37Junying Sun, Jinliang Huang, Jing Chen, Lihui Wang Grain Yield Estimating for Hubei Province Using Remote Sensing Data - Take Semilate Rice as an Example. Search on Bibsonomy ESIAT (1) The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Crop yield, Crop yield estimation models using remote sensing data, Productivity zoning, Hubei province
37Kees Veelenturf The Road to Better Reliability and Yield Embedded DfM Tools. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF wire spreading, yield prediction, yield improvement, DfM
37Sy-Yen Kuo, W. Kent Fuchs Fault Diagnosis and Spare Allocation for Yield Enhancement in Large Reconfigurable PLA's. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF reconfigurable PLAs, spare allocation, circuit density, chip size, fault diagnosis algorithm, computational complexity, fault tolerant computing, fault location, programmable logic arrays, multiple faults, logic arrays, yield enhancement, reconfigurable logic, memory structures, circuit reliability, manufacturing yield
37James C. Harden, Noel R. Strader II Architectural Yield Optimization for WSI. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1988 DBLP  DOI  BibTeX  RDF architectural yield optimisation, integrated circuit yield modeling, computing structures, VLSI, fault tolerant computing, computer architecture, redundancy, failure analysis, wafer-scale integration, circuit reliability
36Lin Huang 0002, Qiang Xu 0001 Performance yield-driven task allocation and scheduling for MPSoCs under process variation. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF performance yield, process variation, task scheduling
36Michal Wegiel, Chandra Krintz Dynamic prediction of collection yield for managed runtimes. Search on Bibsonomy ASPLOS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF reference bits, clustering, parallel, concurrent, operating system, garbage collection, yield prediction
36Megat Norulazmi Megat Mohamed Noor, Shaidah Jusoh Visualizing the Yield Pattern Outcome for Automatic Data Exploration. Search on Bibsonomy Asia International Conference on Modelling and Simulation The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Automatic data exploration, manufactuirng yield predictive system, Data mining, machine learning, data visualization, predictive system
36Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF decoupled design, 8T, 6T, stacked devices, stability, yield, sram, double gate
36Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF dose map, placement, timing yield, leakage power reduction
36Yi Wang, Wai-Shing Luk, Xuan Zeng 0001, Jun Tao 0001, Changhao Yan, Jiarong Tong, Wei Cai 0003, Jia Ni Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF non-Gaussian, process variations, yield, clock skew scheduling
36Mohamed H. Abu-Rahma, Kinshuk Chowdhury, Joseph Wang, Zhiqin Chen, Sei Seung Yoon, Mohab Anis A methodology for statistical estimation of read access yield in SRAMs. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF access failure, random variations, memory, variability, statistical modeling, yield, SRAM, worst-case
36Donghwi Lee, Erik H. Volkerink, Intaik Park, Jeff Rearick Empirical Validation of Yield Recovery Using Idle-Cycle Insertion. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF false failure, ATPG, delay testing, functional test, structural test, IR drop, yield loss
36Fei Su, Krishnendu Chakrabarty Yield enhancement of reconfigurable microfluidics-based biochips using interstitial redundancy. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF space redundancy, reconfiguration, Microfluidics, yield enhancement
36Song Peng, Rajit Manohar Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF asynchronous circuits, yield, defect tolerance, 3D integration, self-reconfiguration
36Robert Madge New test paradigms for yield and manufacturability. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF nanometer-era semiconductor, test paradigm, yield and manufacturability
36Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester Parametric yield estimation considering leakage variability. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF variability, leakage, parametric yield
36Chaochang Chiu, Jih-Tay Hsu, Chih-Yung Lin The Application of Genetic Programming in Milk Yield Prediction for Dairy Cows. Search on Bibsonomy Rough Sets and Current Trends in Computing The full citation details ... 2000 DBLP  DOI  BibTeX  RDF dynamic mutation, milk yield prediction, Genetic programming
36G. S. Samudra, H. M. Chen, D. S. H. Chan, Yaacob Ibrahim Yield Optimization by Design Centering and Worst-Case Distance Analysis. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF worst-case distance, design centering, optimization, VLSI design, parametric yield
36Witold A. Pleskacz Yield Estimation of VLSI Circuits with Downscaled Layouts. Search on Bibsonomy DFT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF IC layout scaling, VLSI circuits, critical area, spot defects, manufacturing yield
36Dimitris Nikolos, Haridimos T. Vergos On the Yield of VLSI Processors with on-chip CPU Cache. Search on Bibsonomy EDCC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Indexing terms On-chip CPU caches, Partially good chips, Fault Tolerance, Yield Enhancement
36Steven D. Millman Improving quality: Yield versus test coverage. Search on Bibsonomy J. Electron. Test. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF quality, Fault modeling, yield, test economics, physical defects
35Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm. Search on Bibsonomy DSD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Guo Yu, Peng Li 0001 Yield-aware hierarchical optimization of large analog integrated circuits. Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy 0001 Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
35Zhaojun Wo, Israel Koren, Maciej J. Ciesielski Yield-aware Floorplanning. Search on Bibsonomy DSD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
35Dirk K. de Vries, Paul L. C. Simon Calibration of Open Interconnect Yield Models. Search on Bibsonomy DFT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
35Noh-Jin Park, Byoungjae Jin, K. M. George, Nohpill Park, Minsu Choi Regressive Testing for System-on-Chip with Unknown-Good-Yield. Search on Bibsonomy DFT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
35Kamal Rajkanan Yield Analysis Methodology for Low Defectivity Wafer Fabs. Search on Bibsonomy MTDT The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
34Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai DFM/DFY practices during physical designs for timing, signal integrity, and power. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF 0.13 micron, DFY, dynamic IR drop, process variation, physical designs, DFM, design for manufacturability, signal integrity, timing integrity, yield analysis, design for yield
34Gerard A. Allan, Anthony J. Walton Efficient critical area estimation for arbitrary defect shapes. Search on Bibsonomy DFT The full citation details ... 1997 DBLP  DOI  BibTeX  RDF critical area estimation, arbitrary defect shapes, circular defects, elliptical defects, rod shaped defects, arbitrary shaped defects, Edinburgh Yield Estimator, Cadence layout editor, EYE-sampling tool, EYE, EYES, integrated circuit yield, IC layout
33Uthman Alsaiari, Resve A. Saleh Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Partitioning, Redundancy, Yield, Flip-Flop
32M. Javad Paknejad, Farrokh Nasri, John F. Affisco Yield improvement and yield variability reduction in an EOQ model with planned shortages and random yield. Search on Bibsonomy Comput. Ind. Eng. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
32Robert O. Briggs, Sajda Qureshi, Bruce A. Reinig Satisfaction Attainment Theory as a Model for Value Creation. Search on Bibsonomy HICSS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Nam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, Youngsoo Shin Frequency and yield optimization using power gates in power-constrained designs. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF optimization, yield, power gate, frequency
32Jin-Tai Yan, Zhi-Wei Chen Redundant wire insertion for yield improvement. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF redundant wire, routing, yield
32Yan Pan, Joonho Kong, Serkan Ozdemir, Gokhan Memik, Sung Woo Chung Selective wordline voltage boosting for caches to manage yield under process variations. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF access time failure, selective wordline voltage boosting, cache, process variations, yield
32Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs. Search on Bibsonomy FPGA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF FPGA, routing, variation, yield enhancement
32Jing Li 0073, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy 0001 Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF STT MRAM, yield
32Qiang Zhou 0001, Yici Cai, Duo Li, Xianlong Hong A Yield-Driven Gridless Router. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF gridless routing, integrated circuit layout, critical area, design for yield
32N. Pete Sedcole, Peter Y. K. Cheung Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. Search on Bibsonomy FPGA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF statistical theory, within-die variability, modelling, FPGA, delay, reconfiguration, process variation, yield
32Greg Yeric, Ethan Cohen, John Garcia, Kurt Davis, Esam Salem, Gary Green Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF systematic yield loss, test structure, BEOL, DFM, process monitoring, silicon debug, infrastructure IP
32Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja Yield-Driven, False-Path-Aware Clock Skew Scheduling. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF performance-related circuit yield loss, circuit-level parameters, DFM, clock skew scheduling
32Katherine Shu-Min Li, Chung-Len Lee 0001, Yao-Wen Chang, Chauchin Su, Jwu E. Chen Multilevel full-chip routing with testability and yield enhancement. Search on Bibsonomy SLIP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF multilevel routing, yield, testability
32Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang A methodology to improve timing yield in the presence of process variations. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF timing analysis, gate sizing, timing yield
32Farid N. Najm, Noel Menezes Statistical timing analysis based on a timing yield model. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF statistical timing analysis, principal components, timing yield
32Thomas S. Barnett, Adit D. Singh, Victor P. Nelson Yield-Reliability Modeling for Fault Tolerant Integrated Circuits. Search on Bibsonomy DFT The full citation details ... 2001 DBLP  DOI  BibTeX  RDF infant mortality, negative binomial distribution, clustering, reliability, redundancy, yield, defects, defect tolerance, burn-in
32Hugo Cheung, Sandeep K. Gupta 0001 A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF critical severity, test escape, fault modeling, IDDQ, yield loss
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