Search results for "deep-submicron"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
94	N. Venkateswaran 0002, S. Balaji, V. Sridhar	Fault tolerant bus architecture for deep submicron based processors.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF	deep submicron technology, fault tolerance, interconnect, electromigration
80	Chih-Wen Lu, Chauchin Su, Chung-Len Lee 0001, Jwu E. Chen	Is IDDQ testing not applicable for deep submicron VLSI in year 2011?	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	deep submicron VLSI, IDDQ current estimation, random process deviations, IDDQ distributions, VLSI, statistical analysis, integrated circuit testing, CMOS integrated circuits, leakage currents, IDDQ testing, statistical approach, standard deviation, input vectors, circuit size
75	Li-Rong Zheng 0001, Hannu Tenhunen	Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI Circuits.	ARVLSI	1999	DBLP DOI BibTeX RDF	Mixed-Signal VLSI, Interconnection, Crosstalk, Noise Margin
74	Michael Nicolaidis	Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies.	VTS	1999	DBLP DOI BibTeX RDF	Very deep submicron, soft-errors, single event upsets, fault tolerant design
67	Mohammad Tehranipoor, Kenneth M. Butler	Guest Editors' Introduction: IR Drop in Very Deep-Submicron Designs.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	PSN, IR drop, power supply noise, deep-submicron designs
67	Ilia Polian, Sandip Kundu, Jean-Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker 0001	Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.	VTS	2005	DBLP DOI BibTeX RDF	Deep submicron technology modeling, Resistive bridging faults
67	Lorena Anghel, Michael Nicolaidis, Issam Alzaher-Noufal	Self-Checking Circuits versus Realistic Faults in Very Deep Submicron.	VTS	2000	DBLP DOI BibTeX RDF	Concurrent checking, self–checking circuits, timing faults, very deep submicron, hardware fault tolerance, soft errors, defects, nanometer technologies
67	Rosa Rodríguez-Montañés, Joan Figueras	Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs.	DATE	1998	DBLP DOI BibTeX RDF	IDDQ testability, CMOS, deep-submicron
67	Stephan P. Athan, David L. Landis, Sami A. Al-Arian	A novel built-in current sensor for IDDQ testing of deep submicron CMOS ICs.	VTS	1996	DBLP DOI BibTeX RDF	deep submicron CMOS ICs, fault diagnosability, ULSI CMOS, fault diagnosis, integrated circuit testing, fault detectability, CMOS integrated circuits, leakage currents, built-in current sensor, I/sub DDQ/ testing, electric current measurement, ULSI, electric sensing devices
61	Adrian Maxim, M. Gheorghe	A novel physical based model of deep-submicron CMOS transistors mismatch for Monte Carlo SPICE simulation.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
61	Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi	Noise tolerant low voltage XOR-XNOR for fast arithmetic.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	XOR-XNOR circuits, multipliers, noise tolerant, deep submicron, nanometer technology
53	S. Yoshitomi	Challenges to Accuracy for the Design of Deep-Submicron RF-CMOS Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	130 nm, RF-CMOS analog circuits, MOSFET models, EKV3.0 model, electro magnetic effects, building blocks, deep submicron
53	Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R. Suresh	Transistor Flaring in Deep Submicron-Design Considerations.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Deep Submicron (DSM), pullback, photolithography, Subwavelength-lithography, Optical Proximity Correction (OPC), SPICE-models, standard-ce1l library, Design for Manufacturability (DFM)
53	Rahul Kumar, C. P. Ravikumar	Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Power Estimation, Leakage Power, Linear Regression, Deep Submicron
53	Anton Chichkov, Dirk Merlier, Peter Cox	Current Testing Procedure for Deep Submicron Devices.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	ASIC testing, IDDQ, deep submicron
52	Patrick Schaumont, David D. Hwang	Turning liabilities into assets: Exploiting deep submicron CMOS technology to design secure embedded circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
47	Paul-Peter Sotiriadis, Anantha P. Chandrakasan	A bus energy model for deep submicron technology.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
47	Yonghee Im, Kaushik Roy 0001	O2ABA: a novel high-performance predictable circuit architecture for the deep submicron era.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
47	Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni	Extending the Viability of IDDQ Testing in the Deep Submicron Era.	ISQED	2002	DBLP DOI BibTeX RDF
47	Naresh R. Shanbhag, Krishnamurthy Soumyanath, Samuel Martin	Reliable low-power design in the presence of deep submicron noise (embedded tutorial session).	ISLPED	2000	DBLP DOI BibTeX RDF
47	Lun Ye, Foong-Charn Chang, Peter Feldmann, Rakesh Chadha, Nagaraj Ns, Frank Cano	Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs.	DATE	1999	DBLP DOI BibTeX RDF
47	Ming-Dou Ker, Chung-Yu Wu, Tao Cheng, Hun-Hsien Chang	Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
47	J. Will Specks, Walter L. Engl	Computer-aided design and scaling of deep submicron CMOS.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
47	Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini	Bringing NoCs to 65 nm.	IEEE Micro	2007	DBLP DOI BibTeX RDF	network on chip, low-power design, power management, multicore architectures, on-chip interconnection networks, design aids, deep submicron design
47	Karim Arabi, Resve A. Saleh, Xiongfei Meng	Power Supply Noise in SoCs: Metrics, Management, and Measurement.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	metrics, DFT, power supply noise, deep-submicron, production test, power integrity
47	Nallamothu Satyanarayana, Madhu Mutyam, A. Vinaya Babu	Exploiting on-chip data behavior for delay minimization.	SLIP	2007	DBLP DOI BibTeX RDF	coding, crosstalk, deep-submicron
47	Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi	A high speed and leakage-tolerant domino logic for high fan-in gates.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	high speed, noise immunity, deep submicron, fan-in, domino
47	Masaharu Goto, Toshinori Sato	Leakage Energy Reduction in Register Renaming.	ICDCS Workshops	2004	DBLP DOI BibTeX RDF	super-scalar processors, embedded processors, register renaming, deep submicron, Leakage energy
47	Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Ana Sonia Leon	A dual-core 64b ultraSPARC microprocessor for dense server applications.	DAC	2004	DBLP DOI BibTeX RDF	L2, UltraSPARC, coupling noise, deep submicron technology, dense server, dual-core, throughput computing, cache, multiprocessor, leakage, NBTI, negative bias temperature instability
47	Mohamed A. Elgamel, Tarek Darwish, Magdy A. Bayoumi	Noise Tolerant Low Power Dynamic TSPCL D Flip-Flops.	ISVLSI	2002	DBLP DOI BibTeX RDF	noise, power, flip-flop, deep submicron
47	Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy 0001	Dynamic Noise Analysis with Capacitive and Inductive Coupling.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	capacitiance, dynamic noise margin, crosstalk, inductance, noise analysis, deep submicron, noise model
47	Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul	Estimation of the likelihood of capacitive coupling noise.	DAC	2002	DBLP DOI BibTeX RDF	noise, signal integrity, deep submicron
47	Abby A. Ilumoka	Efficient prediction of interconnect crosstalk using neural networks.	ICTAI	2000	DBLP DOI BibTeX RDF	interconnect crosstalk prediction, deep submicron downscaling, wirecells, modular artificial neural networks, multiparadigm prototyping system, equicoupling contours, isocouples, transconductance amplifier, neural networks, delays, delay, finite element method, neural nets, crosstalk, experimental results, circuit CAD, finite element analysis, circuit simulation, circuit simulator, integrated circuit interconnections, wafer-scale integration, wafer scale integration
47	Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng	Dynamic Timing Analysis Considering Power Supply Noise Effects.	ISQED	2000	DBLP DOI BibTeX RDF	dynamic timing analysis, input pattern dependent, power supply noise, deep submicron designs
47	Anirudh Devgan	Efficient coupled noise estimation for on-chip interconnects.	ICCAD	1997	DBLP DOI BibTeX RDF	coupled noise estimation, dynamic logic circuit families, noise criticality pruning, physical design based noise avoidance, circuit simulation, on-chip interconnects, Elmore delay, noise analysis, timing simulation, integrated circuit noise, deep submicron design
42	José Luis Rosselló, Jaume Segura 0001	A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk.	DATE	2004	DBLP DOI BibTeX RDF
33	Jan Schat	Fault Clustering in deep-submicron CMOS Processes.	DATE	2008	DBLP DOI BibTeX RDF
33	Tino Heijmen	Soft Error Rates in Deep-Submicron CMOS Technologies.	IOLTS	2006	DBLP DOI BibTeX RDF
33	Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil	Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
33	Zhao Li, C.-J. Richard Shi	An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation.	DATE	2005	DBLP DOI BibTeX RDF
33	Tino Heijmen	Analytical Semi-Empirical Model for SER Sensitivity Estimation of Deep-Submicron CMOS Circuits.	IOLTS	2005	DBLP DOI BibTeX RDF
33	Xiaojun Li 0001, Bing Huang, J. Qin, X. Zhang, Michael Talmor, Z. Gur, Joseph B. Bernstein	Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE.	ISQED	2005	DBLP DOI BibTeX RDF
33	Geoff V. Merrett, Bashir M. Al-Hashimi	Leakage Power Analysis and Comparison of Deep Submicron Logic Gates.	PATMOS	2004	DBLP DOI BibTeX RDF
33	Peter Caputa, Henrik Fredriksson, Martin Hansson, Stefan Back Andersson, Atila Alvandpour, Christer Svensson	An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies.	PATMOS	2004	DBLP DOI BibTeX RDF
33	Nattawut Thepayasuwan, Alex Doboli	Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip.	DATE	2004	DBLP DOI BibTeX RDF
33	Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex	Interconnect width selection for deep submicron designs using the table lookup method.	SLIP	2004	DBLP DOI BibTeX RDF	interconnect sizing, power-delay trade-off, wire sizing
33	Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann	Cache Array Architecture Optimization at Deep Submicron Technologies.	ICCD	2004	DBLP DOI BibTeX RDF
33	Mohamed Abbas, Makoto Ikeda, Kunihiro Asada	Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime.	DFT	2004	DBLP DOI BibTeX RDF
33	Ming-Dou Ker, Wen-Yi Chen	Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS Processes.	ISQED	2004	DBLP DOI BibTeX RDF
33	Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim	Profile-guided microarchitectural floorplanning for deep submicron processor design.	DAC	2004	DBLP DOI BibTeX RDF	microarchitectural planning, computer architecture, floorplanning
33	Lei Wang 0003, Naresh R. Shanbhag	Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
33	Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng	Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
33	Tim Schoenauer, Jörg Berthold, Christoph Heer	Reduced Leverage of Dual Supply voltages in Ultra Deep Submicron Technologies.	PATMOS	2003	DBLP DOI BibTeX RDF
33	James Lin	Design technology challenges for system and chip level designs in very deep submicron technologies.	CODES+ISSS	2003	DBLP DOI BibTeX RDF
33	Nattawut Thepayasuwan, Vaishali Damle, Alex Doboli	Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip.	ICCD	2003	DBLP DOI BibTeX RDF
33	Zeynep Toprak Deniz, Yusuf Leblebici	Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
33	Michele Favalli, Marcello Dalpasso	Bridging fault modeling and simulation for deep submicron CMOS ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
33	Xavier Aragonès, José Luis González 0001, Francesc Moll, Antonio Rubio 0001	Noise Generation and Coupling Mechanisms in Deep-Submicron ICs.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
33	Luís Miguel Silveira, Nuno Vargas	Characterizing Substrate Coupling in Deep-Submicron Designs.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
33	Michele Favalli, Cecilia Metra	Online Testing Approach for Very Deep-Submicron ICs.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
33	Cristian Constantinescu	Impact of Deep Submicron Technology on Dependability of VLSI Circuits.	DSN	2002	DBLP DOI BibTeX RDF
33	Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T. N. Vijaykumar	Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay.	HPCA	2002	DBLP DOI BibTeX RDF	resizable cache design, low power processor, energy aware architecture
33	Mohammad M. Mansour, Naresh R. Shanbhag	Simplified current and delay models for deep submicron CMOS digital circuits.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
33	Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar	Reducing leakage in a high-performance deep-submicron instruction cache.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
33	Manoj Sachdev	Current-Based Testing for Deep-Submicron VLSIs.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF
33	Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar	An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches.	HPCA	2001	DBLP DOI BibTeX RDF
33	Pirouz Bazargan-Sabet, Fabrice Ilponse	A Model for Crosstalk Noise Evaluation in Deep Submicron Processes.	ISQED	2001	DBLP DOI BibTeX RDF
33	Ali Keshavarzi, Kaushik Roy 0001, Charles F. Hawkins	Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
33	Dennis Sylvester, Kurt Keutzer	A global wiring paradigm for deep submicron design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
33	Zemo Yang, Samiha Mourad	Crosstalk in Deep Submicron DRAMs.	MTDT	2000	DBLP DOI BibTeX RDF	Noise and Submicron, Crosstalk, DRAM
33	Kamran Eshraghian	Deep Submicron USLI Design Paradigm: Who is Writing the Future?	ISQED	2000	DBLP DOI BibTeX RDF
33	Carlo Guardiani, Andrzej J. Strojwas	Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead?	ISQED	2000	DBLP DOI BibTeX RDF
33	Rafi Levy, David T. Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov	ClariNet: a noise analysis tool for deep submicron design.	DAC	2000	DBLP DOI BibTeX RDF
33	Kenneth L. Shepard, Vinod Narayanan, Ron Rose	Harmony: static noise analysis of deep submicron digital integrated circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
33	Amir H. Salek, Jinan Lou, Massoud Pedram	An integrated logical and physical design flow for deep submicron circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
33	Todd M. Austin	DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design.	MICRO	1999	DBLP DOI BibTeX RDF
33	Li-Rong Zheng 0001, Hannu Tenhunen	Effective power and ground distribution scheme for deep submicron high speed VLSI circuits.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
33	Rajamohana Hegde, Naresh R. Shanbhag	Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
33	Th. Calin, Lorena Anghel, Michael Nicolaidis	Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS.	VTS	1999	DBLP DOI BibTeX RDF
33	Jason Cong, Lei He 0001	An efficient technique for device and interconnect optimization in deep submicron designs.	ISPD	1998	DBLP DOI BibTeX RDF
33	Jay Abraham	Power calculation and modeling in deep submicron.	ISLPED	1998	DBLP DOI BibTeX RDF
33	N. S. Nagaraj, Kenneth L. Shepard, Takahide Inone	Taming Noise in Deep Submicron Digital Integrated Circuits (Panel).	DAC	1998	DBLP DOI BibTeX RDF
33	Hugo De Man	Education for the Deep Submicron Age: Business as Usual?	DAC	1997	DBLP DOI BibTeX RDF
33	Mohamed A. Imam, Mohamed A. Osman, Ashraf A. Osman	MOSFET global modeling for deep submicron devices with a modified BSIM1 SPICE model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
33	Kenneth L. Shepard, Vinod Narayanan	Noise in deep submicron digital design.	ICCAD	1996	DBLP DOI BibTeX RDF	static analysis, noise, crosstalk, inductance, CMOS circuits, noise margins
33	Franco Venturi, R. Kent Smith, Enrico Sangiorgi, Mark R. Pinto, Bruno Riccò	A general purpose device simulator coupling Poisson and Monte Carlo transport with applications to deep submicron MOSFETs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
33	Mehrdad Nourani, Arun Radhakrishnan	Testing On-Die Process Variation in Nanometer VLSI.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	nanometer VLSI, ultra deep-submicron, fast Fourier transform, process variation, frequency domain, ring oscillator
33	Kaushik Roy 0001, T. M. Mak, Kwang-Ting (Tim) Cheng	Test Consideration for Nanometer-Scale CMOS Circuits.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	deep-submicron test, delay test, statistical timing, nanometer technologies
33	Ken Butler	Conference Reports: 2005 International Test Conference.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	low-cost ATE, very-deep submicron tecnology, yield ramping, International Test Conference, ITC 2005
33	Naresh R. Shanbhag	Reliable and energy-efficient digital signal processing.	DAC	2002	DBLP DOI BibTeX RDF	reliability, communications, low-power, energy-efficiency, noise, broadband, noise-tolerance, deep submicron
33	Amir H. Farrahi, David J. Hathaway, Maogang Wang, Majid Sarrafzadeh	Quality of EDA CAD Tools: Definitions, Metrics and Directions.	ISQED	2000	DBLP DOI BibTeX RDF	Design Quality Metrics, Integrated Design Exploration, Incremental Synthesis, Layout-Driven Synthesis' System-Level Interconnect Prediction and Planning, Tool Interoperability, Deep Submicron Designs
33	Mariagrazia Graziano, Marco Delaurenti, Guido Masera, Gianluca Piccinini, Maurizio Zamboni	Noise Safety Design Methodologies.	ISQED	2000	DBLP DOI BibTeX RDF	Electromigration Safety, Deep-submicron Design Reliability, Noise, Noise Tolerance, Noise Models
27	Laurent Sauvage, Sylvain Guilley, Yves Mathieu	Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	EMA, security, FPGA, DPA, SCA, cartography
27	Prateek Mishra, Anish Muttreja, Niraj K. Jha	Low-power FinFET circuit synthesis using multiple supply and threshold voltages.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Low-power, linear programming, synthesis, TCMS
27	Nishant Chandra, Apoorva Kumar Yati, A. B. Bhattacharyya	Extended-Sakurai-Newton MOSFET Model for Ultra-Deep-Submicrometer CMOS Digital Design.	VLSI Design	2009	DBLP DOI BibTeX RDF
27	T. Venkata Kalyan, Madhu Mutyam, Vijaya Sankara Rao Pasupureddi	Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
27	Preetham Lakshmikanthan, Adrian Nunez	A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits.	PATMOS	2006	DBLP DOI BibTeX RDF
27	Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp	DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.	DATE	2006	DBLP DOI BibTeX RDF
27	Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham	A Scheme for On-Chip Timing Characterization.	VTS	2006	DBLP DOI BibTeX RDF
27	Uday Reddy Bandi, Murty Dasaka, Pavan K. Kumar	Design in reliability for communication designs.	DAC	2006	DBLP DOI BibTeX RDF	electro migration, nanometer design challenges, self heat, reliability, EDA tools