Search results for "scan-path"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
83	Nilabha Dev, Sandeep Bhatia, Subhasish Mukherjee, Sue Genova, Vinayak Kadam	A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings.	VLSI Design	2008	DBLP DOI BibTeX RDF
73	Jason P. Hurst, Nick Kanopoulos	Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	flip-flop sharing, standard scan path, standard scan path design, two-vector test sets, VLSI, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, sequential circuits, flip-flops, integrated logic circuits, sequential machines, delay fault testing
73	Kuen-Jong Lee, Tsung-Chu Huang	An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	multiple scan chains, interleaving scan, test power reduction, peak power reduction
73	Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen	Peak-power reduction for multiple-scan circuits during test application.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	peak-power reduction, multiple scan chain based circuits, peak periodicity, peak width, power waveforms, scan-based circuits, delay buffers, interleaving scan technique, data output, logic testing, logic testing, delays, integrated circuit testing, application specific integrated circuits, SOC, boundary scan testing
62	Seongmoon Wang, Srimat T. Chakradhar	A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
62	Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang 0008	Double-Tree Scan: A Novel Low-Power Scan-Path Architecture.	ITC	2003	DBLP DOI BibTeX RDF
62	Seongmoon Wang, Srimat T. Chakradhar	A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs.	ITC	2003	DBLP DOI BibTeX RDF
61	Samantha Edirisooriya, Geetani Edirisooriya	Diagnosis of scan path failures.	VTS	1995	DBLP DOI BibTeX RDF	scan path failures, scan based diagnostic schemes, faulty circuits, logic circuitry, scan chain fault diagnosis, fault diagnosis, logic testing, integrated circuit testing, design for testability, combinational circuits, integrated logic circuits
60	Nur A. Touba, Edward J. McCluskey	Applying two-pattern tests using scan-mapping.	VTS	1996	DBLP DOI BibTeX RDF	scan-mapping, combinational mapping logic, logic testing, built-in self test, built-in self-testing, fault coverage, delay faults, pseudo-random testing, deterministic testing, two-pattern tests
60	Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi	ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
60	Mohammad Alisafaee, Safar Hatami, Ehsan Atoofian, Zainalabedin Navabi, Ali Afzali-Kusha	A low-power scan-path architecture.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
55	C. P. Ravikumar, Rajamani Rajarajan	Genetic Algorithms for Scan Path Design.	VLSI Design	1996	DBLP DOI BibTeX RDF
53	Seiken Yano	Unified scan design with scannable memory arrays.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	unified scan design, scannable memory arrays, single scan path, scan operation time, scannable register file, fault diagnosis, design for testability, design-for-testability, automatic testing, logic CAD, flip-flops, flip-flops, arrays, shift registers, integrated memory circuits
48	Roberto Bevacqua, Luca Guerrazzi, Franco Fummi	SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation.	EUROMICRO	1996	DBLP DOI BibTeX RDF	test storage, scan-path techniques, Built-In Self Test, design for testability, Design for Testability, BIST, test pattern generation, SCAN, test sequences
48	Yoshihiro Konno, Kazushi Nakamura, Tatsushige Bitoh, Koji Saga, Seiken Yano	A Consistent Scan Design System for Large-Scale ASICs.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
45	Shih Ping Lin 0001, Chung-Len Lee 0001, Jwu E. Chen	A Scan Matrix Design for Low Power Scan-Based Test.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
45	Weiwei Mao, Michael D. Ciletti	Reducing correlation to improve coverage of delay faults in scan-path design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
44	Víctor H. Champac, Joan Figueras	Testability of floating gate defects in sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flip-flops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flip-flops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing
40	Michael Nicolaidis, O. Kebichi, Vladimir Castro Alves	Trade-offs in scan path and BIST implementations for RAMs.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	RAM test algorithms, BIST, Aliasing, signature analysis, scan path, coupling faults
40	Yehezkel Yeshurun, Eric L. Schwartz	Shape Description with a Space-Variant Sensor: Algorithms for Scan-Path, Fusion, and Convergence Over Multiple Scans.	IEEE Trans. Pattern Anal. Mach. Intell.	1989	DBLP DOI BibTeX RDF	space-variant sensor, fixation points, multiscan view, boundary curvature, computer vision, convergence, computerised pattern recognition, fusion, machine vision, image sensors, image sensors, scan-path
38	Arno Kunzmann, Hans-Joachim Wunderlich	An analytical approach to the partial scan problem.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	partial scan path, sequential test generation, design for testability
38	Sunggu Lee, Kang G. Shin	Design for test using partial parallel scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
38	Robert B. Norwood, Edward J. McCluskey	High-Level Synthesis for Orthogonal Sca.	VTS	1997	DBLP DOI BibTeX RDF
37	Haruhiko Takeuchi, Yoshiko Habuchi	A Quantitative Method for Analyzing Scan Path Data Obtained by Eye Tracker.	CIDM	2007	DBLP DOI BibTeX RDF
37	Makoto Ikeda, Hideyuki Aoki, Kunihiro Asada	DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path.	ISQED	2000	DBLP DOI BibTeX RDF
35	Mathew D. Hunter, Quoc Hao Mach, Ratvinder Singh Grewal 0001	The relationship between scan path direction and cognitive processing.	C3S2E	2010	DBLP DOI BibTeX RDF	QEEG, human-computer interaction, eye tracking, cognitive processing
33	Ozgur Sinanoglu	Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Test power reduction, Scan power reduction, Serial transformations, Scan chain modification, Design for testability, Core-based testing
33	Ozgur Sinanoglu, Alex Orailoglu	Scan Power Minimization through Stimulus and Response Transformations.	DATE	2004	DBLP DOI BibTeX RDF
33	Robert B. Norwood, Edward J. McCluskey	Synthesis-for-scan and scan chain ordering.	VTS	1996	DBLP DOI BibTeX RDF	synthesis-for-scan procedure, scan chain ordering, testable circuit design, beneficial scan, VLSI, logic testing, integrated circuit testing, design for testability, logic design, sequential circuits, logic synthesis, flip-flops, integrated circuit design, integrated logic circuits, test strategy, boundary scan testing, functional specifications
31	Minoru Nakayama, Yosiyuki Takahasi	Estimation of certainty for responses to multiple-choice questionnaires using eye movements.	ACM Trans. Multim. Comput. Commun. Appl.	2008	DBLP DOI BibTeX RDF	scan-path analysis, support vector machines, Eye-movements, certainty
31	Masayuki Tsukisaka, Takashi Nanya	A testable design for asynchronous fine-grain pipeline circuits.	PRDC	2000	DBLP DOI BibTeX RDF	asynchronous fine-grain pipeline circuits, dynamic gates, high-performance datapath design, pipeline latches, scan latch libraries, logic testing, logic CAD, SPICE, CMOS technology, scan path, SPICE simulation, testable design
30	T. A. García, Antonio J. Acosta 0001, J. M. Mora, J. Ramos, José Luis Huertas	Self-Timed Boundary-Scan Cells for Multi-Chip Module Test.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	self-timed CMOS design, testing interconnections, boundary-scan, MCM testing
30	Michael Gössel, Egor S. Sogomonyan, Adit D. Singh	Scan-Path with Directly Duplicated and Inverted Duplicated Registers.	VTS	2002	DBLP DOI BibTeX RDF
28	Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya	An Efficient Scan Tree Design for Compact Test Pattern Set.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
27	Varun Arora, Indranil Sengupta 0001	A Unified Approach to Partial Scan Design using Genetic Algorithm.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
26	Jeff Klingner	Fixation-aligned pupillary response averaging.	ETRA	2010	DBLP DOI BibTeX RDF	fixation-aligned pupillary response, pupillometry, task-evoked pupillary response, eye tracking, scan path, fixation
26	Zahari M. Darus, Iftekhar Ahmed 0003, Liakot Ali	A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test processor chip, multiple polynomial linear feedback shift register, ASIC chip, scan-path testing, external IC tester, simulation, fault coverage, shift registers, pattern generator, multiple seed
25	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
25	Hans-Joachim Wunderlich, Gundolf Kiefer	Bit-flipping BIST.	ICCAD	1996	DBLP DOI BibTeX RDF	mixed-model BIST
24	Dilip K. Bhavsar	Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester.	VTS	2001	DBLP DOI BibTeX RDF
24	Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen	Cost-free scan: a low-overhead scan path design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
24	Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen	Cost-free scan: a low-overhead scan path design methodology.	ICCAD	1995	DBLP DOI BibTeX RDF	Testing, DFT, Scan design
23	Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi	A Selective Trigger Scan Architecture for VLSI Testing.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Delay Testing, Test Compression, Test Application Time, Scan Test, Test Data Volume, Test Power
23	David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre	A secure scan design methodology.	DATE	2006	DBLP DOI BibTeX RDF
23	Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng	Logic BIST with Scan Chain Segmentation.	ITC	2004	DBLP DOI BibTeX RDF
22	Slavisa Jovanovic, Camel Tanougast, Serge Weber	A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems.	AHS	2007	DBLP DOI BibTeX RDF
20	Stefan R. Meier, Mario Steinert, Steffen Buch	Testability of path history memories with register-exchange architecture used in Viterbi-decoders.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
20	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Gated Clock Scheme for Low Power Scan-Based BIST.	IOLTW	2001	DBLP DOI BibTeX RDF
20	Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe	Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique.	DATE	1998	DBLP DOI BibTeX RDF	Scan chain selection, RT and gate levels, Partial scan, Synthesis for testability
20	Hans-Joachim Wunderlich, Sybille Hellebrand	The pseudoexhaustive test of sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
20	Lea Schubart	Analysis of the Scan Path Using Online Newspapers - Path Comparison Between User and Expert.	ISI	2015	DBLP DOI BibTeX RDF
18	Anthony Martinet, Jean Martinet, Nacim Ihaddadene, Stanislas Lew, Chabane Djeraba	Analyzing eye fixations and gaze orientations on films and pictures.	ACM Multimedia	2008	DBLP DOI BibTeX RDF	user, eye gaze, dispersion, film, scan path, picture, eye fixation
18	Rameshsharma Ramloll, Cheryl Trepagnier, Marc M. Sebrechts, Jaishree Beedasy	Gaze Data Visualization Tools: Opportunities and Challenge.	IV	2004	DBLP DOI BibTeX RDF	gaze data, in-context visualization and nets, animation, direct manipulation, sonification, visualization tools, saccade, scan-path, fixation
18	Jeffrey B. Mulligan	A software-based eye tracking system for the study of air-traffic displays.	ETRA	2002	DBLP DOI BibTeX RDF	Head and eye tracking, air traffic displays, scan-path analysis, image registration
18	Vladimir Castro Alves, A. Ribeiro Antunes, Meryem Marzouki	A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	high-level synthesis for testability, systematic flexible synthesis, testability methodology, industrial tools, pragmatic synthesis, AMICAL synthesis, programmable test pattern generation, BUS-based circuit, embedded test paths, high level synthesis, design for testability, BIST, automatic generation, data path, scan path
18	Slawomir Pilarski, André Ivanov, Tiko Kameda	On minimizing aliasing in scan-based compaction.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	built-in self-test, linear feedback shift register, signature analysis, Aliasing probability, scan path, test response compaction
18	J. H. Dick, Erwin Trischler, Chryssa Dislis, Anthony P. Ambler	Sensitivity analysis in economics based test strategy planning.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Costing parameters, sensitivity analysis, Monte Carlo method, scan path
18	Jacob Savir, Robert F. Berry	AC strength of a pattern generator.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	AC test, level sensitive scan design, test pattern generator, scan path
18	Rajesh Gupta 0003, Rajiv Gupta 0002, Melvin A. Breuer	The BALLAST Methodology for Structured Partial Scan Design.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	scan path storage elements, Ballast methodology, structured partial scan design, balanced structure scant test, testability properties, combinatorial automatic test pattern generation, logic testing, sequential circuits, automatic testing, combinatorial circuits
18	Donald T. Tang, Lin S. Woo	Exhaustive Test Pattern Generation with Constant Weight Vectors.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	fault testing, multilevel logic, logic testing, test pattern generation, self-testing, VLSI testing, scan path, Constant weight codes, exhaustive testing
18	Thomas W. Williams, Kenneth P. Parker	Design for Testability - A Survey.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	Built-In Logic Block Observation (BILBO), Level Sensitive Scan Design (LSSD), Random Access Scan, Scan/Set Logic, testing, test generation, self test, Signature Analysis, Scan Path
18	David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre	Securing Scan Control in Crypto Chips.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Crypto-chips, Security, Scan
18	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Gated Clock Scheme for Low Power Testing of Logic Cores.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	test-per-scan, test-per-clock, low power design, low power test
18	Michael Nicolaidis, Yervant Zorian	Scaling Deeper to Submicron: On-Line Testing to the Rescue.	DATE	1999	DBLP DOI BibTeX RDF
15	Philipp J. Stolka, Michel Waringo, Dominik Henrich, Steffen H. Tretbar, Philipp A. Federspil	Robot-Based 3D Ultrasound Scanning and Registration with Infrared Navigation Support.	ICRA	2007	DBLP DOI BibTeX RDF
15	Sang-Woo Ban, Minho Lee 0001	Novelty Analysis in Dynamic Scene for Autonomous Mental Development.	ICANN (1)	2005	DBLP DOI BibTeX RDF
15	Sang-Bok Choi, Sang-Woo Ban, Minho Lee 0001	Human-Like Selective Attention Model with Reinforcement and Inhibition Mechanism.	ICONIP	2004	DBLP DOI BibTeX RDF
15	Dara Koozekanani, Kim L. Boyer, Cynthia Roberts, Steven Katz	Tracking the Optic Nerve Head in OCT Video Using Dual Eigenspaces and an Adaptive Vascular Distribution Model.	CVPR (1)	2001	DBLP DOI BibTeX RDF
15	Andrzej Krasniewski, Slawomir Pilarski	Circular Self-Test Path: A Low-Cost BIST Technique.	DAC	1987	DBLP DOI BibTeX RDF
15	Ayan Palchaudhuri, Digvijay Anand, Anindya Sundar Dhar	FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion.	J. Parallel Distributed Comput.	2022	DBLP DOI BibTeX RDF
15	Wolfgang Fuhl	HPCGen: Hierarchical K-Means Clustering and Level Based Principal Components for Scan Path Genaration.	CoRR	2022	DBLP BibTeX RDF
15	Wolfgang Fuhl, Enkelejda Kasneci	HPCGen: Hierarchical K-Means Clustering and Level Based Principal Components for Scan Path Genaration.	ETRA	2022	DBLP DOI BibTeX RDF
15	Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar	Design Automation for Tree-based Nearest Neighborhood-aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion.	ACM Trans. Design Autom. Electr. Syst.	2021	DBLP DOI BibTeX RDF
15	Srikrishnaraja Mahadas, Courtney Semkewyc, Shradha Suresh, George K. Hung	Scan path during change-detection visual search.	Comput. Biol. Medicine	2021	DBLP DOI BibTeX RDF
15	Abderrezzaq Sendjasni, Mohamed-Chaker Larabi, Faouzi Alaya Cheikh	Perceptually-Weighted Cnn For 360-Degree Image Quality Assessment Using Visual Scan-Path And Jnd.	ICIP	2021	DBLP DOI BibTeX RDF
15	Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar	Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion.	FPGA	2020	DBLP DOI BibTeX RDF
15	Suiyi Ling, Jesús Gutiérrez 0001, Ke Gu 0001, Patrick Le Callet	Prediction of the Influence of Navigation Scan-Path on Perceived Quality of Free-Viewpoint Videos.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2019	DBLP DOI BibTeX RDF
15	Yang Zhang 0033, Kai Tang 0001	Automatic Sweep Scan Path Planning for Five-Axis Free-Form Surface Inspection Based on Hybrid Swept Area Potential Field.	IEEE Trans Autom. Sci. Eng.	2019	DBLP DOI BibTeX RDF
15	Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue	An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis.	ITC-Asia	2019	DBLP DOI BibTeX RDF
15	Hsien Chih Chuang, Da Lun Tang	Reconfirm gestalt principles from scan-path analysis on viewing photos.	ISPACS	2019	DBLP DOI BibTeX RDF
15	Suiyi Ling, Jesús Gutiérrez 0001, Ke Gu 0001, Patrick Le Callet	Prediction of the Influence of Navigation Scan-path on Perceived Quality of Free-Viewpoint Videos.	CoRR	2018	DBLP BibTeX RDF
15	Wan-Ting Sun, Feng-Ru Sheu, Meng-Jung Tsai	Understanding Inquiry-Based Searching Behaviors Using Scan Path Analysis: A Pilot Study.	ICITL	2018	DBLP DOI BibTeX RDF
15	Li-Ming Zhao, Xin-Wei Li, Wei-Long Zheng, Bao-Liang Lu	Active Feedback Framework with Scan-Path Clustering for Deep Affective Models.	ICONIP (2)	2018	DBLP DOI BibTeX RDF
15	Marc Assens, Kevin McGuinness, Xavier Giró-i-Nieto, Noel E. O'Connor	SaltiNet: Scan-path Prediction on 360 Degree Images using Saliency Volumes.	CoRR	2017	DBLP BibTeX RDF
15	Pawel Kasprowski, Katarzyna Harezlak, Pawel Fudalej, Piotr Fudalej	Examining the Impact of Dental Imperfections on Scan-Path Patterns.	KES-IDT (2)	2017	DBLP DOI BibTeX RDF
15	Frode Eika Sandnes, Fausto Orsi Medola	Effects of Optimizing the Scan-Path on Scanning Keyboards with QWERTY-Layout for English Text.	AAATE Conf.	2017	DBLP DOI BibTeX RDF
15	Marc Assens, Xavier Giró-i-Nieto, Kevin McGuinness, Noel E. O'Connor	SaltiNet: Scan-Path Prediction on 360 Degree Images Using Saliency Volumes.	ICCV Workshops	2017	DBLP DOI BibTeX RDF
15	Zi Zhou, Yang Zhang 0033, Kai Tang 0001	Sweep scan path planning for efficient freeform surface inspection on five-axis CMM.	Comput. Aided Des.	2016	DBLP DOI BibTeX RDF
15	Pallavi Raiturkar, Andrew Lee, Eakta Jain	Scan path and movie trailers for implicit annotation of videos.	SAP	2016	DBLP DOI BibTeX RDF
15	Junghwan Kim, Young-Woo Lee, Minho Cheong, Sungyoul Seo, Sungho Kang	A test methodology to screen scan-path failures.	ISOCC	2016	DBLP DOI BibTeX RDF
15	Arash Ashrafi, Ramachandran Vaidyanathan	An Architecture for Configuring an Effcient Scan Path for a Subset of Elements.	IPDPS Workshops	2015	DBLP DOI BibTeX RDF
15	Suleyman Al-Showarah, Naseer Al-Jawad, Harin Sellahewa	Effects of User Age on Smartphone and Tablet Use, Measured with an Eye-Tracker via Fixation Duration, Scan-Path Duration, and Saccades Proportion.	HCI (5)	2014	DBLP DOI BibTeX RDF
15	Bowen Wu, Qiangzhi Zhang, Pengfei Ye, Qinghua Huang	A Kinect-based scan path planning method for ultrasound imaging.	BMEI	2014	DBLP DOI BibTeX RDF
15	Lijuan Duan, Zeming Zhao, Wei Ma, Jili Gu, Zhen Yang 0004, Yuanhua Qiao	A combined model for scan path in pedestrian searching.	IJCNN	2014	DBLP DOI BibTeX RDF
15	Michael Raschke, Dominik Herr, Tanja Blascheck, Thomas Ertl, Michael Burch, Sven Willmann, Michael Schrauf	A visual approach for scan path comparison.	ETRA	2014	DBLP DOI BibTeX RDF
15	Michael Raschke, Dominik Herr, Tanja Blascheck, Thomas Ertl, Michael Burch, Sven Willmann, Michael Schrauf	A visual approach for scan path comparison.	ETRA	2014	DBLP DOI BibTeX RDF
15	Yuto Goto, Hironobu Fujiyoshi	Recovering 3-D gaze scan path and scene structure from inside-out camera.	AH	2013	DBLP DOI BibTeX RDF
15	Salvador Manich, Markus S. Wamser, Oscar M. Guillen, Georg Sigl	Differential scan-path: A novel solution for secure design-for-testability.	ITC	2013	DBLP DOI BibTeX RDF
15	Haruhiko Takeuchi, Noriyuki Matsuda	Scan-path analysis by the string-edit method considering fixation duration.	SCIS&ISIS	2012	DBLP DOI BibTeX RDF
15	Michael Raschke, Xuemei Chen, Thomas Ertl	Parallel scan-path visualization.	ETRA	2012	DBLP DOI BibTeX RDF