Search results for "subthreshold"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
127	Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang	Design and analysis of ultra-thin-body SOI based subthreshold SRAM.	ISLPED	2009	DBLP DOI BibTeX RDF	poisson's equation, subthreshold SRAM, ultra-thin-body, soi, static noise margin
106	Bo Zhai, Scott Hanson, David T. Blaauw, Dennis Sylvester	Analysis and mitigation of variability in subthreshold design.	ISLPED	2005	DBLP DOI BibTeX RDF	max of lognormal RVs, subthreshold variability
96	Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay	Slew-aware clock tree design for reliable subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	slew, clocks, subthreshold
86	Sumanth Amarchinta, Dhireesha Kudithipudi	Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	charge-boosters, subthreshold design, biasing
83	Tony Tae-Hyoung Kim, Hanyong Eom, John Keane 0001, Chris H. Kim	Utilizing reverse short channel effect for optimal subthreshold circuit design.	ISLPED	2006	DBLP DOI BibTeX RDF	PVT variations, reverse short channel effect, optimization, digital circuits, subthreshold circuits, subthreshold operation
83	Benton H. Calhoun, Anantha P. Chandrakasan	Characterizing and modeling minimum energy operation for subthreshold circuits.	ISLPED	2004	DBLP DOI BibTeX RDF	minimum energy point, subthreshold model, energy model, subthreshold circuits
80	John Keane 0001, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim	Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing.	DAC	2006	DBLP DOI BibTeX RDF	subthreshold logic, ultra-low power design, logical effort
78	David T. Blaauw, Bo Zhai	Energy efficient design for subthreshold supply voltage operation.	ISCAS	2006	DBLP DOI BibTeX RDF
78	Hendrawan Soeleman, Kaushik Roy 0001, Bipul Chandra Paul	Robust subthreshold logic for ultra-low power operation.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
75	Biswajit Mishra, Bashir M. Al-Hashimi	Subthreshold FIR Filter Architecture for Ultra Low Power Applications.	PATMOS	2008	DBLP DOI BibTeX RDF	Subthreshold design, Minimum Energy Point, Ultra Low Power Design, Leakage, FIR
75	Songqing Zhang, Vineet Wason, Kaustav Banerjee	A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations.	ISLPED	2004	DBLP DOI BibTeX RDF	die-to-die variations, electrothermal couplings, subthreshold leakage power distribution, yield estimation, process variations, within-die variations
67	Rodrigo Jaramillo-Ramirez, Javid Jaffari, Mohab Anis	Variability-aware design of subthreshold devices.	ISCAS	2008	DBLP DOI BibTeX RDF
65	Scott Hanson, Bo Zhai, David T. Blaauw, Dennis Sylvester, Andres Bryant, Xinlin Wang	Energy optimality and variability in subthreshold design.	ISLPED	2006	DBLP DOI BibTeX RDF	ultra-low energy, variability, subthreshold circuits
65	Jabulani Nyathi, Brent Bero	Logic circuits operating in subthreshold voltages.	ISLPED	2006	DBLP DOI BibTeX RDF	logic styles, medium-to-high speed, off current, ultra-low power, noise margins, subthreshold, body biasing
62	Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy 0001	Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
57	Belén Sancristóbal, José M. Sancho, Jordi García-Ojalvo	Resonant Spike Propagation in Coupled Neurons with Subthreshold Activity.	ICANN (2)	2008	DBLP DOI BibTeX RDF
57	Vahid Moalemi, Ali Afzali-Kusha	Subthreshold Pass Transistor Logic for Ultra-Low Power Operation.	ISVLSI	2007	DBLP DOI BibTeX RDF
57	Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy 0001	A Feasibility Study of Subthreshold SRAM Across Technology Generations.	ICCD	2005	DBLP DOI BibTeX RDF
57	L. Darrell Whitley, Keith Bush, Jonathan E. Rowe	Subthreshold-Seeking Behavior and Robust Local Search.	GECCO (2)	2004	DBLP DOI BibTeX RDF
57	Volkan Kursun, Eby G. Friedman	Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits.	ISQED	2004	DBLP DOI BibTeX RDF
57	Ming-Jer Chen, Jib-Shin Ho	A three-parameters-only MOSFET subthreshold current CAD model considering back-gate bias and process variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
54	David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat	Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic.	ISLPED	2009	DBLP DOI BibTeX RDF	short-channel effects, subthreshold logic, variability, cmos digital integrated circuits, ultra-low power, gate leakage
54	Lei Zhang 0033, Zhiping Yu, Xiangqing He	A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current Mirrors.	ISQED	2008	DBLP DOI BibTeX RDF	CMOS Process Fluctuations, Subthreshold Current Mirror, Discrete Martingale, Probability, Random Variable
54	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm
52	Stefan Reinker, Ernest Puil, Robert M. Miura	Membrane Resonance and Stochastic Resonance Modulate Firing Patterns of Thalamocortical Neurons.	J. Comput. Neurosci.	2004	DBLP DOI BibTeX RDF	membrane resonance, thalamic neurons, noise, stochastic resonance, neuron model
52	Chris Hyung-Il Kim, Hendrawan Soeleman, Kaushik Roy 0001	Ultra-low-power DLMS adaptive filter for hearing aid applications.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
49	Bo Zhai, Ronald G. Dreslinski, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester	Energy efficient near-threshold chip multi-processing.	ISLPED	2007	DBLP DOI BibTeX RDF	near-threshold, energy efficient, CMP, subthreshold
49	Zhiyu Liu, Volkan Kursun	Leakage current starved domino logic.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, sleep mode, domino logic, subthreshold leakage current, dual threshold voltage
47	John Keane 0001, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim	Stack Sizing for Optimal Current Drivability in Subthreshold Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
47	Håvard Pedersen Alstad, Snorre Aunet	Improving Circuit Security against Power Analysis Attacks with Subthreshold Operation.	DDECS	2008	DBLP DOI BibTeX RDF
47	Tony Tae-Hyoung Kim, John Keane 0001, Hanyong Eom, Chris H. Kim	Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
47	Mingoo Seok, Scott Hanson, Dennis Sylvester, David T. Blaauw	Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design.	DAC	2007	DBLP DOI BibTeX RDF
47	Scott Hanson, Mingoo Seok, Dennis Sylvester, David T. Blaauw	Nanometer Device Scaling in Subthreshold Circuits.	DAC	2007	DBLP DOI BibTeX RDF
47	Horacio G. Rotstein, Tim Oppermann, John A. White, Nancy Kopell	The dynamic structure underlying subthreshold oscillatory activity and the onset of spikes in a model of medial entorhinal cortex stellate cells.	J. Comput. Neurosci.	2006	DBLP DOI BibTeX RDF	Reduction of dimensions, Canard, Generalized integrate-and-fire models, Theta rhythm, Hopf bifurcation
47	Walid Elgharbawy, Pradeep Golconda, Ashok Kumar 0001, Magdy A. Bayoumi	A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
47	Bhavana Jharia, Sankar Sarkar, Rajendra Prasad Agarwal	Analytical Study of Impact Ionization and Subthreshold Current in Submicron n-MOSFET.	ISQED	2005	DBLP DOI BibTeX RDF
47	Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David T. Blaauw	Energy Optimization of Subthreshold-Voltage Sensor Network Processors.	ISCA	2005	DBLP DOI BibTeX RDF
47	James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan	Subthreshold leakage modeling and reduction techniques.	ICCAD	2002	DBLP DOI BibTeX RDF
47	Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Andreas G. Andreou	A general subthreshold MOS translinear theorem.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
44	David Bol, Denis Flandre, Jean-Didier Legat	Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	adaptive circuits, subthreshold logic, variability, CMOS digital integrated circuits, ultra-low power
44	Michael B. Henry, Syed Imtiaz Haider, Leyla Nazhandali	A low-power parallel design of discrete wavelet transform using subthreshold voltage technology.	CASES	2008	DBLP DOI BibTeX RDF	low power, parallel, wavelet, subthreshold
44	Yuto Nakamura, Kazuhiro Tsuboi, Osamu Hoshino	Lateral Excitation between Dissimilar Orientation Columns for Ongoing Subthreshold Membrane Oscillations in Primary Visual Cortex.	ICANN (2)	2008	DBLP DOI BibTeX RDF	Lateral excitation, Feature binding, Orientation map, Ongoing subthreshold membrane oscillation, Neural network model, Primary visual cortex
44	Luiz Alberto Pasini Melek, Márcio C. Schneider, Carlos Galup-Montoro	Body-bias compensation technique for SubThreshold CMOS static logic gates.	SBCCI	2004	DBLP DOI BibTeX RDF	body-bias compensation, static logic, low-power, CMOS, logic circuits, subthreshold
42	Julie S. Haas, Alan D. Dorval II, John A. White	Contributions of I h to feature selectivity in layer II stellate cells of the entorhinal cortex.	J. Comput. Neurosci.	2007	DBLP DOI BibTeX RDF	Inward rectifier, Spike-triggered covariance, Single-neuron computation, Reliability, Principal component analysis, Information theory
42	Myeong-Eun Hwang, Tamer Cakici, Kaushik Roy 0001	Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling.	DATE	2007	DBLP DOI BibTeX RDF
42	Cristina Masoller, M. C. Torrent, Jordi García-Ojalvo	Neuronal Multistability Induced by Delay.	ICANN (1)	2007	DBLP DOI BibTeX RDF
42	Liam Paninski	The most likely voltage path and large deviations approximations for integrate-and-fire neurons.	J. Comput. Neurosci.	2006	DBLP DOI BibTeX RDF	Stochastic dynamics, Freidlin-Wentzell, Intracellular recordings, Calculus of variations, Likelihood
42	Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner	Theoretical and practical limits of dynamic voltage scaling.	DAC	2004	DBLP DOI BibTeX RDF	minimum energy point, dynamic voltage scaling
42	Xinghai Tang, Vivek De, James D. Meindl	Intrinsic MOSFET parameter fluctuations due to random dopant placement.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
39	Yu-Shiang Lin, Dennis Sylvester	Runtime leakage power estimation technique for combinational circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	subthreshold leakage analysis, runtime leakage power estimation technique, dynamic estimation methods, static estimation methods, combinational circuits, error estimation, SPICE simulations
39	Zhiyu Liu, Volkan Kursun	Leakage Biased Sleep Switch Domino Logic.	ISQED	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, sleep mode, Domino logic, subthreshold leakage current, dual threshold voltage
39	Amir Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz	Leakage current reduction by new technique in standby mode.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	subthreshold current, low power, leakage current, digital integrated circuits, static power
39	Kiyoo Itoh 0001	Low-voltage memories for power-aware systems.	ISLPED	2002	DBLP DOI BibTeX RDF	DRAM and SRAM cells, gain cells, gate-source/substrate-source back-biasing, memory-rich architectures, multi-Vr, non-volatile RAMs, on-chip voltage converters, peripheral circuits, subthreshold current, testing
36	Jeremy R. Tolbert, Saibal Mukhopadhyay	Accurate buffer modeling with slew propagation in subthreshold circuits.	ISQED	2009	DBLP DOI BibTeX RDF
36	Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Ali Peiravi, Snorre Aunet, Tuan Vu Cao	New subthreshold concepts in 65nm CMOS technology.	ISQED	2009	DBLP DOI BibTeX RDF
36	Michael B. Henry, Leyla Nazhandali	Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture.	HiPEAC	2009	DBLP DOI BibTeX RDF
36	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
36	Vahid Moalemi, Ali Afzali-Kusha	Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies.	ISVLSI	2007	DBLP DOI BibTeX RDF
36	Niklas Lotze, Maurits Ortmanns, Yiannos Manoli	A Study on self-timed asynchronous subthreshold logic.	ICCD	2007	DBLP DOI BibTeX RDF
36	Jinhui Chen, Lawrence T. Clark, Yu Cao	Robust Design of High Fan-In/Out Subthreshold Circuits.	ICCD	2005	DBLP DOI BibTeX RDF
36	Keng Hoong Wee, Ji-Jon Sit, Rahul Sarpeshkar	Biasing techniques for subthreshold MOS resistive grids.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
36	Hongchin Lin, Chao-Jui Liang	A sub-1V bandgap reference circuit using subthreshold current.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
36	Walid Elgharbawy, Magdy A. Bayoumi	New Bulk Dynamic Threshold NMOS Schemes for Low-Energy Subthreshold Domino-Like Circui.	ISVLSI	2004	DBLP DOI BibTeX RDF
36	Nazareth P. Castellanos, Francisco de Borja Rodríguez Ortiz, Pablo Varona	Stochastic Networks with Subthreshold Oscillations and Spiking Activity.	IWANN (1)	2003	DBLP DOI BibTeX RDF
36	Alice Wang, Anantha P. Chandrakasan, Stephen V. Kosonocky	Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits.	ISVLSI	2002	DBLP DOI BibTeX RDF
36	Dingming Xie, Mengzhang Cheng, Leonard Forbes	SPICE models for flicker noise in n-MOSFETs from subthreshold tostrong inversion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
34	Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	body bias clustering, performance compensation, layout, manufacturing variability, subthreshold circuits
34	Kristian Granhaug, Snorre Aunet	Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Subthreshold CMOS, Output-wired redundancy, Yield and defect tolerance
34	Hendrawan Soeleman, Kaushik Roy 0001	Ultra-low power digital subthreshold logic circuits.	ISLPED	1999	DBLP DOI BibTeX RDF	ultra-low power, digital logic, subthreshold circuits
31	Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy 0001	Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
31	Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner	The limit of dynamic voltage scaling and insomniac dynamic voltage scaling.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
31	Nam Sung Kim, David T. Blaauw, Trevor N. Mudge	Quantitative analysis and optimization techniques for on-chip cache leakage power.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
31	Le Yan, Jiong Luo, Niraj K. Jha	Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
31	José Antonio Villacorta-Atienza, Fivos Panetsos	Information coding by ensembles of resonant neurons.	Biol. Cybern.	2005	DBLP DOI BibTeX RDF
31	Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie 0001, Wenping Wang	Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits.	VLSI Design	2005	DBLP DOI BibTeX RDF
31	Márta Rencz, Vladimír Székely, S. Török, Kholdoun Torki, Bernard Courtois	IDDQ Testing of Submicron CMOS - by Cooling?	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	submicron, cooling, I DDQ testing
31	Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl	CMOS system-on-a-chip voltage scaling beyond 50nm.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
31	Rupert Howes, William Redman-White, Ken G. Nichols, Peter J. Mole, Michael J. Robinson, Simon Bird	An SOS MOSFET model based on calculation of the surface potential.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
31	W. W. Wong, Juin J. Liou	JFET circuit simulation using SPICE implemented with an improved model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
31	Hiroyoshi Tanimoto, Naoyuki Shigyo	Discretization error in MOSFET device simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
31	David M. Lewis	Device model approximation using 2N trees.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
31	Te-Kuang Chiang	Nanosheet FET: A new subthreshold current model caused by interface-trapped-charge and its application for evaluation of subthreshold logic gate.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
31	Arun Kumar, P. S. T. N. Srinivas, Pramod Kumar Tiwari	Analytical Modeling of Subthreshold Current and Subthreshold Swing of Schottky-Barrier Source/Drain Double Gate-All-Around (DGAA) MOSFETs.	iSES	2019	DBLP DOI BibTeX RDF
31	Ramesh Vaddi, R. P. Agarwal, Sudeb Dasgupta	Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
31	Idan Segev	התנהגות פוטנציאלים תת-סיפיים בתא עצב בעל ממברנה אילינארית (The behavior of Subthreshold potentials in a neuron with a nonlinear membrane.; The behavior of subthreshold potentials in a neuron with a nonlinear membrane.).		1982	RDF
29	Hamed F. Dadgour, Muhammad Mustafa Hussain, Casey Smith, Kaustav Banerjee	Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS.	DAC	2010	DBLP DOI BibTeX RDF	energy-efficient electronics, laterally-actuated NEMS, nano-electro-mechanical switches, steep-subthreshold switch, logic design, process variation
29	Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park	Leakage Minimization Technique for Nanoscale CMOS VLSI.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	nanometer CMOS, cell characterization, gate-tunneling current, input pattern generation, leakage power, subthreshold leakage current
29	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process
29	Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy 0001	Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.	ISLPED	2007	DBLP DOI BibTeX RDF	signal slope, interconnect, gate delay, subthreshold operation
29	T. M. Mak, Sani R. Nassif	Guest Editors' Introduction: Process Variation and Stochastic Design and Test.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	silicon manufacturing processes, adaptive circuits, process variation, process monitoring, subthreshold leakage
29	Scott Hanson, Dennis Sylvester, David T. Blaauw	A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	voltage scaling, gate sizing, subthreshold circuits
29	Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud	An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, low power circuit design, subthreshold leakage, dual threshold voltage
29	Walid Elgharbawy, Pradeep Golconda, Magdy A. Bayoumi	Noise-tolerant high fan-in dynamic CMOS circuit design.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	high fan-in domino, CMOS, noise-tolerant, subthreshold leakage, dynamic circuits
29	Paul Beckett	Low-power circuits using dynamic threshold devices.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	silicide, thin-body, CMOS, nanotechnology, SOI, subthreshold leakage, double-gate
29	Saibal Mukhopadhyay, Kaushik Roy 0001	Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation.	ISLPED	2003	DBLP DOI BibTeX RDF	band-to-band tunneling, variability, Monte Carlo, threshold voltage, gate leakage, subthreshold leakage
29	David Scott, Shaoping Tang, Song Zhao, Mahalingam Nandakumar	Device Physics Impact on Low Leakage, High Speed DSP Design Techniques (invited).	ISQED	2002	DBLP DOI BibTeX RDF	standby, GIDL, leakage, tunneling, subthreshold, current
29	Claude Thibeault	A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures.	VTS	1997	DBLP DOI BibTeX RDF	IC diagnosis, probabilistic differential quiescent current signature, noise source, embedded logic, robustness, maximum likelihood estimation, maximum likelihood estimation, IDDQ testing, subthreshold leakage current
29	Andreas G. Andreou, Kwabena A. Boahen	A 590, 000 transistor 48, 000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retina.	ARVLSI	1995	DBLP DOI BibTeX RDF	silicon retina, analog VLSI focal plane processor, phototransduction, local gain control, single chip system, vertebrate distal retina, ultra low power dissipation, n-well double metal double poly digital oriented CMOS technology, current-mode subthreshold CMOS, 48000 pixel, computer vision, VLSI, edge detection, CMOS integrated circuits, image sensors, contrast, edge enhancement, CMOS imager, focal planes, area efficiency, 1.2 micron
26	Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky	Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	CMOS logic devices, reliability, Markov process, monte carlo method, poisson distribution, laplace transform
26	Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya	A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs.	ASP-DAC	2009	DBLP DOI BibTeX RDF