Search results for "yield"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
90	Allan Y. Wong	A Statistical Approach To Identify Semiconductor Process Equipment Related Yield Problems.	DFT	1997	DBLP DOI BibTeX RDF	Systematic yield, Random yield, process equipment defect density, Statistical techniques, Yield analysis
82	Qing Su, Charles C. Chiang, Jamil Kawa	Hotspot Based Yield Prediction with Consideration of Correlations.	ISQED	2008	DBLP DOI BibTeX RDF	Systematic Yield, DFM (design for manufacturing), correlation, Yield, Hotspot, Yield Prediction
71	Subarna Sinha, Charles C. Chiang	A methodology for fast and accurate yield factor estimation during global routing.	ICCAD	2007	DBLP DOI BibTeX RDF
67	Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya, Yuzi Kanazawa	Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances.	DAC	2010	DBLP DOI BibTeX RDF	analog/mixed-signal, optimization, yield, Pareto-front
62	Stuart L. Riley	Limitations to Estimating Yield Based on In-Line Defect Measurements.	DFT	1999	DBLP DOI BibTeX RDF	Defect-limited yield, Yield estimation, In-line defect measurements, Kill ratio estimation, Defect review sampling, Defect classification, Yield prediction
61	M. Zhang, M. Z. Li, Gang Liu, M. H. Wang	Yield Mapping in Precision Farming.	CCTA	2007	DBLP DOI BibTeX RDF	yield monitor system, grain flow sensor, yield map, precision agriculture
61	Athanasios T. Markinos, Theofanis A. Gemtos, D. Pateras, L. Toulios, G. Zerva, M. Papaeconomou	The influence of cotton variety in the calibration factor of a cotton yield monitor.	Oper. Res.	2005	DBLP DOI BibTeX RDF	cotton, yield mapping, yield monitor, calibration, varieties
61	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko	Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA redundancy, interconnect faults, fault tolerance, yield enhancement, interconnect model, yield prediction, catastrophic faults, FPGA interconnect
60	Akhil Garg 0001, Prashant Dubey	Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost.	DFT	2006	DBLP DOI BibTeX RDF	Compression and Yield, Memory, Repair, Fuse
55	Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown	Parametric Yield Analysis and Optimization in Leakage Dominated Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
55	Rajnish K. Prasad, Israel Koren	The Effect of Placement on Yield for Standard Cell Designs.	DFT	2000	DBLP DOI BibTeX RDF
49	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko	Yield enhancements of design-specific FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	design-specific FPGA, interconnect faults, interconnect utilization, yield enhancement, yield prediction, structured ASIC, FPGA interconnect
49	Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov	Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	Timing specifications testing, Test Environment, Tester OTA and yield, High-speed interconnect testing, Yield analysis
49	Tom Thomas, Brian W. Anthony	Area, Performance, and Yield Implications of Redundancy in On-Chip Caches.	ICCD	1999	DBLP DOI BibTeX RDF	cache, redundancy, microprocessor, yield, SRAM, yield enhancement, microprocessor design, embedded SRAM
48	Jianfeng Luo, Subarna Sinha, Qing Su, Jamil Kawa, Charles C. Chiang	An IC manufacturing yield model considering intra-die variations.	DAC	2006	DBLP DOI BibTeX RDF	random variation, systematic variation, CMP, spatial correlation, manufacturing yield
47	Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp	DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.	DATE	2006	DBLP DOI BibTeX RDF
47	Xiaohong Jiang 0001, Susumu Horiguchi, Yue Hao	Predicting the Yield Efficacy of a Defect-Tolerant Embedded Core.	DFT	2000	DBLP DOI BibTeX RDF
44	Fang Gong, Hao Yu 0001, Yiyu Shi 0001, Daesoo Kim, Junyan Ren, Lei He 0001	QuickYield: an efficient global-search based parametric yield estimation with performance constraints.	DAC	2010	DBLP DOI BibTeX RDF	circuit simulation, parametric yield
44	Parijat Dube, Yezekael Hayel	A Real-Time Yield Management Framework for E-Services.	CEC/EEE	2006	DBLP DOI BibTeX RDF	discrete choice model, expected delay, price-delay tradeoff, optimization, queueing theory, Yield management
44	Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Stephen W. Director	Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance.	DAC	2005	DBLP DOI BibTeX RDF	correlation, variability, yield, leakage
44	Fred J. Meyer, Nohpill Park	Predicting Defect-Tolerant Yield in the Embedded Core Context.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Yield, integrated circuit, defect tolerance, embedded core
44	Pascal Bichebois, Pierre Mathery	Analysis of Defect to Yield Correlation on Memories: Method, Algorithms and Limits.	DFT	1997	DBLP DOI BibTeX RDF	algorithm, tool, correlation, method, errors, inspection, yield, failure, defect, limits
44	Hans T. Heineken, Wojciech Maly	Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs.	ICCAD	1996	DBLP DOI BibTeX RDF	Standard Cell Designs, Synthesis, Interconnects, Manufacturability, Yield
43	Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David T. Blaauw	A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
43	Martin D. F. Wong	Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers.	ICCD	2004	DBLP DOI BibTeX RDF
43	Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu	Failure Factor Based Yield Enhancement for SRAM Designs.	DFT	2004	DBLP DOI BibTeX RDF
43	Bing Qiu 0003, Yvon Savaria, Meng Lu, Chunyan Wang 0004, Claude Thibeault	Yield Modeling of a WSI Telecom Router Architecture.	DFT	2002	DBLP DOI BibTeX RDF
43	Arunshankar Venkataraman, Israel Koren	Determination of Yield Bounds Prior to Routing.	DFT	1999	DBLP DOI BibTeX RDF
41	Sandra Levasseur, Frederic Duvivier	Application of a yield model merging critical areas and defectivity to industrial products.	DFT	1997	DBLP DOI BibTeX RDF	industrial products, survey sampling based estimation tool, fabrication process, SGS-Thomson Crolles plant, multiple products, process versions, 0.5 micron, robustness, defectivity, EYES, critical areas, yield model, integrated circuit yield
40	Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu	Behavior-level yield enhancement approach for large-scaled analog circuits.	DAC	2010	DBLP DOI BibTeX RDF	process variation, analog circuits, yield enhancement
40	Costas Argyrides, Giorgos Dimosthenous, Dhiraj K. Pradhan, Carlos Arthur Lang Lisbôa, Luigi Carro	Reliability aware yield improvement technique for nanotechnology based circuits.	SBCCI	2009	DBLP DOI BibTeX RDF	reliability, nanotechnology, yield improvement
40	Cesare Ferri, Sherief Reda, R. Iris Bahar	Parametric yield management for 3D ICs: Models and strategies for improvement.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	performance, process variations, leakage, 3D integration, yield management
40	Sachin S. Sapatnekar	Building your yield of dreams.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	nanoscale, modeling variations, CMOS, yield, design for manufacturability, DFM
40	Love Singhal, Sejong Oh, Eli Bozorgzadeh	Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	configuration selection, delay budgeting, process variation, task allocation, within-die variation, timing yield
40	Antonis Papanikolaou, T. Grabner, Miguel Miranda, Philippe Roussel, Francky Catthoor	Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	system exploration, process variability, parametric yield
40	Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar	Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration.	DAC	2006	DBLP DOI BibTeX RDF	pareto surfaces, performance space, optimization, yield
40	Azharul Karim, Saman K. Halgamuge, A. J. R. Smith, Arthur L. Hsu	Manufacturing Yield Improvement by Clustering.	ICONIP (3)	2006	DBLP DOI BibTeX RDF	Clustering quality, Filtration of noisy data, Data mining, Self-organising map, Yield improvement
40	Marco Ottavi, Xiaopeng Wang, Fred J. Meyer, Fabrizio Lombardi	Simulation of reconfigurable memory core yield.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	Markov chain, manufacturability, yield, defect tolerance
40	Tianxu Zhao, Yue Hao, Peijun Ma, Taifeng Chen	Relation between Reliability and Yield of IC's Based on Discrete Defect Distribution Model.	DFT	2001	DBLP DOI BibTeX RDF	Distribution of the defect size, Reliability, Yield
40	Israel Koren, Zahava Koren	Incorporating Yield Enhancement into the Floorplanning Process.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	memory ICs, routing complexity, redundancy, microprocessor, Floorplanning, yield
40	Israel Koren	Should Yield be a Design Objective?	ISQED	2000	DBLP DOI BibTeX RDF	routing, floorplanning, yield, compaction, critical area
40	Zhan Chen, Israel Koren	Techniques for Yield Enhancement of VLSI Adders.	ASAP	1995	DBLP DOI BibTeX RDF	VLSI yield, VLSI adder, defect tolerance, VLSI layout
40	Bruno Ciciani	Redundancy effect on yield of binary tree RAMs.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	semiconductor memory design, VLSI chip design, yield evaluation, Fault-tolerant memories
39	Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada	Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
39	Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada	Timing-driven cell layout de-compaction for yield optimization by critical area minimization.	DATE	2006	DBLP DOI BibTeX RDF
39	Azadeh Davoodi, Ankur Srivastava 0001	Variability driven gate sizing for binning yield optimization.	DAC	2006	DBLP DOI BibTeX RDF	speed binning, process variations, gate sizing
39	Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy 0001	A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
39	Zhaojun Wo, Israel Koren, Maciej J. Ciesielski	An ILP Formulation for Yield-driven Architectural Synthesis.	DFT	2005	DBLP DOI BibTeX RDF
39	Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown	Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization.	ISQED	2005	DBLP DOI BibTeX RDF
39	Joseph A. Reynick	Investment vs. Yield Relationship for Memories and IP in SOC.	ITC	2004	DBLP DOI BibTeX RDF
38	Zhaoliang Pan, Melvin A. Breuer	Estimating Error Rate in Defective Logic Using Signature Analysis.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Binning integrated circuits, effective yield, signature testing, error rate, error tolerance, yield loss
38	Shishpal Rawat, Raul Camposano, Andrew B. Kahng, Joseph Sawicki, Mike Gianfagna, Naeem Zafar, Atul Sharan	DFM: where's the proof of value?	DAC	2006	DBLP DOI BibTeX RDF	ROI, DFM, design for manufacture, OPC, RET, yield optimization, design for yield
38	Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei	A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	timing specifications testing, test environment, tester OTA and yield, high-speed interconnect testing, yield analysis
37	Junying Sun, Jinliang Huang, Jing Chen, Lihui Wang	Grain Yield Estimating for Hubei Province Using Remote Sensing Data - Take Semilate Rice as an Example.	ESIAT (1)	2009	DBLP DOI BibTeX RDF	Crop yield, Crop yield estimation models using remote sensing data, Productivity zoning, Hubei province
37	Kees Veelenturf	The Road to Better Reliability and Yield Embedded DfM Tools.	DATE	2000	DBLP DOI BibTeX RDF	wire spreading, yield prediction, yield improvement, DfM
37	Sy-Yen Kuo, W. Kent Fuchs	Fault Diagnosis and Spare Allocation for Yield Enhancement in Large Reconfigurable PLA's.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	reconfigurable PLAs, spare allocation, circuit density, chip size, fault diagnosis algorithm, computational complexity, fault tolerant computing, fault location, programmable logic arrays, multiple faults, logic arrays, yield enhancement, reconfigurable logic, memory structures, circuit reliability, manufacturing yield
37	James C. Harden, Noel R. Strader II	Architectural Yield Optimization for WSI.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	architectural yield optimisation, integrated circuit yield modeling, computing structures, VLSI, fault tolerant computing, computer architecture, redundancy, failure analysis, wafer-scale integration, circuit reliability
36	Lin Huang 0002, Qiang Xu 0001	Performance yield-driven task allocation and scheduling for MPSoCs under process variation.	DAC	2010	DBLP DOI BibTeX RDF	performance yield, process variation, task scheduling
36	Michal Wegiel, Chandra Krintz	Dynamic prediction of collection yield for managed runtimes.	ASPLOS	2009	DBLP DOI BibTeX RDF	reference bits, clustering, parallel, concurrent, operating system, garbage collection, yield prediction
36	Megat Norulazmi Megat Mohamed Noor, Shaidah Jusoh	Visualizing the Yield Pattern Outcome for Automatic Data Exploration.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	Automatic data exploration, manufactuirng yield predictive system, Data mining, machine learning, data visualization, predictive system
36	Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif	Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield.	ISQED	2008	DBLP DOI BibTeX RDF	decoupled design, 8T, 6T, stacked devices, stability, yield, sram, double gate
36	Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao	Dose map and placement co-optimization for timing yield enhancement and leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dose map, placement, timing yield, leakage power reduction
36	Yi Wang, Wai-Shing Luk, Xuan Zeng 0001, Jun Tao 0001, Changhao Yan, Jiarong Tong, Wei Cai 0003, Jia Ni	Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays.	DAC	2008	DBLP DOI BibTeX RDF	non-Gaussian, process variations, yield, clock skew scheduling
36	Mohamed H. Abu-Rahma, Kinshuk Chowdhury, Joseph Wang, Zhiqin Chen, Sei Seung Yoon, Mohab Anis	A methodology for statistical estimation of read access yield in SRAMs.	DAC	2008	DBLP DOI BibTeX RDF	access failure, random variations, memory, variability, statistical modeling, yield, SRAM, worst-case
36	Donghwi Lee, Erik H. Volkerink, Intaik Park, Jeff Rearick	Empirical Validation of Yield Recovery Using Idle-Cycle Insertion.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	false failure, ATPG, delay testing, functional test, structural test, IR drop, yield loss
36	Fei Su, Krishnendu Chakrabarty	Yield enhancement of reconfigurable microfluidics-based biochips using interstitial redundancy.	ACM J. Emerg. Technol. Comput. Syst.	2006	DBLP DOI BibTeX RDF	space redundancy, reconfiguration, Microfluidics, yield enhancement
36	Song Peng, Rajit Manohar	Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	asynchronous circuits, yield, defect tolerance, 3D integration, self-reconfiguration
36	Robert Madge	New test paradigms for yield and manufacturability.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	nanometer-era semiconductor, test paradigm, yield and manufacturability
36	Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester	Parametric yield estimation considering leakage variability.	DAC	2004	DBLP DOI BibTeX RDF	variability, leakage, parametric yield
36	Chaochang Chiu, Jih-Tay Hsu, Chih-Yung Lin	The Application of Genetic Programming in Milk Yield Prediction for Dairy Cows.	Rough Sets and Current Trends in Computing	2000	DBLP DOI BibTeX RDF	dynamic mutation, milk yield prediction, Genetic programming
36	G. S. Samudra, H. M. Chen, D. S. H. Chan, Yaacob Ibrahim	Yield Optimization by Design Centering and Worst-Case Distance Analysis.	ICCD	1999	DBLP DOI BibTeX RDF	worst-case distance, design centering, optimization, VLSI design, parametric yield
36	Witold A. Pleskacz	Yield Estimation of VLSI Circuits with Downscaled Layouts.	DFT	1999	DBLP DOI BibTeX RDF	IC layout scaling, VLSI circuits, critical area, spot defects, manufacturing yield
36	Dimitris Nikolos, Haridimos T. Vergos	On the Yield of VLSI Processors with on-chip CPU Cache.	EDCC	1996	DBLP DOI BibTeX RDF	Indexing terms On-chip CPU caches, Partially good chips, Fault Tolerance, Yield Enhancement
36	Steven D. Millman	Improving quality: Yield versus test coverage.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	quality, Fault modeling, yield, test economics, physical defects
35	Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi	Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm.	DSD	2008	DBLP DOI BibTeX RDF
35	Guo Yu, Peng Li 0001	Yield-aware hierarchical optimization of large analog integrated circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
35	Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy 0001	Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies.	DATE	2005	DBLP DOI BibTeX RDF
35	Zhaojun Wo, Israel Koren, Maciej J. Ciesielski	Yield-aware Floorplanning.	DSD	2005	DBLP DOI BibTeX RDF
35	Dirk K. de Vries, Paul L. C. Simon	Calibration of Open Interconnect Yield Models.	DFT	2003	DBLP DOI BibTeX RDF
35	Noh-Jin Park, Byoungjae Jin, K. M. George, Nohpill Park, Minsu Choi	Regressive Testing for System-on-Chip with Unknown-Good-Yield.	DFT	2003	DBLP DOI BibTeX RDF
35	Kamal Rajkanan	Yield Analysis Methodology for Low Defectivity Wafer Fabs.	MTDT	2000	DBLP DOI BibTeX RDF
34	Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai	DFM/DFY practices during physical designs for timing, signal integrity, and power.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, DFY, dynamic IR drop, process variation, physical designs, DFM, design for manufacturability, signal integrity, timing integrity, yield analysis, design for yield
34	Gerard A. Allan, Anthony J. Walton	Efficient critical area estimation for arbitrary defect shapes.	DFT	1997	DBLP DOI BibTeX RDF	critical area estimation, arbitrary defect shapes, circular defects, elliptical defects, rod shaped defects, arbitrary shaped defects, Edinburgh Yield Estimator, Cadence layout editor, EYE-sampling tool, EYE, EYES, integrated circuit yield, IC layout
33	Uthman Alsaiari, Resve A. Saleh	Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits.	ISQED	2008	DBLP DOI BibTeX RDF	Partitioning, Redundancy, Yield, Flip-Flop
32	M. Javad Paknejad, Farrokh Nasri, John F. Affisco	Yield improvement and yield variability reduction in an EOQ model with planned shortages and random yield.	Comput. Ind. Eng.	2015	DBLP DOI BibTeX RDF
32	Robert O. Briggs, Sajda Qureshi, Bruce A. Reinig	Satisfaction Attainment Theory as a Model for Value Creation.	HICSS	2004	DBLP DOI BibTeX RDF
32	Nam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, Youngsoo Shin	Frequency and yield optimization using power gates in power-constrained designs.	ISLPED	2009	DBLP DOI BibTeX RDF	optimization, yield, power gate, frequency
32	Jin-Tai Yan, Zhi-Wei Chen	Redundant wire insertion for yield improvement.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	redundant wire, routing, yield
32	Yan Pan, Joonho Kong, Serkan Ozdemir, Gokhan Memik, Sung Woo Chung	Selective wordline voltage boosting for caches to manage yield under process variations.	DAC	2009	DBLP DOI BibTeX RDF	access time failure, selective wordline voltage boosting, cache, process variations, yield
32	Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera	Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, routing, variation, yield enhancement
32	Jing Li 0073, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy 0001	Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement.	DAC	2008	DBLP DOI BibTeX RDF	STT MRAM, yield
32	Qiang Zhou 0001, Yici Cai, Duo Li, Xianlong Hong	A Yield-Driven Gridless Router.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	gridless routing, integrated circuit layout, critical area, design for yield
32	N. Pete Sedcole, Peter Y. K. Cheung	Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis.	FPGA	2007	DBLP DOI BibTeX RDF	statistical theory, within-die variability, modelling, FPGA, delay, reconfiguration, process variation, yield
32	Greg Yeric, Ethan Cohen, John Garcia, Kurt Davis, Esam Salem, Gary Green	Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	systematic yield loss, test structure, BEOL, DFM, process monitoring, silicon debug, infrastructure IP
32	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja	Yield-Driven, False-Path-Aware Clock Skew Scheduling.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	performance-related circuit yield loss, circuit-level parameters, DFM, clock skew scheduling
32	Katherine Shu-Min Li, Chung-Len Lee 0001, Yao-Wen Chang, Chauchin Su, Jwu E. Chen	Multilevel full-chip routing with testability and yield enhancement.	SLIP	2005	DBLP DOI BibTeX RDF	multilevel routing, yield, testability
32	Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang	A methodology to improve timing yield in the presence of process variations.	DAC	2004	DBLP DOI BibTeX RDF	timing analysis, gate sizing, timing yield
32	Farid N. Najm, Noel Menezes	Statistical timing analysis based on a timing yield model.	DAC	2004	DBLP DOI BibTeX RDF	statistical timing analysis, principal components, timing yield
32	Thomas S. Barnett, Adit D. Singh, Victor P. Nelson	Yield-Reliability Modeling for Fault Tolerant Integrated Circuits.	DFT	2001	DBLP DOI BibTeX RDF	infant mortality, negative binomial distribution, clustering, reliability, redundancy, yield, defects, defect tolerance, burn-in
32	Hugo Cheung, Sandeep K. Gupta 0001	A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study.	VTS	2000	DBLP DOI BibTeX RDF	critical severity, test escape, fault modeling, IDDQ, yield loss