Search results for "SRAM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
42	Mohammed Shareef I, Pradeep Nair, Bharadwaj Amrutur	Energy Reduction in SRAM using Dynamic Voltage and Frequency Management.	VLSI Design	2008	DBLP DOI BibTeX RDF	Delay Monitor, DVFM, Pareto optimal curve, Replica circuits, SRAM, Energy reduction, Energy monitor
42	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang	Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	FD/SOI, low-power, stability, SRAM
42	Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Kaushik Roy 0001	Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM.	DAC	2006	DBLP DOI BibTeX RDF	adaptive source biasing, hold failures, low power SRAM
42	Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif	Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events.	DAC	2006	DBLP DOI BibTeX RDF	statistical performance analysis, SRAM, yield prediction
42	Kanak Agarwal, Sani R. Nassif	Statistical analysis of SRAM cell stability.	DAC	2006	DBLP DOI BibTeX RDF	modeling, reliability, stability, SRAM, noise margin
42	Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy 0001	Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS.	VTS	2005	DBLP DOI BibTeX RDF	Failure mechanixm, Process Variation, DFT, SRAM, March Test
42	Josh Yang, Baosheng Wang, André Ivanov	Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode.	VLSI Design	2004	DBLP DOI BibTeX RDF	6T SRAM, Area Penalty, Write Recovery, Memory testing, Test Time, Open Defects
40	Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan	Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems.	VLSI Design	2009	DBLP DOI BibTeX RDF
40	Tsu-Ming Liu, Chen-Yi Lee	Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	prediction, memory hierarchy, H.264/AVC, lookahead
40	Rajesh Garg, Peng Li 0001, Sunil P. Khatri	Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs).	ISCAS	2008	DBLP DOI BibTeX RDF
40	Sherif A. Tawfik, Volkan Kursun	Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation.	ISQED	2008	DBLP DOI BibTeX RDF
40	Sumesh Udayakumaran, Angel Dominguez, Rajeev Barua	Dynamic allocation for scratch-pad memory using compile-time decisions.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	embedded systems, compiler, Memory allocation, software caching, scratch pad, software-managed cache
39	Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, Dennis Sylvester, David T. Blaauw	Low power circuit design based on heterojunction tunneling transistors (HETTs).	ISLPED	2009	DBLP DOI BibTeX RDF	SRAM design, low power applications, tunneling transistor
38	Minki Cho, Jason Schlessman, Wayne H. Wolf, Saibal Mukhopadhyay	Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications.	ASP-DAC	2009	DBLP DOI BibTeX RDF
38	Mahadevan Gomathisankaran, Akhilesh Tyagi	WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays.	ISVLSI	2004	DBLP DOI BibTeX RDF
35	Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López 0001, José Duato	An hybrid eDRAM/SRAM macrocell to implement first-level data caches.	MICRO	2009	DBLP DOI BibTeX RDF	retention time, static and dynamic memory cells, leakage current
35	Yu-Hsun Lin, Xuan-Yi Lin, Yeh-Ching Chung	Reducing Leakage Power of JPEG Image on Asymmetric SRAM.	CSE (2)	2009	DBLP DOI BibTeX RDF
35	S. Lakshminarayanan, J. Joung, Giri Narasimhan, Ravi Kapre, M. Slanina, J. Tung, Morgan Whately, C.-L. Hou, W.-J. Liao, S.-C. Lin, P.-G. Ma, C.-W. Fan, M.-C. Hsieh, F.-C. Liu, K.-L. Yeh, W.-C. Tseng, S. W. Lu	Standby power reduction and SRAM cell optimization for 65nm technology.	ISQED	2009	DBLP DOI BibTeX RDF
35	Soner Yaldiz, Umut Arslan, Xin Li 0001, Larry T. Pileggi	Efficient statistical analysis of read timing failures in SRAM circuits.	ISQED	2009	DBLP DOI BibTeX RDF
35	D. E. Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek K. De	Accurate Estimation of SRAM Dynamic Stability.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
35	Kanak Agarwal, Sani R. Nassif	The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
35	Hoang Le, Weirong Jiang, Viktor K. Prasanna	Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA.	FPL	2008	DBLP DOI BibTeX RDF
35	Lara Dolecek, Masood Qazi, Devavrat Shah, Anantha P. Chandrakasan	Breaking the simulation barrier: SRAM evaluation through norm minimization.	ICCAD	2008	DBLP DOI BibTeX RDF
35	Kunhyuk Kang, Haldun Kufluoglu, Kaushik Roy 0001, Muhammad Ashraful Alam	Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
35	Eze Kamanu, Pratapa Reddy, Kenneth Hsu, Marcin Lukowiak	A New Architecture for Single-Event Detection & Reconfiguration of SRAM-based FPGAs.	HASE	2007	DBLP DOI BibTeX RDF
35	Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff	Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA.	DATE	2007	DBLP DOI BibTeX RDF
35	Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis	High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process.	DSD	2007	DBLP DOI BibTeX RDF
35	Luca Sterpone, Massimo Violante	A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	transient fault injection, FPGA, reliability, place and route
35	Josh Yang, Baosheng Wang, Yuejian Wu, André Ivanov	Fast detection of data retention faults and other SRAM cell open defects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
35	Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy 0001	Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design.	DATE	2006	DBLP DOI BibTeX RDF
35	Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev	Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests.	MTDT	2006	DBLP DOI BibTeX RDF
35	Bin Zhang 0011, Ari Arapostathis, Sani R. Nassif, Michael Orshansky	Analytical modeling of SRAM dynamic stability.	ICCAD	2006	DBLP DOI BibTeX RDF
35	Chua-Chin Wang, Ching-Li Lee, Wun-Ji Lin	A 4-Kb low power 4-T SRAM design with negative word-line gate drive.	ISCAS	2006	DBLP DOI BibTeX RDF
35	R. Venkatraman, R. Castagnetti, S. Ramesh 0004	The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability.	ISQED	2006	DBLP DOI BibTeX RDF
35	Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida Kanj, Sani R. Nassif	System-Level SRAM Yield Enhancement.	ISQED	2006	DBLP DOI BibTeX RDF
35	Tan Soon-Hwei, Loh Poh-Yee, Mohd-Shahiman Sulaiman	A Low-Power High-Speed 1-Mb CMOS SRAM.	DELTA	2006	DBLP DOI BibTeX RDF
35	Armin Wellig, Julien Zory	Static Noise Margin Analysis of Sub-threshold SRAM Cells in Deep Sub-micron Technology.	PATMOS	2005	DBLP DOI BibTeX RDF
35	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
35	Yingmin Li, Mark Hempstead, Patrick Mauro, David M. Brooks, Zhigang Hu, Kevin Skadron	Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices.	ISLPED	2005	DBLP DOI BibTeX RDF	architecture, power, temperature, clock gating
35	Ankur Goel, Baquer Mazhari	Gate Leakage and Its Reduction in Deep Submicron SRAM.	VLSI Design	2005	DBLP DOI BibTeX RDF
35	Chua-Chin Wang, Yih-Long Tseng, Hon-Yuan Leo, Ron Hu	A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
35	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan	Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
35	Raymond A. Heald, Ping Wang	Variability in sub-100nm SRAM designs.	ICCAD	2004	DBLP DOI BibTeX RDF
35	John C. Lach, Jason Brandon, Kevin Skadron	A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs.	ICCD	2004	DBLP DOI BibTeX RDF
35	Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante	On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs.	IOLTS	2004	DBLP DOI BibTeX RDF
35	Huifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, Jan M. Rabaey	SRAM Leakage Suppression by Minimizing Standby Supply Voltage.	ISQED	2004	DBLP DOI BibTeX RDF
35	Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez	AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold.	ITC	2004	DBLP DOI BibTeX RDF
35	Sergey Romanovsky, Arun Achyuthan, Sreedhar Natarajan, Wing Leung	Leakage Reduction techniques in a 0.13um SRAM Cell.	VLSI Design	2004	DBLP DOI BibTeX RDF
35	Meenatchi Jagasivamani, Dong Sam Ha	Development of a low-power SRAM compiler.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
34	Paul Zuber, Petr Dobrovolný, Miguel Miranda	A holistic approach for statistical SRAM analysis.	DAC	2010	DBLP DOI BibTeX RDF	statistical SRAM analysis, process variability, yield prediction
34	Maziar Goudarzi, Tohru Ishihara	Instruction cache leakage reduction by changing register operands and using asymmetric sram cells.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	asymmetric sram, leakage, instruction cache, register renaming
34	Sheng Lin 0006, Yong-Bin Kim, Fabrizio Lombardi	A low leakage 9t sram cell for ultra-low power operation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	sram cell, low power, nanotechnology, leakage power, static noise margin
34	Young-Gu Kim, Soo-Hwan Kim, Hoon Lim, Sanghoon Lee, Keun-Ho Lee, Young-Kwan Park, Moon-Hyun Yoo	The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale Era.	ISQED	2008	DBLP DOI BibTeX RDF	Statistical failure analysis, DFM, SRAM
34	Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif	Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield.	ISQED	2008	DBLP DOI BibTeX RDF	decoupled design, 8T, 6T, stacked devices, stability, yield, sram, double gate
34	Alexandre Ney, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin	An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing.	VTS	2008	DBLP DOI BibTeX RDF	write driver, design-for-diagnosis, diagnosis, SRAM
34	Bastien Giraud, Amara Amara	Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS.	DELTA	2008	DBLP DOI BibTeX RDF	SRAM cell, Double Gate (DG), Static Noise Margin (SNM), Write Margin (WM)
34	Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang	A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	booster circuit, low power, yield, SRAM
34	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Hage-Hassan	Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	SRAM core-cell, resistive open defects, memory testing, March test, dynamic faults
34	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies.	DAC	2005	DBLP DOI BibTeX RDF	SRAM memories, VDSM technologies, core-cell, test, march test, dynamic faults, defect analysis
34	Navid Azizi, Andreas Moshovos, Farid N. Najm	Low-leakage asymmetric-cell SRAM.	ISLPED	2002	DBLP DOI BibTeX RDF	low-leakage, low-power, SRAM, dual-Vt
34	Ad J. van de Goor, J. E. Simonse	Defining SRAM Resistive Defects and Their Simulation Stimuli.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Resistive defects, simulation stimuli, SRAM functional faults, SPICE simulation
33	Ihsen Alouani, Hamzeh Ahangari, Özcan Özturk 0001, Smaïl Niar	NS-SRAM: Neighborhood Solidarity SRAM for Reliability Enhancement of SRAM Memories.	DSD	2016	DBLP DOI BibTeX RDF
32	Yangyang Pan, Tong Zhang 0002	Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking.	ASAP	2009	DBLP DOI BibTeX RDF
32	Xiaoxia Wu, Jian Li 0059, Lixin Zhang 0002, Evan Speight, Ramakrishnan Rajamony, Yuan Xie 0001	Hybrid cache architecture with disparate memory technologies.	ISCA	2009	DBLP DOI BibTeX RDF	hybrid cache architecture, three-dimensional ic
32	Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin	Fault models for embedded-DRAM macros.	DAC	2009	DBLP DOI BibTeX RDF	memory testing, embedded DRAM
32	Lushan Liu, Pradeep Nagaraj, Shambhu J. Upadhyaya, Ramalingam Sridhar	Defect Analysis and Defect Tolerant Design of Multi-port SRAMs.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Multi-port SRAMs, Defect/fault tolerant design, Defect analysis
32	Lushan Liu, Ramalingam Sridhar, Shambhu J. Upadhyaya	A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells.	DFT	2006	DBLP DOI BibTeX RDF
32	Sadagopan Srinivasan, Vinodh Cuppu, Bruce L. Jacob	Transparent data-memory organizations for digital signal processors.	CASES	2001	DBLP DOI BibTeX RDF
31	Viktor Pus, Jan Korenek	Fast and scalable packet classification using perfect hash functions.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, sram, packet classification
31	Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert	A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM.	DELTA	2008	DBLP DOI BibTeX RDF	dummy bitline driver, self-timed memory, low power, SRAM, statistical design
31	Betty Prince	Nanotechnology and emerging memories.	SBCCI	2007	DBLP DOI BibTeX RDF	FeRAM, ferroelectric, floating body, nanocrystal, nitride storage, scaling issues, single electron memories, memory, variability, scaling, SRAM, MEMs, DRAM, flash, MRAM, phase change, non-volatile, molecular memory
31	Amit Agarwal 0001, Kaushik Roy 0001	A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime.	ISLPED	2003	DBLP DOI BibTeX RDF	diode, low leakage cache, SRAM, gate leakage
31	Yen-Jen Chang, Chia-Lin Yang, Feipei Lai	A power-aware SWDR cell for reducing cache write power.	ISLPED	2003	DBLP DOI BibTeX RDF	circuit-level, write power, low power, cache, SRAM
31	Jian Liu, Rafic Z. Makki, Ayman I. Kayssi	Dynamic Power Supply Current Testing of CMOS SRAMs.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	transient power supply current (i DDT), transient current sensor, disturb fault, CMOS SRAM
30	Tom Thomas, Brian W. Anthony	Area, Performance, and Yield Implications of Redundancy in On-Chip Caches.	ICCD	1999	DBLP DOI BibTeX RDF	cache, redundancy, microprocessor, yield, SRAM, yield enhancement, microprocessor design, embedded SRAM
30	Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang	On Designing of 4-Valued Memory with Double-Gate TFT.	ISMVL	1995	DBLP DOI BibTeX RDF	thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit
30	Puneet Sawhney, Haroon Rasheed	Static RAM generators with automated characterization techniques for a 0.5 micron triple-metal embedded array.	VLSI Design	1995	DBLP DOI BibTeX RDF	static RAM generators, automatic generator characterisation tool, triple-metal embedded array, metallized SRAMs, single-port static RAMs, dual-port static RAMs, user-defined size, 0.5 micron, application specific integrated circuits, integrated circuit design, circuit CAD, aspect ratio, ASIC design, SRAM chips, SRAM chips, module generators
30	Ka-Ming Keung, Akhilesh Tyagi	SRAM CP: A Charge Recycling Design Schema for SRAM.	PATMOS	2006	DBLP DOI BibTeX RDF
27	Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM.	ISLPED	2010	DBLP DOI BibTeX RDF	fine-grain control, low power, cache memory, microarchitecture, variation, low voltage
27	Luca Sterpone	Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	fault tolerance, FPGA, Single Event Upset, Triple Modular Redundancy, Timing-driven Placement
27	Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri	Low power and high performance sram design using bank-based selective forward body bias.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	low power, high performance, body bias
27	Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme.	ISQED	2009	DBLP DOI BibTeX RDF
27	Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection.	VLSI Design	2009	DBLP DOI BibTeX RDF
27	Ke Xu 0014, Chiu-sing Choy	A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC.	IEEE Trans. Circuits Syst. Video Technol.	2008	DBLP DOI BibTeX RDF
27	Florian Bauer, Georg Georgakos, Doris Schmitt-Landsiedel	A Design Space Comparison of 6T and 8T SRAM Core-Cells.	PATMOS	2008	DBLP DOI BibTeX RDF
27	Luca Sterpone, M. A. Aguirre, Jonathan Noel Tombs, Hipólito Guzmán-Miranda	On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications.	DATE	2008	DBLP DOI BibTeX RDF
27	Chenjie Gu, Jaijeet S. Roychowdhury	An efficient, fully nonlinear, variability-aware non-monte-carlo yield estimation procedure with applications to SRAM cells and ring oscillators.	ASP-DAC	2008	DBLP DOI BibTeX RDF
27	Weirong Jiang, Viktor K. Prasanna	Parallel IP lookup using multiple SRAM-based pipelines.	IPDPS	2008	DBLP DOI BibTeX RDF
27	Weirong Jiang, Qingbo Wang, Viktor K. Prasanna	Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup.	INFOCOM	2008	DBLP DOI BibTeX RDF
27	Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jacob A. Abraham	Adaptive SRAM memory for low power and high yield.	ICCD	2008	DBLP DOI BibTeX RDF
27	Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum	ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits.	ICCD	2008	DBLP DOI BibTeX RDF
27	Abhijit Sil, Eswar Prasad Kolli, Soumik Ghosh, Magdy A. Bayoumi	High speed single-ended pseudo differential current sense amplifier for SRAM cell.	ISCAS	2008	DBLP DOI BibTeX RDF
27	Jungseob Lee, Lin Xie, Azadeh Davoodi	A Dual-Vt low leakage SRAM array robust to process variations.	ISCAS	2008	DBLP DOI BibTeX RDF
27	Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	Failure analysis for ultra low power nano-CMOS SRAM under process variations.	SoCC	2008	DBLP DOI BibTeX RDF
27	Hao-I Yang, Ssu-Yun Lai, Wei Hwang	Low-power floating bitline 8-T SRAM design with write assistant circuits.	SoCC	2008	DBLP DOI BibTeX RDF
27	Amith Singhee, Jiajing Wang, Benton H. Calhoun, Rob A. Rutenbar	Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
27	Maziar Goudarzi, Tohru Ishihara, Hamid Noori	Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.	HiPEAC	2008	DBLP DOI BibTeX RDF	process variation, cache memory, Leakage power, power reduction
27	Richard F. Hobson	A New Single-Ended SRAM Cell With Write-Assist.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
27	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Resistive-open defects, Pre-charge circuits, Memory testing, Dynamic faults
27	Tiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell	Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation.	ISVLSI	2007	DBLP DOI BibTeX RDF