Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | Victor L. Winter, Shiraz Hussain |
Verilog Synthesis in the Higher-Order Transformation Framework of TL. |
HASE |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Arnab Biswas, Luca De Michielis, Antonios Bazigos, Adrian Mihai Ionescu |
Compact modeling of DG-Tunnel FET for Verilog-A implementation. |
ESSDERC |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Grazvydas Ziemys, Andrew Giebfried, Markus Becherer, Irina Eichwald, Doris Schmitt-Landsiedel, Stephan Breitkreutz-v. Gamm |
Modelling and simulation of nanomagnetic logic with cadence virtuoso using Verilog-A. |
ESSDERC |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Alan Leung, Dimitar Bounov, Sorin Lerner |
C-to-Verilog translation validation. |
MEMOCODE |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Po-Yu Kuo, Liao-Fong Sie |
Analyze the behavior model based on Verilog-A for Sallen-Key low-pass filter. |
ICCE-TW |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Natalia Kushik, Nina Yevtushenko 0001, Stanislav N. Torgaev, Nikita Shatilov |
On using ABC for deriving distinguishing sequences for Verilog-descriptions. |
EWDTS |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Jin Hee Kim, Jason Helge Anderson |
Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Shinya Takamaeda-Yamazaki |
Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Amr Lotfy, Syed Feruz Syed Farooq, Qi S. Wang, Soner Yaldiz, Praveen Mosalikanti, Nasser A. Kurd |
A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology. |
CICC |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Mohammad-Mahdi Bidmeshki, Yiorgos Makris |
VeriCoq: A Verilog-to-Coq converter for proof-carrying hardware automation. |
ISCAS |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Xiang Liang, Ligang Hou, Jinhui Wang, Chunhui Yang, Deyang Gao, Lin Zhu |
Transaction level model of HDMI transmitter based on System Verilog. |
ASICON |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Allen Waters, Un-Ku Moon |
A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW. |
A-SSCC |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Mike Brinson, Vadim Kuznetsov |
Qucs equation-defined and Verilog-A RF device models for harmonic balance circuit simulation. |
MIXDES |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Elise Rosati, Morgan Madec, Jean-Baptiste Kammerer, Abir Rezgui, Christophe Lallement, Jacques Haiech |
Verilog-A compact space-dependent model for biology. |
MIXDES |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Sonam Negi, Pitchaiah Madduri |
Implementation of high speed radix-10 parallel multiplier using Verilog. |
VDAT |
2015 |
DBLP DOI BibTeX RDF |
|
18 | M. Santhanalakshmi, K. Yasoda |
Verilog-A implementation of energy-efficient SAR ADCs for biomedical application. |
VDAT |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Sonam Negi, Pitchaiah Madduri |
Implementation of high speed radix-10 parallel multiplier using Verilog. |
VDAT |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Yuanfan Yang, Jimson Mathew, Rishad A. Shafik, Dhiraj K. Pradhan |
Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis. |
IEEE Embed. Syst. Lett. |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Tatiana Mileydy Leal del Río, Luz Noé Oliva-Moreno, Antonio Gustavo Juárez Gracia |
Implementation of the communication protocols SPI and I2C using a FPGA by the HDL-Verilog language. |
Res. Comput. Sci. |
2014 |
DBLP BibTeX RDF |
|
18 | Tze Sin Tan, Bakhtiar Affendi Rosdi |
Verilog HDL Simulator Technology: A Survey. |
J. Electron. Test. |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Sabrina Liao, Mark Horowitz |
A Verilog Piecewise-Linear Analog Behavior Model for Mixed-Signal Validation. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Moaz Mostafa, Mona Safar, M. Watheq El-Kharashi, Mohamed Dessouky |
System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Ahmed A. M. Emara, Mohamed M. Aboudina, Hossam A. H. Fahmy |
Corrected and accurate Verilog-A for linear dopant drift model of memristors. |
MWSCAS |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Kehan Zhu, Vishal Saxena, Wan Kuang |
Compact Verilog-A modeling of silicon traveling-wave modulator for hybrid CMOS photonic circuit design. |
MWSCAS |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Tariq B. Ahmad, Maciej J. Ciesielski |
Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning. |
ISVLSI |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Grzegorz Bazydlo, Marian Adamski, Lukasz Stefanowicz |
Translation UML diagrams into Verilog. |
HSI |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Maria-Anna Chalkiadaki, Cédric Valla, Frédéric Poullet, Matthias Bucher |
Why- and how- to integrate Verilog-A compact models in SPICE simulators. |
Int. J. Circuit Theory Appl. |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Abhishek Jain 0003, Giuseppe Bonanno, Hima Gupta, Ajay Goyal |
Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs |
CoRR |
2013 |
DBLP BibTeX RDF |
|
18 | George Matheou, Paraskevas Evripidou |
Verilog-based simulation of hardware support for data-flow concurrency on multicore systems. |
ICSAMOS |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oghenekarho Okobiah |
Polynomial Metamodel integrated Verilog-AMS for memristor-based mixed-signal system design. |
MWSCAS |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Sandeep Miryala, Mehrdad Montazeri, Andrea Calimera, Enrico Macii, Massimo Poncino |
A verilog-a model for reconfigurable logic gates based on graphene pn-junctions. |
DATE |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Carsten Wegener |
Method of modeling analog circuits in verilog for mixed-signal design simulations. |
ECCTD |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Mahmoud Fawzy Wagdy, Sandesh Maraliga Jayaram |
A Novel Flash Fast-Locking Digital PLL: Verilog-AMS Modeling and Simulations. |
ITNG |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Samir Ouchani, Otmane Aït Mohamed, Mourad Debbabi |
A formal verification framework for Bluespec System Verilog. |
FDL |
2013 |
DBLP BibTeX RDF |
|
18 | Sabrina Liao, Mark Horowitz |
A Verilog piecewise-linear analog behavior model for mixed-signal validation. |
CICC |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Himani Mittal, Dinesh Chandra, Arvind Tiwari |
Design of Low Power FSM Using Verilog in VLSI. |
QSHINE |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oghenekarho Okobiah |
iVAMS: Intelligent metamodel-integrated Verilog-AMS for circuit-accurate system-level mixed-signal design exploration. |
ASAP |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Florian Stock, Andreas Koch 0001, Dietmar Hildenbrand |
FPGA-accelerated color edge detection using a Geometric-Algebra-to-Verilog compiler. |
ISSoC |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Michal Doligalski, Marian Adamski |
UML state machine implementation in FPGA devices by means of dual model and Verilog. |
INDIN |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Adam Duley, Chris Spandikow, Miryung Kim |
Vdiff: a program differencing algorithm for Verilog hardware description language. |
Autom. Softw. Eng. |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Beatriz Blanco-Filgueira, Paula López 0001, Juan Bautista Roldán |
A Verilog-AMS photodiode model including lateral effects. |
Microelectron. J. |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Bernhard Peischl, Naveed Riaz, Franz Wotawa |
Automated Debugging of Verilog Designs. |
Int. J. Softw. Eng. Knowl. Eng. |
2012 |
DBLP DOI BibTeX RDF |
|
18 | George Gal, Omar Abdelfattah, Gordon W. Roberts |
A 30-40 GHz fractional-N frequency synthesizer development using a Verilog-A high-level design methodology. |
MWSCAS |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson |
The VTR project: architecture and CAD for FPGAs from verilog to routing. |
FPGA |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Marc Renaudin, Alain Fonkoua |
Tiempo Asynchronous Circuits System Verilog Modeling Language. |
ASYNC |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Ian G. Harris |
Automatic generation of Verilog bus transactors from natural language protocol specifications. |
HLDVT |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Huibiao Zhu, Peng Liu, Jifeng He 0001, Shengchao Qin |
Mechanical Approach to Linking Operational Semantics and Algebraic Semantics for Verilog Using Maude. |
UTP |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Darshan A. Dimplu, Fei Wang |
Behavior Modeling of Programmable Metallization Cell Using Verilog-A. |
ITNG |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Flavius Gruian, Mehmet Ali Arslan |
Java bytecode to hardware made easy with bluespec system verilog. |
JTRES |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Junbeom Yoo, Jong-Hoon Lee, Sehun Jeong, Sung Deok Cha |
FBDtoVerilog: A Vendor-Independent Translation from FBDs into Verilog Programs. |
SEKE |
2011 |
DBLP BibTeX RDF |
|
18 | Han Zhu, Huibiao Zhu, Si Liu 0001, Jian Guo 0005 |
Towards Denotational Semantics for Verilog in PVS. |
SSIRI (Companion) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Jun Ye, Qingping Tan, Tun Li, GuoRong Cao |
FeatureVerilog: Extending Verilog to Support Feature-Oriented Programming. |
IPDPS Workshops |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo |
Verilog-A modeling of SPAD statistical phenomena. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Yosi Ben-Asher, Nadav Rotem, Eddie Shochat |
Finding the best compromise in compiling compound loops to Verilog. |
J. Syst. Archit. |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Rosario M. Reas, Anastacia B. Alvarez, Joy Alinda P. Reyes |
Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL. |
UKSim |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Patrick O'Neil Meredith, Michael Katelman, José Meseguer 0001, Grigore Rosu |
A formal executable semantics of Verilog. |
MEMOCODE |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Matthias Raffelsieper, Mohammad Reza Mousavi 0001, Chris W. H. Strolenberg |
Checking and deriving module paths in Verilog cell library descriptions. |
DATE |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Peter Jamieson, Kenneth B. Kent, Farnaz Gharibian, Lesley Shannon |
Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research. |
FCCM |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi |
Fault injection in mixed-signal environment using behavioral fault modeling in Verilog-A. |
BMAS |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Adam Duley, Chris Spandikow, Miryung Kim |
A program differencing algorithm for verilog HDL. |
ASE |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Lijun Li, Carl Tropper |
A Multiway Design-driven Partitioning Algorithm for Distributed Verilog Simulation. |
Simul. |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Colin C. McAndrew, Zoltan Huszka, Geoffrey J. Coram |
Bipolar Transistor Excess Phase Modeling in Verilog-A. |
IEEE J. Solid State Circuits |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Takialddin Al-smadi |
Learning to Computer Architecture Courses Using Verilog Hardware Description Language (VHDL). |
Egypt. Comput. Sci. J. |
2009 |
DBLP BibTeX RDF |
|
18 | Kwan-Hee Jo, Ji-Hye Bong, Kyeong-Sik Min, Sung-Mo Kang |
A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs. |
IEICE Electron. Express |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Bernhard Peischl, Naveed Riaz, Franz Wotawa |
Employing Test Suites for Verilog Fault Localization. |
CAEPIA |
2009 |
DBLP DOI BibTeX RDF |
|
18 | David Kammler, Junqing Guan, Gerd Ascheid, Rainer Leupers, Heinrich Meyr |
A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations. |
SSIRI |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Sina Meraji, Wei Zhang 0034, Carl Tropper |
On the Scalability and Dynamic Load Balancing of Parallel Verilog Simulations. |
WSC |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Matthias Raffelsieper, Jan-Willem Roorda, Mohammad Reza Mousavi 0001 |
Model Checking Verilog Descriptions of Cell Libraries. |
ACSD |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Purvi D. Mulani |
SoC Level Verification Using System Verilog. |
ICETET |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Sina Meraji, Wei Zhang 0034, Carl Tropper |
On the Scalability of Parallel Verilog Simulation. |
ICPP |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Zhen Zhang, Hui Zhang |
The Hardware Interface Design In SoC with Verilog Language. |
SSME |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Mario Auer, Christoph Wurzinger |
Verhaltensmodellierung von Delta-Sigma-ADCs unter Verwendung von Verilog-A. |
Elektrotech. Informationstechnik |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Yen-Chu Hung |
The Effect of Problem-Solving Instruction on Computer Engineering Majors' Performance in Verilog Programming. |
IEEE Trans. Educ. |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Mile K. Stojcev |
Navabi Zainalabedin, Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, & Verification (second ed.), McGraw Hill, New York (2006) ISBN 0-07-144564-1 Hardcover, pp 384, plus XVI. |
Microelectron. Reliab. |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Arvind, Rishiyur S. Nikhil |
Hands-on Introduction to Bluespec System Verilog (BSV) (Abstract). |
MEMOCODE |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Steve Haynal, Timothy Kam, Michael Kishinevsky, Emily Shriver, Xinning Wang |
A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study. |
MEMOCODE |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah |
Reveal: A Formal Verification Tool for Verilog Designs. |
LPAR |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Yosi Ben-Asher, Eddie Shochat |
Finding the Best Compromise in Compiling Compound Loops to Verilog. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler |
Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Mohammad Shokrollah-Shirazi, Seyed Ghassem Miremadi |
FPGA-Based Fault Injection into Synthesizable Verilog HDL Models. |
SSIRI |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Susovon Samanta, Srikanth Pam, H. Mohan Geddada, Siddhartha Mukhopadhyay |
An Improved Algorithm for Frequency Response Analysis of Switching Convertes and its Implementation in Verilog-A. |
ICIIS |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Laurent Lemaitre, Colin C. McAndrew |
Voltage-controlled-current-source-only verilog-a resistor model for R⩾0. |
BMAS |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Albrecht Jander, Linda Engelbrecht, Pallavi Dhagat |
Dynamic Verilog - A Model of a Magnetoresistive Spin Valve. |
BMAS |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Thomas J. Sheffler |
Design of a Switch-Level Analog Model for Verilog. |
BMAS |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Keiichiro Ishihara, Takeyuki Tsuruma, Yasuhiko Iguchi, Takeshi Sawada, Makoto Watanabe, Yasuhito Maki |
Implementation of Optical Response of Thin Film Transistor with Verilog-A for Mobile LCD Applications. |
BMAS |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Yi Wang, Yikai Wang, Lenian He |
Behavioral modeling for operational amplifier in sigma-delta modulators with Verilog-A. |
APCCAS |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Hung-Yuan Chu, Chun-Hung Yang, Chi-Wai Leng, Chien-Hung Tsai |
A top-down, mixed-level design methodology for CT BP ΔΣ modulator using verilog-A. |
APCCAS |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Naiyong Jin, Chengjie Shen, Jun Chen, Taoyong Ni |
Engineering of An Assertion-based PSLSimple-Verilog Dynamic Verifier by Alternating Automata. |
TTSS |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Zhipeng Ye, Wenbin Chen, Michael Peter Kennedy |
Modeling and Simulation of Delta-Sigma Fractional-N PLL Frequency Synthesizer in Verilog-AMS. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Karl Stroetmann |
Computer-Architektur - Modellierung, Entwicklung und Verifikation mit Verilog: Grundlagen der Elektro- und Informationstechnik. |
|
2007 |
RDF |
|
18 | Daniel Kroening, Natasha Sharygina |
Interactive presentation: Image computation and predicate refinement for RTL verilog using word level proofs. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Shireesh Verma, Ian G. Harris, Kiran Ramineni |
Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Carl Ebeling, Brian French |
Abstract Verilog: A Hardware Description Language for Novice Students. |
MSE |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Walter Fergusson, Rakesh H. Patel, William Bereza |
Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A. |
CICC |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Maher Assaad, David R. S. Cumming |
CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC. |
SoC |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Mile K. Stojcev |
Stephen Brown Zvonko Vranesic, Fundamental of Digital Logic with Verilog Design, McGraw Hill, Boston, 2004, Hardcover, pp 844, plus XX, ISBN 0-07-121359-7. |
Microelectron. Reliab. |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Robert B. Reese, Mitchell A. Thornton |
Introduction to Logic Synthesis using Verilog HDL |
|
2006 |
DOI RDF |
|
18 | Jan Schat |
Simulation of SoCs with embedded mixed-signal Cores using a Verilog High-Speed Virtual Serial Interface. |
ICECS |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Murali Shanmugasundaram, Shanthi Pavan |
Rapid Simulation of Current Steering Digital-to-Analog Converters using Verilog-A. |
CICC |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Takafumi Yamamoto, Tsutomu Suzuki, Hideki Asai |
Concurrent Design of Delta-Sigma Modulator Using Behavioral Modeling and Simulation with the Verilog-A. |
CICC |
2006 |
DBLP DOI BibTeX RDF |
|