Search results for "BIST"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
29	Elmet Orasson, Rein Raidma, Raimund Ubar, Gert Jervan, Zebo Peng	Fast Test Cost Calculation for Hybrid BIST in Digital Systems.	DSD	2001	DBLP DOI BibTeX RDF
29	Biplab K. Sikdar, Samir Roy, Debesh K. Das	Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
29	Abhijit Jas, C. V. Krishna, Nur A. Touba	Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme.	VTS	2001	DBLP DOI BibTeX RDF
29	Makoto Sugihara, Hiroto Yasuura, Hiroshi Date	Analysis and Minimization of Test Time in a Combined BIST and External Test Approach.	DATE	2000	DBLP DOI BibTeX RDF
29	Alfredo Benso, Stefano Di Carlo, Silvia Chiusano, Paolo Prinetto, Fabio Ricciato, Monica Lobetti Bodoni, Maurizio Spadari	On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs.	ICCD	2000	DBLP DOI BibTeX RDF
29	Miron Abramovici, Charles E. Stroud, Brandon Skaggs, John Marty Emmert	Improving On-Line BIST-Based Diagnosis for Roving STARs.	IOLTW	2000	DBLP DOI BibTeX RDF	on-line testing and diagnosis, FPGA test and diagnosis
29	Giuseppe Biasoli, Fabrizio Ferrandi, Donatella Sciuto, Alessandro Fin, Franco Fummi	BIST Architectures Selection Based on Behavioral Testing.	DFT	2000	DBLP DOI BibTeX RDF
29	Gert Jervan, Zebo Peng, Raimund Ubar	Test Cost Minimization for Hybrid Bist.	DFT	2000	DBLP DOI BibTeX RDF
29	Vivek Chickermane, Scott Richter, Carl Barnhart	Integrating Logic BIST in VLSI Designs with Embedded Memories.	VTS	2000	DBLP DOI BibTeX RDF
29	Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya	An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits.	ASP-DAC	1999	DBLP DOI BibTeX RDF
29	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira 0001, Marcelino B. Santos	Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
29	Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou	Low Power Dissipation in BIST Schemes for Modified Booth Multipliers.	DFT	1999	DBLP DOI BibTeX RDF	Modified Booth Multipliers, Low Power, Built In Self Test, VLSI Testing
29	Mihalis Psarakis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers.	VTS	1999	DBLP DOI BibTeX RDF
29	Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee	An Efficient BIST Method for Small Buffers.	VTS	1999	DBLP DOI BibTeX RDF
29	Iyad Rayane, Jaime Velasco-Medina, Michael Nicolaidis	A Digital BIST for Operational Amplifiers Embedded in Mixed-Signal Circuits.	VTS	1999	DBLP DOI BibTeX RDF
29	Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik	Efficient test-point selection for scan-based BIST.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
29	Ishwar Parulkar, Sandeep K. Gupta 0001, Melvin A. Breuer	Estimation of BIST Resources During High-Level Synthesis.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	built-in self-test, high-level synthesis, estimation
29	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantinos Halatsis	R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique.	ITC	1998	DBLP DOI BibTeX RDF
29	Nilanjan Mukherjee 0001, Tapan J. Chakraborty, Sudipta Bhawmik	A BIST scheme for the detection of path-delay faults.	ITC	1998	DBLP DOI BibTeX RDF
29	Xiaoling Sun, Micaela Serra	On-line and off-line testing with shared resources: a new BIST approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
29	Rodrigue Byrne	Determining Aliasing Probabilities in BIST by Counting Strings.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	response analysis architectures, compression techniques, aliasing probabilities, deterministic finite automata
29	Chin-Long Wey	Built-in self-test (BIST) design of high-speed carry-free dividers.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
29	Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar	A Novel BIST Architecture With Built-in Self Check.	VLSI Design	1996	DBLP DOI BibTeX RDF
29	Koichi Tanno, Akio Koyama, T. Taketa, Shoichi Noguchi	Buffer insertion/self-token (BIST) protocol for multimedia LANs.	ICNP	1995	DBLP DOI BibTeX RDF
29	Kwanghyun Kim, Joseph G. Tront, Dong Sam Ha	Automatic Insertion of BIST Hardware Using VHDL.	DAC	1988	DBLP BibTeX RDF
28	Jing Li 0073, Aditya Bansal, Swaroop Ghosh, Kaushik Roy 0001	An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	Low-temperature polycrystalline silicon (LTPS), grain boundary (GB), inherent variation, thin-film transistor (TFT), generic, reconfigurable, hybrid system, BIST, DFT, 3D integration
28	Alodeep Sanyal, Sandip Kundu	A Built-in Test and Characterization Method for Circuit Marginality Related Failures.	ISQED	2008	DBLP DOI BibTeX RDF	Circuit Marginality, Pseudorandom Pattern Generator (PRPG), Multiple Input Signature Register (MISR), Fmax testing based on frequency shmoo, Built-In Self-Test (BIST), Design-for-Testability (DFT), Linear Feedback Shift Register (LFSR)
28	Michael R. Nelms, Kevin W. Gorman, Darren Anand	Generating At-Speed Array Fail Maps with Low-Speed ATE.	VTS	2004	DBLP DOI BibTeX RDF	Delay & Performance Test, Diagnosis & Debug, Design for Testability, BIST, Memory Test
28	Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar	Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories.	VLSI Design	2004	DBLP DOI BibTeX RDF	Built-in self-test for memories, neighbourhood pattern sensitive faults, programmable BIST
28	Benoît Charlot, Salvador Mir, Fabien Parrain, Bernard Courtois	Generation of Electrically Induced Stimuli for MEMS Self-Test.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	MEMS test case-studies, MEMS failure mechanisms, BIST, self-test
28	Xiaoling Sun, Jian Xu, Pieter M. Trouborst	Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules.	DFT	2001	DBLP DOI BibTeX RDF	configurable logic blocks, fault diagnosis, BIST, FPGA testing
28	Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi	Low-cost DC built-in self-test of linear analog circuits using checksums.	VLSI Design	1996	DBLP DOI BibTeX RDF	DC built-in self-test, catastrophic failures, line opens, DC transfer function, on-chip fault detection, BIST circuitry, fault diagnosis, built-in self test, integrated circuit testing, transfer functions, analogue integrated circuits, checksums, linear analog circuits, matrix representations, fault classes
28	Michael Nicolaidis	Efficient UBIST implementation for microprocessor sequencing parts.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	strongly code disjoint checkers, signature analyser, UBIST, microprocessor sequencing part, BIST, LFSR, self-checking circuits, totally self-checking circuits
28	Ender Baykut, Veysel Kula	The Volatility and Shock Transmission Patterns Between the BIST Sustainability and BIST 100 Indices.	Frontiers Appl. Math. Stat.	2019	DBLP DOI BibTeX RDF
28	Xiankun Jin, Tao Chen 0006, Mayank Jain, Arun Kumar Barman, David Kramer, Doug Garrity, Randall L. Geiger, Degang Chen 0001	An on-chip ADC BIST solution and the BIST enabled calibration scheme.	ITC	2017	DBLP DOI BibTeX RDF
28	Mehdi Sadi, Gustavo K. Contreras, Dat Tran, Jifeng Chen, LeRoy Winemberg, Mark M. Tehranipoor	BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning.	ITC	2016	DBLP DOI BibTeX RDF
28	Sybille Hellebrand, Thomas Indlekofer, Matthias Kampmann, Michael A. Kochte, Chang Liu 0010, Hans-Joachim Wunderlich	FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects.	ITC	2014	DBLP DOI BibTeX RDF
28	Hongzhi Li	A BIST (Built-In Self-Test) strategy for mixed-signal integrated circuits (BIST (Built-in Self-Test) Strategie für integrierte Mixed-Signal Schaltungen) (PDF / PS)		2004	RDF
28	Nicola Nicolici, Bashir M. Al-Hashimi	Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation.	ITC	2001	DBLP DOI BibTeX RDF
28	Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian	HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs.	ITC	1999	DBLP DOI BibTeX RDF
26	Stephen K. Sunter, Aubin Roy	A Mixed-Signal Test Bus and Analog BIST with 'Unlimited' Time and Voltage Resolution.	ETS	2011	DBLP DOI BibTeX RDF	mixed-signal DFT, analog bus, mixed-signal BIST
26	Swapnil Bahl, Vishal Srivastava	Self-Programmable Shared BIST for Testing Multiple Memories.	ETS	2008	DBLP DOI BibTeX RDF	Memory testing and Semiconductor memory, Built-in Self-test (BIST), Pipeline architecture
26	M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre	AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis.	DELTA	2008	DBLP DOI BibTeX RDF	AES core, BIST, secure systems
26	Alex Gonsales, Marcelo Lubaszewski, Luigi Carro, Michel Renovell	A New FPGA for DSP Applications Integrating BIST Capabilities.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	hardware test, FPGA, digital signal processing, DSP, BIST, reconfigurable architectures
26	Alexander Irion, Gundolf Kiefer, Harald P. E. Vranken, Hans-Joachim Wunderlich	Circuit partitioning for efficient logic BIST synthesis.	DATE	2001	DBLP DOI BibTeX RDF	divide-and-conquer, circuit partitioning, deterministic BIST
26	Jacob Savir	Distributed BIST Architecture to Combat Delay Faults.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	BIST, LFSR, delay test, MISR, LSSD, SRL
26	Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira 0001, Marcelino B. Santos	Low Power BIST by Filtering Non-Detecting Vectors.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	low power BIST, low energy consumption, LFSR, gated clock
26	Wei-Lun Wang, Kuen-Jong Lee	Accelerated test pattern generators for mixed-mode BIST environments.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
26	Hsin-Po Wang 0002, Jon Turino	DFT and BIST techniques for the future.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	multimillion gate system-on-chip, multinational design, logic testing, built-in self test, design for testability, quality, BIST, economics, DFT, integrated circuit design, time to market, production testing, IC design, integrated circuit economics
26	Der-Cheng Huang, Wen-Ben Jone	An efficient parallel transparent diagnostic BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	parallel transparent diagnostic BIST, built-in self-diagnosis method, multiple embedded memory arrays, transparent diagnostic interface, redundant read/write/shift operations, march algorithm, TDiagRSMarch algorithm, low hardware overhead, test time reduction, diagnostic efficiency, parallel algorithms, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic testing, test coverage, integrated memory circuits
26	Jacob Savir	Salvaging Test Windows in BIST Diagnostics.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	BIST diagnostics, error signature, autonomous MISR, LFSR, signature analysis, MISR
26	Jacob Savir	Salvaging test windows in BIST diagnostic.	VTS	1997	DBLP DOI BibTeX RDF	test window, STUMPS architecture, BIST diagnostics, signature measurement, built-in self test
26	Vladimír Székely, Márta Rencz, Bernard Courtois	Integrating on-chip temperature sensors into DfT schemes and BIST architectures.	VTS	1997	DBLP DOI BibTeX RDF	on-chip low-power small-area CMOS temperature sensor, DfTT, design for thermal testability, safety-critical circuit, integrated circuit testing, BIST, CMOS integrated circuits
26	Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak	Syndrome signature in output compaction for VLSI BIST.	VLSI Design	1996	DBLP DOI BibTeX RDF	syndrome signature, output compaction, VLSI BIST, input patterns, n-input combinational circuit, primary syndrome, subsyndromes, subfunctions, single-output circuit, multiple output, VLSI, logic testing, data compression, built-in self test, integrated circuit testing, combinational circuits, switching functions, exhaustive testing
26	Jing-Yang Jou	An effective BIST design for PLA.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST design, deterministic test pattern generator, cross point, AND array, fault detection capability, contact fault model, logic testing, built-in self test, integrated circuit testing, combinational circuits, automatic testing, programmable logic arrays, PLA, CMOS logic circuits, characteristic polynomial, stuck-at fault model, multiple input signature register
26	Nur A. Touba, Edward J. McCluskey	Transformed pseudo-random patterns for BIST.	VTS	1995	DBLP DOI BibTeX RDF	pseudorandom patterns transformation, onchip test pattern generation, mapping logic, on-chip TPG, logic testing, built-in self test, integrated circuit testing, logic design, BIST, combinational circuits, automatic testing, combinational logic
26	Imtiaz P. Shaik, Michael L. Bushnell	A graph approach to DFT hardware placement for robust delay fault BIST.	VLSI Design	1995	DBLP DOI BibTeX RDF	graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI
25	Jan Arild Tofte, Chee-Kian Ong, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng	Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test.	VTS	2000	DBLP DOI BibTeX RDF	cross-correlation signature register, CCSR, implicit functional testing, harmonic distortion, THD, classification, synthesis, noise, BIST, convex hull, polygon, discrimination, analog test, cross-correlation, mixed-signal, pseudo-random, pseudo-random, labview, impulse response, performance parameter, analog BIST
25	Xiaodong Zhang 0010, Kaushik Roy 0001	Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction.	DFT	1999	DBLP DOI BibTeX RDF	BIST Synthesis, Weighted Random Pattern Generator, Low Power BIST, Testing, Low Power, Cellular Automata, Peak Power
25	Han Bin Kim, Dong Sam Ha, Takeshi Takahashi 0003	On ILP Formulations for Built-In Self-Testable Data Path Synthesis.	DAC	1999	DBLP DOI BibTeX RDF	high-level BIST synthesis, built-in self-test, BIST, ILP
25	Salvador Mir, Marcelo Lubaszewski, Bernard Courtois	Unified built-in self-test for fully differential analog circuits.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	on-line/off-line analog test, unified BIST, fully differential analog circuits, common-mode feedback, analog BIST
23	Prashant Dubey, Akhil Garg 0001, Sravan Kumar Bhaskarani	GALS Based Shared Test Architecture for Embedded Memories.	ISCAS	2007	DBLP DOI BibTeX RDF
23	Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan	Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m).	VLSI Design	2007	DBLP DOI BibTeX RDF
23	Yung-Chieh Lin, Feng Lu 0002, Kwang-Ting Cheng	Pseudofunctional testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
23	Shibaji Banerjee, Dipanwita Roy Chowdhury	Built-In Self-Test for Flash Memory Embedded in SoC.	DELTA	2006	DBLP DOI BibTeX RDF
23	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Built-in sequential fault self-testing of array multipliers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
23	Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis	Accumulator-Based Weighted Pattern Generation.	IOLTS	2005	DBLP DOI BibTeX RDF
23	Amit Laknaur, Haibo Wang 0005	Built-In-Self-Testing Techniques for Programmable Capacitor Arrays.	ISQED	2005	DBLP DOI BibTeX RDF
23	R. Dean Adams, Robert Abbott, Xiaoliang Bai, Dwayne Burek, Eric MacDonald	An Integrated Memory Self Test and EDA Solution.	MTDT	2004	DBLP DOI BibTeX RDF
23	Omar I. Khan, Michael L. Bushnell	Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing.	ITC	2004	DBLP DOI BibTeX RDF
23	Sunil Rafeeque, Vinita Vasudevan	A Built-in-Self-Test Scheme for Digital to Analog Converters.	VLSI Design	2004	DBLP DOI BibTeX RDF
23	Stephen Pateras	Achieving At-Speed Structural Test.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
23	Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu	Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
23	Jin-Fu Li 0001, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin	A Hierarchical Test Scheme for System-On-Chip Designs.	DATE	2002	DBLP DOI BibTeX RDF
23	Kazumi Hatayama, Michinobu Nakao, Yasuo Sato	At-Speed Built-in Test for Logic Circuits with Multiple Clocks.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
23	Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu	On-chip Analog Response Extraction with 1-Bit ? - Modulators.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
23	Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy	On output response compression in the presence of unknown output values.	DAC	2002	DBLP DOI BibTeX RDF
23	Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri	Cellular automata as a built in self test structure.	ASP-DAC	2001	DBLP DOI BibTeX RDF
23	Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou	Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier.	ARVLSI	2001	DBLP DOI BibTeX RDF
23	Ilker Hamzaoglu, Janak H. Patel	Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators.	VTS	2000	DBLP DOI BibTeX RDF	Built-in-Self-Test, Test Generation, Combinational Circuits, Test Application Time, Stuck-at Fault Model
23	Albrecht P. Stroele	Synthesis for Arithmetic Built-In Self-Tes.	VTS	2000	DBLP DOI BibTeX RDF	test configuration, built-in self-test, high-level synthesis, synthesis for testability, Accumulator
23	Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng	Embedded hardware and software self-testing methodologies for processor cores.	DAC	2000	DBLP DOI BibTeX RDF
23	Klaus Herrmann 0002, Jan Otterstedt, Hartwig Jeschke, M. Kuboschek	A MIMD-based video signal processing architecture suitable for large area integration and a 16.6-cm2 monolithic implementation.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
23	Debaditya Mukherjee, Melvin A. Breuer	An IEEE 1149.1 Compliant Test Control Architecture.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	test control, local test control, distributed test control, dynamic test control, built-in self-test, design-for-test, boundary scan, test bus
23	Michael Nicolaidis, Yervant Zorian	On-Line Testing for VLSI - A Compendium of Approaches.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	fail-safe circuits, SEU hardened circuits, monitoring of reliability indicators, thermal monitors, radiation monitors, on-line testing, self-checking circuits, current monitors
23	Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar	Efficient Implementation of Multiple On-Chip Signature Checking.	VLSI Design	1997	DBLP DOI BibTeX RDF
23	Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja	A Tutorial on Built-in Self-Test. I. Principles.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
23	Wen-Ben Jone, Anita Gleason	Analysis of Hamming count compaction scheme.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	index vector, spectral coefficients, Built-in self test, compaction, syndrome
23	Hussam Y. Abujbara, Sami A. Al-Arian	Self-testing and self-reconfiguration architecture for 2-D WSI arrays.	SPDP	1990	DBLP DOI BibTeX RDF
23	Michael Zimmermann, Manfred Geilert	Generation of embedded RAMs with built-in test using object-oriented programming.	EURO-DAC	1990	DBLP DOI BibTeX RDF
22	Shyam Kumar Devarakond, Shreyas Sen, Abhijit Chatterjee	BIST assisted wideband digital compensation for MB-UWB transmitters.	DDECS	2009	DBLP DOI BibTeX RDF
22	Aftab Farooqi, Richard O. Gale, Sudhakar M. Reddy, Brian Nutter, Chris Monico	Markov source based test length optimized SCAN-BIST architecture.	ISQED	2009	DBLP DOI BibTeX RDF
22	Manuel J. Barragan Asian, Diego Vázquez, Adoración Rueda	Practical Implementation of a Network Analyzer for Analog BIST Applications.	DATE	2008	DBLP DOI BibTeX RDF
22	Waleed K. Al-Assadi, Sindhu Kakarla	A BIST Technique for Crosstalk Noise Detection in FPGAs.	DFT	2008	DBLP DOI BibTeX RDF
22	Bei Cao, Liyi Xiao, Yongsheng Wang	A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata.	DELTA	2008	DBLP DOI BibTeX RDF
22	Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara	Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
22	James Chien-Mo Li, Hung-Mao Lin, Fang-Min Wang	Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	fault tolerance, reliability, testing, Diagnostics
22	Erdem Serkan Erdogan, Sule Ozev	An ADC-BiST scheme using sequential code analysis.	DATE	2007	DBLP DOI BibTeX RDF
22	Haridimos T. Vergos	An Efficient BIST Scheme for Non-Restoring Array Dividers.	DSD	2007	DBLP DOI BibTeX RDF
22	Petr Fiser	Pseudo-Random Pattern Generator Design for Column-Matching BIST.	DSD	2007	DBLP DOI BibTeX RDF