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Found 10362 publication records. Showing 10361 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
102Chia-Ming Chang 0002, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang 0002, Yu-Sheng Lu Type-matching clock tree for zero skew clock gating. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF physical design, gated clock, clock network synthesis
93Xiaohong Jiang 0001, Susumu Horiguchi Statistical skew modeling for general clock distribution networks in presence of process variations. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
89Mely Chen Chi, Shih-Hsu Huang A Reliable Clock Tree Design Methodology for ASIC Designs. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Clock tree design, Clock tree synthesis
82Vernon L. Chi Salphasic Distribution of Clock Signals for Synchronous Systems. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF transmission line theory, loaded transmission line, printed circuit board clock planes, clock plane, phase skew, salphasic clock, synchronisation, clocks, distribution network, clock skews, synchronous systems, synchronous system, propagation delay, system clock, phase shifts, clock signals, clock signal
81José Luis Neves, Eby G. Friedman Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
80Julien Lamoureux, Steven J. E. Wilton On the trade-off between power and flexibility of FPGA clock networks. Search on Bibsonomy ACM Trans. Reconfigurable Technol. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF clock-aware placement, FPGA, low-power design, clock distribution networks
80Amor Bouzelat, Zoubir Mammeri Simple reading, implicit rejection and average function for fault-tolerant physical clock synchronization. Search on Bibsonomy EUROMICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF simple reading, implicit rejection, average function, fault tolerant physical clock synchronization algorithms, remote clock reading function, fault value rejection function, convergence function, clock adjustment function, clock value reference set, Lundelius algorithm, reference set, maximum skew, fault tolerance, distributed algorithms, synchronization algorithms
77José Luis Neves, Eby G. Friedman Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
76Hermann Kopetz, Astrit Ademaj, Alexander Hanzlik Integration of Internal and External Clock Synchronization by the Combination of Clock-State and Clock-Rate Correction in Fault-Tolerant Distributed Systems. Search on Bibsonomy RTSS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF fault-tolerant time base, real-time system, clock synchronization, rate adaptation, global time
74Pei-Hsin Ho Industrial clock design. Search on Bibsonomy ISPD The full citation details ... 2009 DBLP  DOI  BibTeX  RDF low power, variability, physical design, clock tree synthesis
74Baris Taskin, Ivan S. Kourtev Delay insertion method in clock skew scheduling. Search on Bibsonomy ISPD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF delay insertion, re-convergent paths, optimization, linear programming, clock skew
74Joe G. Xi, Wayne Wei-Ming Dai Jitter-tolerant clock routing in two-phase synchronous systems. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Deferred-Merge Embedding framework, clock jitter, clock tree cost, jitter-tolerance, jitter-tolerant clock routing, near-zero skew, nonoverlapping interval, safety margin, system operating conditions, two-phase clocking, two-phase jitter-tolerant useful-skew tree, two-phase synchronous systems, simulated annealing, manufacturing, jitter, zero skew
73Atsushi Takahashi 0001, Kazunori Inoue, Yoji Kajitani Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF clock-tree routing, semi-synchronous, deferred-merge-embedding (DME), synchronous, buffer insertion, buffer sizing, clock-schedule
70Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu Activity and register placement aware gated clock network design. Search on Bibsonomy ISPD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF gated clock tree, low power, placement
70Hong Hao, Kanti Bhabuthmal Clock controller design in SuperSPARC II microprocessor. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF SuperSPARC II, internal clock pulses, internal clock, free running mode, IEEE 1149.1 interface, microprocessor, clocks, microprocessor chips, clock controller
69Shinya Abe, Masanori Hashimoto, Takao Onoye Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF mesh-style clock distribution, clock skew, manufacturing variability
69Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal Path Delay Testing: Variable-Clock Versus Rated-Clock. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF rated-clock testing, slow-clock testing, Delay testing, path delay faults, sequential circuit test
68Xin-Wei Shih, Yao-Wen Chang Fast timing-model independent buffered clock-tree synthesis. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
68Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri A novel clock distribution and dynamic de-skewing methodology. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
68Amir H. Farrahi, Chunhong Chen, Ankur Srivastava 0001, Gustavo E. Téllez, Majid Sarrafzadeh Activity-driven clock design. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
68Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang Skew-aware polarity assignment in clock tree. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF peak current, polarity assignment, power/ground noise, Clock skew, clock tree
68JeongKi Park, Young-Tak Kim An Enhanced SNTP (ESNTP) Clock Synchronization for High-Precision Network QoS Measurements. Search on Bibsonomy IPOM The full citation details ... 2008 DBLP  DOI  BibTeX  RDF delay and jitter, clock drift compensation, QoS, performance measurement, Clock synchronization
67Daniela Tulone On the Feasibility of Time Estimation under Isolation Conditions in Wireless Sensor Networks. Search on Bibsonomy Algorithmica The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Sensor networks, Energy conservation, Clock synchronization, Clock drift, Time series models, Resource efficiency
67Hermann Kopetz, Astrit Ademaj, Alexander Hanzlik Combination of clock-state and clock-rate correction in fault-tolerant distributed systems. Search on Bibsonomy Real Time Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Fault-tolerant time base, Real-time system, Clock synchronization, Rate adaptation, Global time
66Monica Donno, Enrico Macii, Luca Mazzoni Power-aware clock tree planning. Search on Bibsonomy ISPD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF clock tree synthesis and routing, physical design and optimization, low-power design, digital design
64Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu Gate planning during placement for gated clock network. Search on Bibsonomy ICCD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
64Kun Sun 0001, Peng Ning, Cliff Wang Secure and resilient clock synchronization in wireless sensor networks. Search on Bibsonomy IEEE J. Sel. Areas Commun. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
64Deshanand P. Singh, Stephen Dean Brown Constrained clock shifting for field programmable gate arrays. Search on Bibsonomy FPGA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
64Stuart K. Tewksbury, Lawrence A. Hornak Optical Clock Distribution in Electronic Systems. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
64Ashutosh Chakraborty, David Z. Pan Skew management of NBTI impacted gated clock trees. Search on Bibsonomy ISPD The full citation details ... 2010 DBLP  DOI  BibTeX  RDF clock skew, clock gating, NBTI
62Ying Zhao 0011, Wanlei Zhou 0001, Yingying Zhang, E. J. Lanham, Jiumei Huang Clock Synchronization State Graphs Based on Clock Precision Difference. Search on Bibsonomy ICA3PP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Precision Difference, State graphics, Self-Adaptive, Clock Synchronization
62Monica Donno, Alessandro Ivaldi, Luca Benini, Enrico Macii Clock-tree power optimization based on RTL clock-gating. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF clock-tree synthsis, low-power design
62Julien Lamoureux, Steven J. E. Wilton FPGA clock network architecture: flexibility vs. area and power. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF FPGA, architecture, low-power, clock network
61Daniel L. Palumbo The Derivation and Experimental Verification of Clock Synchronization Theory. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF clock synchronization theory, Interactive Convergence Clock Synchronization Algorithm, Mid-Point Algorithm, clock circuitry, operating conditions, worst case failures, experimental verification, formal methods, formal verification, synchronisation, clock synchronization, clock skew, byzantine failure, proof of correctness, failure modes, timing circuits, malicious failures
61Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television
60Xiaoji Ye, Peng Li 0001 An application-specific adjoint sensitivity analysis framework for clock mesh sensitivity computation. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
60Ariel Daliot, Danny Dolev, Hanna Parnas Linear Time Byzantine Self-Stabilizing Clock Synchronization. Search on Bibsonomy OPODIS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
60Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman Retiming and clock scheduling for digital circuit optimization. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
60Qing Zhu, Wayne Wei-Ming Dai Planar clock routing for high performance chip and package co-design. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
59Atanu Chattopadhyay, Zeljko Zilic Serial reconfigurable mismatch-tolerant clock distribution. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF process variation, clock skew, clock networks
59Heinrich Moser, Ulrich Schmid 0001 Optimal Deterministic Remote Clock Estimation in Real-Time Systems. Search on Bibsonomy OPODIS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF optimal clock synchronization, remote clock estimation, real-time systems, Distributed algorithms, computing models
59En-Shou Chang, Daniel Gajski, Sanjiv Narayan An optimal clock period selection method based on slack minimization criteria. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF clock slack, scheduling, performance estimation, clock period
59Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman Timing-driven variation-aware nonuniform clock mesh synthesis. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF clock mesh synthesis, non-tree clock networks, vlsi cad, power, process variations, physical design, clock skew, clock distribution
59Alan Olson, Kang G. Shin Fault-Tolerant Clock Synchronization in Large Multicomputer Systems. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF fault-tolerant clock synchronization, large multicomputer systems, clock value, maximum skew, maximum time, fault tolerance, reliability, fault tolerant computing, multiprocessing systems, synchronisation, clocks, clock skew, clock drift, synchronization algorithm
57Cliff C. N. Sze ISPD 2010 high performance clock network synthesis contest: benchmark suite and results. Search on Bibsonomy ISPD The full citation details ... 2010 DBLP  DOI  BibTeX  RDF VLSI, benchmarks, physical design, clock network synthesis
57Anand Rajaram, David Z. Pan Variation tolerant buffered clock network synthesis with cross links. Search on Bibsonomy ISPD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF non-tree clocks, physical design, VLSI CAD, clock network
57Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu Minimizing peak current via opposite-phase clock tree. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF low power, physical design, clock network synthesis
57Benjamin R. Hamilton, Xiaoli Ma, Qi Zhao 0006, Jun (Jim) Xu ACES: adaptive clock estimation and synchronization using Kalman filtering. Search on Bibsonomy MobiCom The full citation details ... 2008 DBLP  DOI  BibTeX  RDF clock offset, resource-constrained network, Kalman filter, clock synchronization, clock skew
57Peter Wohl, John A. Waicukauski Using ATPG for clock rules checking in complex scan design. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF clock rules checking, complex scan designs, structured DFT, automated design-rules-checking, robust set of rules, clock-rule-violation detection, fast clock verification, large microprocessor design, topological circuit analysis, zero delay, user controlled verification, capture ability, port contention, cone tracing, equivalent sources, ATPG, race conditions, computer testing, timing verification
56Bao Liu 0001, Andrew B. Kahng, Xu Xu 0001, Jiang Hu, Ganesh Venkataraman A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
55Ivan S. Kourtev, Eby G. Friedman Clock skew scheduling for improved reliability via quadratic programming. Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
55Kai Zhu 0001, Martin D. F. Wong Clock skew minimization during FPGA placement. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
55Wei-Chung Chao, Wai-Kei Mak Low-power gated and buffered clock network construction. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF low power, buffer, clock gating, Clock tree, zero-skew
55Malay K. Ganai, Aarti Gupta Efficient BMC for Multi-Clock Systems with Clocked Specifications. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF OpenCores multiclock system benchmarks, clocked specifications, multiphased clocks, level-sensitive latches, SAT-based bounded model checking, synchronous multiclock systems, clocked LTL properties, clock modeling schemes, clock constraints, loop-checks, gated clocks
55Kursat Kursat Ozenc, James P. Brommer, Bong-keum Jeong, Nina Shih, Karen Au, John Zimmerman Reverse alarm clock: a research through design example of designing for the self. Search on Bibsonomy DPPI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF alarm clock, bedtime, designing for the self, material possession attachment, children, time, clock, consumer behavior, parents, social role, wakeup
55Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino Dynamic thermal clock skew compensation using tunable delay buffers. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF temperature aware design methodology, tunable delay buffers, clock skew, clock tree
55Chunhong Chen, Changjun Kang, Majid Sarrafzadeh Activity-sensitive clock tree construction for low power. Search on Bibsonomy ISLPED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF low power, clock gating, clock tree, activity pattern
55Min Zhao 0001, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal Worst case clock skew under power supply variations. Search on Bibsonomy Timing Issues in the Specification and Synthesis of Digital Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF clock skew, power supply noise, clock network
53Xiaoji Ye, Min Zhao 0001, Rajendran Panda, Peng Li 0001, Jiang Hu Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF clock mesh, dynamic time step rounding, simulation, macromodel
53Anand Rajaram, David Z. Pan Robust chip-level clock tree synthesis for SOC designs. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF chip-level CTS, physical design, clock network
53Sherif A. Tawfik, Volkan Kursun Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD
53Santashil PalChaudhuri, Amit Kumar Saha, David B. Johnson 0001 Adaptive clock synchronization in sensor networks. Search on Bibsonomy IPSN The full citation details ... 2004 DBLP  DOI  BibTeX  RDF sensor networks, clock synchronization, probabilistic algorithms
53Rui Fan 0004, Nancy A. Lynch Gradient clock synchronization. Search on Bibsonomy PODC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF ad hoc networks, lower bounds, clock synchronization, local algorithms
53Lain-Chyr Hwang, Steen J. Hsu, San-Yuan Wang, Yong-Hua Huang A Hybrid Scheduling Algorithm with Low Complexity: Jumping Virtual Clock Round Robin. Search on Bibsonomy ICDCS Workshops The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Jumping Virtual Clock (JVC), Jumping Virtual Clock Round Robin (JVCRR), Scheduling algorithm, Fair queueing, Round Robin, Virtual clock
53Chung-Seok (Andy) Seo, Abhijit Chatterjee, Sang-Yeon Cho, Nan M. Jokerst Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF H-tree, asymmetric structure, optical clock distribution, optical waveguide loss modeling, optoelectronic system-on-a-package, optimization, clock distribution, clock routing
52Vishwanadh Tirumalashetty, Hamid Mahmoodi Clock Gating and Negative Edge Triggering for Energy Recovery Clock. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
51Zhengtao Yu 0002, Xun Liu Low-Power Rotary Clock Array Design. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
51Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
51Zhengtao Yu 0002, Xun Liu Design of Rotary Clock Based Circuits. Search on Bibsonomy DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
51Liang Huang, Yici Cai, Qiang Zhou 0001, Xianlong Hong, Jiang Hu, Yongqiang Lu 0001 Clock network minimization methodology based on incremental placement. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
51Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen Minimizing coupling jitter by buffer resizing for coupled clock networks. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
51Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen Minimizing Inter-Clock Coupling Jitter. Search on Bibsonomy ISQED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
51Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh Activity-driven clock design for low power circuits. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Gated Clock Tree, Sleep Mode, Power minimization, Clock Tree
51Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi 0001 A practical clock tree synthesis for semi-synchronous circuits. Search on Bibsonomy ISPD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF clock-input timing, environmental and manufacturing conditions, semi-synchronous, various timing clock tree, zero skew clock tree, clock scheduling
50Daniela Tulone A resource--efficient time estimation for wireless sensor networks. Search on Bibsonomy DIALM-POMC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF clock drift rate, clock synchronization, time series forecasting, time estimation, resource efficiency
50Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy 0001 Energy recovery clocking scheme and flip-flops for ultra low-energy applications. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF flip-flop, clock, clock tree, energy recovery, adiabatic
49Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu A single layer zero skew clock routing in X architecture. Search on Bibsonomy Sci. China Ser. F Inf. Sci. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF single layer, X architecture, zero skew, clock routing
49Christoph Lenzen 0001, Thomas Locher, Roger Wattenhofer Tight bounds for clock synchronization. Search on Bibsonomy PODC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF gradient property, optimal skew bounds, clock synchronization
49Fabian Kuhn, Rotem Oshman Gradient Clock Synchronization Using Reference Broadcasts. Search on Bibsonomy OPODIS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Gradient Clock Synchronization, Wireless Networks
49Venkatesh Arunachalam, Wayne P. Burleson Low-power clock distribution in a multilayer core 3d microprocessor. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF 3D ic's, 3D processor architectures, clock grids
49Rui Fan 0004, Nancy A. Lynch Gradient clock synchronization. Search on Bibsonomy Distributed Comput. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Ad-hoc networks, Lower bounds, Clock synchronization, Indistinguishability
49Xinjie Wei, Yici Cai, Meng Zhao, Xianlong Hong Legitimate Skew Clock Routing with Buffer Insertion. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF legitimate skew, buffer insertion, clock routing
49Yongqiang Lu 0001, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Liang Huang, Jiang Hu Navigating registers in placement for clock network minimization. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF low power, placement, clock network, variation tolerance
49Kai Wang 0011, Malgorzata Marek-Sadowska Buffer sizing for clock power minimization subject to general skew constraints. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF sequential linear programming, sizing, clock skew scheduling
49Anand Rajaram, Jiang Hu, Rabi N. Mahapatra Reducing clock skew variability via cross links. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF VLSI, physical design, variation, clock network synthesis
49Jindrich Zejda, Paul Frain General framework for removal of clock network pessimism. Search on Bibsonomy ICCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF clock network reconvergence, voltage and temperature delay variation, process, static timing analysis, deep sub-micron
49Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF di/dt noise, low-noise digital design, supply current shaping, optimization, substrate noise, clock distribution networks
49Nestoras Tzartzanis, William C. Athas Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing. Search on Bibsonomy ARVLSI The full citation details ... 1999 DBLP  DOI  BibTeX  RDF low-power digital CMOS, adiabatic switching, clock-powered logic, energy recovery
49Martin Saint-Laurent, Animesh Datta A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF clock gater, clock gating cell, local clock buffer, set-reset latch
48Attila Pásztor, Darryl Veitch PC based precision timing without GPS. Search on Bibsonomy SIGMETRICS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF pc clocks, software clock, synchronization, timing, GPS, network measurement, NTP
48Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
48Yesin Ryu, Taewhan Kim Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization. Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
48Ashok Narasimhan, Ramalingam Sridhar Impact of Variability on Clock Skew in H-tree Clock Networks. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
48Shih-Hsu Huang, Yow-Tyng Nieh Clock Period Minimization of Non-Zero Clock Skew Circuits. Search on Bibsonomy ICCAD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
48Haksu Kim, Dian Zhou An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles. Search on Bibsonomy ISCAS (6) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
48Olivier Bezet, Véronique Berge-Cherfaoui On-line and post-processing timestamp correspondence for free-running clock nodes, using a network clock. Search on Bibsonomy Real Time Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Timestamping conversion, Timestamping error modeling, Free running clock nodes, Network clock, Distributed architecture
47Qiang Wang, Subodh Gupta, Jason Helge Anderson Clock power reduction for virtex-5 FPGAs. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
47Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay Slew-aware clock tree design for reliable subthreshold circuits. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF slew, clocks, subthreshold
47Anand Rajaram, Raguram Damodaran, Arjun Rajagopal Practical Clock Tree Robustness Signoff Metrics. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
47Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
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open data data released under the ODC-BY 1.0 license