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Publication years (Num. hits)
1959-1969 (15) 1970-1976 (15) 1977-1979 (18) 1980-1981 (16) 1982-1983 (15) 1984-1985 (22) 1986 (19) 1987 (23) 1988 (26) 1989 (42) 1990 (48) 1991 (58) 1992 (71) 1993 (76) 1994 (82) 1995 (119) 1996 (105) 1997 (124) 1998 (148) 1999 (156) 2000 (135) 2001 (171) 2002 (262) 2003 (287) 2004 (377) 2005 (394) 2006 (452) 2007 (487) 2008 (471) 2009 (338) 2010 (217) 2011 (183) 2012 (184) 2013 (186) 2014 (202) 2015 (173) 2016 (181) 2017 (238) 2018 (236) 2019 (222) 2020 (235) 2021 (287) 2022 (268) 2023 (286) 2024 (69)
Publication types (Num. hits)
article(2768) book(2) data(1) incollection(30) inproceedings(4908) phdthesis(28) proceedings(2)
Venues (Conferences, Journals, ...)
ITC(391) CoRR(262) VTS(210) IEEE Trans. Comput. Aided Des....(199) Asian Test Symposium(178) J. Electron. Test.(149) DATE(95) IEEE Trans. Very Large Scale I...(87) ATS(85) IROS(83) ICRA(80) DAC(79) VLSI Design(72) IEEE Trans. Computers(69) Sensors(69) DFT(68) More (+10 of total 1786)
GrowBag graphs for keyword ? (Num. hits/coverage)

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The graphs summarize 3962 occurrences of 1873 keywords

Results
Found 7741 publication records. Showing 7739 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
153Kwang-Ting Cheng Partial scan designs without using a separate scan clock. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock
123Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen Peak-power reduction for multiple-scan circuits during test application. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF peak-power reduction, multiple scan chain based circuits, peak periodicity, peak width, power waveforms, scan-based circuits, delay buffers, interleaving scan technique, data output, logic testing, logic testing, delays, integrated circuit testing, application specific integrated circuits, SOC, boundary scan testing
116Yu Huang 0005, Ruifeng Guo, Wu-Tung Cheng, James Chien-Mo Li Survey of Scan Chain Diagnosis. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
106Abhijit Jas, Bahram Pouya, Nur A. Touba Virtual Scan Chains: A Means for Reducing Scan Length in Cores. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Compression/Decompression, Virtual Scan, Built-In Self-Test, Mapping, Design-for-Testability, LFSR, System Integrator, Integrated Circuits, Integrated Circuits, Scan Chains, Embedded Cores, Digital Testing, Reseeding
102Kuen-Jong Lee, Tsung-Chu Huang An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF multiple scan chains, interleaving scan, test power reduction, peak power reduction
101Xijiang Lin, Yu Huang 0005 Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells. Search on Bibsonomy J. Electron. Test. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Scan shift, Low power test, Scan test, Signal probability
101Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen Cost-free scan: a low-overhead scan path design methodology. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Testing, DFT, Scan design
96Dong Xiang, Mingjing Chen, Hideo Fujiwara Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Random testability, scan enable signal, weighted random testing, scan-based BIST
96Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees. Search on Bibsonomy J. Electron. Test. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF scan tree, logic testing, design for testability, sequential circuit
92Robert B. Norwood, Edward J. McCluskey Synthesis-for-scan and scan chain ordering. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF synthesis-for-scan procedure, scan chain ordering, testable circuit design, beneficial scan, VLSI, logic testing, integrated circuit testing, design for testability, logic design, sequential circuits, logic synthesis, flip-flops, integrated circuit design, integrated logic circuits, test strategy, boundary scan testing, functional specifications
90Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen Cost-free scan: a low-overhead scan path design. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
87Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita Partial scan design and test sequence generation based on reduced scan shift method. Search on Bibsonomy J. Electron. Test. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF partial scan circuit, short test sequence, reduced scan shift, scan design, test sequence generation
86Subhrajit Bhattacharya, Sujit Dey H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF H-SCAN, parallel register connectivity, on-chip response, sequential test vectors, combinational test vectors, combinational ATPG program, RT-level design, integrated circuit testing, design for testability, automatic testing, fault simulation, fault coverage, test pattern generation, comparator, boundary scan testing, test application time, high-level design, area overhead, testing methodology
85Nilabha Dev, Sandeep Bhatia, Subhasish Mukherjee, Sue Genova, Vinayak Kadam A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
85Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy Multiple Scan Tree Design with Test Vector Modification. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
85Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy On reducing test application time for scan circuits using limited scan operations and transfer sequences. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
85Dong Xiang, Kaiwei Li, Hideo Fujiwara Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
85Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita Reducing Scan Shifts Using Folding Scan Trees. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
84Dong Xiang, Shan Gu, Jia-Guang Sun, Yu-Liang Wu A cost-effective scan architecture for scan testing with non-scan test power and test application cost. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
83Irith Pomeranz, Sudhakar M. Reddy Reducing test application time for full scan circuits by the addition of transfer sequences. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF transfer sequences, primary input vectors, scan-in operation, scan-out operation, static compaction procedure, compaction levels, fault diagnosis, logic testing, design for testability, fault detection, automatic testing, boundary scan testing, test set, test application time, full scan circuits
80Dong Xiang, Mingjing Chen, Jia-Guang Sun Scan BIST with biased scan test signals. Search on Bibsonomy Sci. China Ser. F Inf. Sci. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF random testability, test signal, biased random testing, scan-based BIST
80Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara Improving test effectiveness of scan-based BIST by scan chain partitioning. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
80Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure. Search on Bibsonomy DELTA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
80Irith Pomeranz, Sudhakar M. Reddy On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains. Search on Bibsonomy ICCD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
78Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda Scan insertion criteria for low design impact. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF scan insertion criteria, design impact, flip-flop ordering, capacitance constraints, layout information, Italtel Design Environment, logic testing, integrated circuit testing, sequential circuits, automatic testing, application specific integrated circuits, logic CAD, flip-flops, integrated circuit design, power dissipation, partial scan, design flow, boundary scan testing, scan chain, capacitance, full scan
76Ozgur Sinanoglu Low Cost Scan Test by Test Correlation Utilization. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF test correlation, scan architecture design, test data compression, scan-based testing
76Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee Functional Scan Chain Testing. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF functional scan chain, alternating sequence, scan chain testing, design for testability, test point insertion
76Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Scan forest, test application cost, test data volume, test power
76Nur A. Touba, Edward J. McCluskey Applying two-pattern tests using scan-mapping. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF scan-mapping, combinational mapping logic, logic testing, built-in self test, built-in self-testing, fault coverage, delay faults, pseudo-random testing, deterministic testing, two-pattern tests
75Geewhun Seok, Il-soo Lee, Tony Ambler, Baxter F. Womack An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing Constraint. Search on Bibsonomy DFT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
75Abhijit Jas, Bahram Pouya, Nur A. Touba Test data compression technique for embedded cores using virtual scan chains. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
75Irith Pomeranz Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
73Hao Zheng, Kewal K. Saluja, Rajiv Jain Test application time reduction for scan based sequential circuits. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF scan based sequential circuits, single clock configuration, nonscan flip-flops, test vector length, nonatomic two-clock scan method, test generation environment, logic testing, sequential circuits, flip-flops, clocks, partial scan, boundary scan testing, test application time
73Sridhar Narayanan, Melvin A. Breuer Asynchronous multiple scan chain. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF asynchronous multiple scan chains, scan flip-flops, control complexity, I/O pin count, DFT method, logic IC, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, flip-flops, integrated logic circuits, scan designs, boundary scan testing, test application time
72Seiken Yano Unified scan design with scannable memory arrays. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF unified scan design, scannable memory arrays, single scan path, scan operation time, scannable register file, fault diagnosis, design for testability, design-for-testability, automatic testing, logic CAD, flip-flops, flip-flops, arrays, shift registers, integrated memory circuits
71Ozgur Sinanoglu Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations. Search on Bibsonomy J. Electron. Test. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Test power reduction, Scan power reduction, Serial transformations, Scan chain modification, Design for testability, Core-based testing
71Elizabeth M. Rudnick, Janak H. Patel A genetic approach to test application time reduction for full scan and partial scan circuits. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF partial scan circuits, design-for-testability techniques, compact test set generation, genetic algorithms, genetic algorithms, logic testing, design for testability, logic design, sequential circuits, combinational circuits, DFT, flip-flops, test application time reduction, full scan circuits
71Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie 0001 Scan-chain design and optimization for three-dimensional integrated circuits. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF scan-chain design, genetic algorithm, integer linear programming, randomized rounding, LP relaxation, 3D ICs
71Min Gyung Kang, Juan Caballero, Dawn Xiaodong Song Distributed Evasive Scan Techniques and Countermeasures. Search on Bibsonomy DIMVA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF scan detection, distributed scanning, information-hiding, evasion
70Zhen Chen, Dong Xiang, Boxue Yin A power-effective scan architecture using scan flip-flops clustering and post-generation filling. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF test, low power, design for test, scan design
70Hideo Fujiwara, Akihiro Yamamoto Parity-scan design to reduce the cost of test application. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
70Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips. Search on Bibsonomy VTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF scan-based DFT, security, detection probability, low overhead, cryptographic hardware
70Dong Xiang, Ming-Jing Chen, Kaiwei Li, Yu-Liang Wu Scan-Based BIST Using an Improved Scan Forest Architecture. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
70Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
69Irith Pomeranz, Sudhakar M. Reddy Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
67Seongmoon Wang, Wenlong Wei A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF peak current reduction, average power dissipation, clock tree construction, special scan cells, scan chain reordering, ATPG, scan designs
67Kee Sup Kim, Charles R. Kime Partial scan flip-flop selection by use of empirical testability. Search on Bibsonomy J. Electron. Test. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF scan flip-flop selection, serial scan, design for testability, testability, partial scan
67Samantha Edirisooriya, Geetani Edirisooriya Diagnosis of scan path failures. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF scan path failures, scan based diagnostic schemes, faulty circuits, logic circuitry, scan chain fault diagnosis, fault diagnosis, logic testing, integrated circuit testing, design for testability, combinational circuits, integrated logic circuits
66Yong-sheng Cheng, Zhiqiang You, Jishun Kuang Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction. Search on Bibsonomy DELTA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF full scan testing, scan tree, routing complexity, test response data volume, design-for-testability
66Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita Test sequence compaction by reduced scan shift and retiming. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF reduced scan shift, full scan designed circuits, computational complexity, logic testing, timing, transformation, design for testability, sequential circuits, sequential circuit, logic CAD, flip-flops, flip-flops, retiming, computing time, test length, test sequence generation, test sequence compaction
66Prab Varma, Tushar Gheewala The economics of scan-path design for testability. Search on Bibsonomy J. Electron. Test. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF state retention problem, Design for testability, scan, partial scan, test economics, life-cycle costs
66Sunghoon Chun, Taejin Kim, YongJoon Kim, Sungho Kang 0001 An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation. Search on Bibsonomy VTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Scan chain based test, Diagnosis, Symbolic Simulation
65Dong Xiang, Ming-Jing Chen, Hideo Fujiwara Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Test signal, random testability, weighted random testing, scan-based BIST
65Wei Li 0023, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
65Michael Cogswell, Shazia Mardhani, Kevin Melocco, Hina Arora A Structured Graphical Tool for Analyzing Boundary Scan Violations. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
65Soo Young Lee, Kewal K. Saluja Test application time reduction for sequential circuits with scan. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
65Irith Pomeranz, Sudhakar M. Reddy Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs. Search on Bibsonomy VTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
65Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li 0036, Krishnendu Chakrabarty Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
65Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
65Ozgur Sinanoglu, Alex Orailoglu Modeling Scan Chain Modifications For Scan-in Test Power Minimization. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
64Nicola Nicolici, Bashir M. Al-Hashimi Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
61Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li Layout-aware scan chain reorder for launch-off-shift transition test coverage. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF scan chain ordering, test generation, transition faults, Scan test
61Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch Power-Driven Routing-Constrained Scan Chain Design. Search on Bibsonomy J. Electron. Test. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF scan chain design, DfT, low power testing, scan testing
61Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier Enhanced Reduced Pin-Count Test for Full-Scan Design. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF reduced pin-count test, core test, design for testability, ATE, boundary-scan test, scan test
61Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic Securing Designs against Scan-Based Side-Channel Attacks. Search on Bibsonomy IEEE Trans. Dependable Secur. Comput. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Security and Privacy Protection, Scan-Based Design, Secure Design, Reliability and Testing
61Lanjia Wang, Hai-Xin Duan, Xing Li 0001 Port Scan Behavior Diagnosis by Clustering. Search on Bibsonomy ICICS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF port scan detection, clustering, network security
61Bo Yang 0010, Kaijie Wu 0001, Ramesh Karri Secure scan: a design-for-test architecture for crypto chips. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF crypto hardware, scan-based DFT, security, testability
61Xiaodong Zhang 0010, Kaushik Roy 0001 Power Reduction in Test-Per-Scan BIST. Search on Bibsonomy IOLTW The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Test-per-scan, Low Power BIST, Testing, Low Power, BIST, Weighted Random Pattern
61Jayabrata Ghosh-Dastidar, Nur A. Touba A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF built-in self-test Scan Chains, Design-for-Diagnosis, Multi-Input Signature Register, Design-for-Testability, LFSR, Integrated Circuits, Integrated Circuits, Digital Testing, Design-for-Debug
61Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik Integration of partial scan and built-in self-test. Search on Bibsonomy J. Electron. Test. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF test points, built-in self-test, design for testability, partial scan
60Yu-Ze Wu, Mango Chia-Tso Chao Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes. Search on Bibsonomy VTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF signal transitions, correlation, reordering, scan-chain
60Xiaoxia Wu, Paul Falkenstern, Yuan Xie 0001 Scan chain design for three-dimensional integrated circuits (3D ICs). Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
60Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
60Nisar Ahmed, Mohammad Tehranipoor Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique. Search on Bibsonomy DFT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
60Irith Pomeranz, Sudhakar M. Reddy Autoscan: a scan design without external scan inputs or outputs. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
60Shih Ping Lin 0001, Chung-Len Lee 0001, Jwu E. Chen A Scan Matrix Design for Low Power Scan-Based Test. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
60Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy 0001 Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
60Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
60Seongmoon Wang, Xiao Liu, Srimat T. Chakradhar Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
60Irith Pomeranz Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
60Sandeep Bhatia, Niraj K. Jha Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
56Roberto Bevacqua, Luca Guerrazzi, Franco Fummi SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation. Search on Bibsonomy EUROMICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF test storage, scan-path techniques, Built-In Self Test, design for testability, Design for Testability, BIST, test pattern generation, SCAN, test sequences
56Hardy J. Pottinger, Chien-Yuh Lin Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education
56Arun Balakrishnan, Srimat T. Chakradhar Partial scan design for technology mapped circuits. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF technology mapped circuits, scan flip-flops selection, multiple memory elements, library block, integer linear program formulation, production VLSI circuits, VLSI, graph theory, linear programming, design for testability, integer programming, logic design, logic CAD, VLSI design, flip-flops, integrated circuit design, circuit CAD, integrated logic circuits, functional specifications, partial scan design
56Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos Efficient partial scan cell gating for low-power scan-based testing. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF partial gating, scan cell gating, Low-power testing, scan-based testing
56Lifeng He, Yuyan Chao, Kenji Suzuki 0001, Hidenori Itoh A Run-Based One-Scan Labeling Algorithm. Search on Bibsonomy ICIAR The full citation details ... 2009 DBLP  DOI  BibTeX  RDF label equivalence, raster scan, connected component, run-length encoding, Labeling algorithm
56Hong-Sik Kim, Sungho Kang 0001, Michael S. Hsiao A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment. Search on Bibsonomy J. Electron. Test. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Keyword System on a chip, Test compression, Low power testing, Scan testing
56Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. Search on Bibsonomy VTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Faults in scan cells, stuck-at and stuck-on faults
56Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding Scan chain clustering for test power reduction. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF test, low power, design for test, scan design
56Wei-Lun Wang, Kuen-Jong Lee An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF mixed-mode pattern generation, built-in self-test, power consumption, test application time, scan chain
56Sandeep Bhatia, Prab Varma Test Compaction in a Parallel Access Scan Environment. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Test Vector Compaction, Design for Testability, Scan
56Sándor P. Fekete, Joseph S. B. Mitchell, Christiane Schmidt 0001 Minimum Covering with Travel Cost. Search on Bibsonomy ISAAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
56Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang Broadcasting test patterns to multiple circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
55Zhen Chen, Boxue Yin, Dong Xiang Conflict driven scan chain configuration for high transition fault coverage and low test power. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
55Fei Wang, Yu Hu 0001, Huawei Li 0001, Xiaowei Li 0001 A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
55Xiaoding Chen, Michael S. Hsiao An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
55Li Zhang 0006, Wen Gao 0001, Qiang Wang 0011, Debin Zhao Macroblock-Level Adaptive Scan Scheme for Discrete Cosine Transform Coefficients. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
55Irith Pomeranz, Sudhakar M. Reddy Improved n-Detection Test Sequences Under Transparent Scan. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
55Yu Huang 0005, Keith Gallie Diagnosis of defects on scan enable and clock trees. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
55Minsik Cho, David Z. Pan PEAKASO: Peak-Temperature Aware Scan-Vector Optimization. Search on Bibsonomy VTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
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