Search results for "Verilog-A"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
37	Ondrej Subrt, Petr Struhovský, Pravoslav Martínek, Jirí Hospodka	Virtual Testing Environment for A/D Converters in Verilog-A and Maple Platform.	DDECS	2008	DBLP DOI BibTeX RDF
36	Qinlin Chen, Nairen Zhang, Jinpeng Wang, Tian Tan 0001, Chang Xu 0001, Xiaoxing Ma, Yue Li 0006	The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog.	Proc. ACM Program. Lang.	2023	DBLP DOI BibTeX RDF
36	Yicong Shao, Chao Wang, Jiajie Huang, Wangzilu Lu, Zhiwen Gu, Longfan Li, Yuhang Zhang, Jian Zhao 0004, Wei Mao, Yongfu Li 0002	V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation.	APCCAS	2023	DBLP DOI BibTeX RDF
29	Weisheng Zhao, Guillaume Agnus, Vincent Derycke, Arianna Filoramo, Christian Gamrat, Jean-Philippe Bourgoin	Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design.	NanoNet	2009	DBLP DOI BibTeX RDF	Hybrid Nano/CMOS circuits, OG-CNTFET, Verilog-A, Carbon Nanotube, Functional Modelling
28	Junjun Li, Sopan Joshi, Ryan Barnes, Elyse Rosenbaum	Compact modeling of on-chip ESD protection devices using Verilog-A.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
19	Rajdeep Mukhopadhyay, Subrat Kumar Panda, Pallab Dasgupta, John Gough	Instrumenting AMS assertion verification on commercial platforms.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	OVL, SVA, integrated mixed signal design, verification library, simulation, Assertion
19	Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke	Word level predicate abstraction and refinement for verifying RTL verilog.	DAC	2005	DBLP DOI BibTeX RDF	SAT, predicate abstraction, verilog
19	Jean Oudinot	The Most Complete Mixed-Signal Simulation Solution with ADVance MS.	PATMOS	2003	DBLP DOI BibTeX RDF
19	Huibiao Zhu, Jonathan P. Bowen, Jifeng He 0001	Deriving Operational Semantics from Denotational Semantics for Verilog.	APSEC	2001	DBLP DOI BibTeX RDF
19	Akira Matsuzawa	High Quality Analog CMOS and Mixed Signal LSI Design.	ISQED	2001	DBLP DOI BibTeX RDF
18	Dias Azhigulov, Zeqin Lu, James Pond, Lukas Chrostowski, Sudip Shekhar	Enabling data-driven and bidirectional model development in Verilog-A for photonic devices.	CoRR	2024	DBLP DOI BibTeX RDF
18	Hugh D. Morison, Jagmeet Singh, Nayem Al Kayed, A. Aadhi, Maryam Moridsadat, Marcus Tamura, Alexander N. Tait, Bhavin J. Shastri	Nonlinear dynamics in neuromorphic photonic networks: physical simulation in Verilog-A.	CoRR	2024	DBLP DOI BibTeX RDF
18	Andrea Ballo, Alfio Dario Grasso, Marco Privitera	Demystifying Regulating Active Rectifiers for Energy Harvesting Systems: A Tutorial Assisted by Verilog-A Models.	IEEE Access	2023	DBLP DOI BibTeX RDF
18	C. Mukherjee 0001, Djeber Guendouz, Marina Deng, H. Bertin, Antoine Bobin, Nicolas Vaissiere, Christophe Caillaud, Akshay M. Arabhavi, Rimjhim Chaudhary, Olivier Ostinelli, Colombo R. Bolognesi, Patrick Mounaix, Cristell Maneux	SPICE Modeling in Verilog-A for Photo-Response in UTC-Photodiodes Targeting Beyond-5G Circuit Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
18	Nicola Dall'Ora, Sadia Azam, Enrico Fraccaroli, Renaud Gillon, Franco Fummi	Verilog-A Implementation of Generic Defect Templates for Analog Fault Injection.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
18	Andrea La Gala, Lorenzo Stevenazzi, Elia A. Vallicelli, Mattia Tambaro, Stefano Vassanelli, Andrea Baschirotto, Marcello De Matteis	Hodgkin-Huxley Verilog-A Electrical Neuron Membrane Model.	ICECS 2022	2022	DBLP DOI BibTeX RDF
18	Rafael Vieira, Fábio Passos, Ricardo Povoa, Ricardo Martins 0003, Nuno Horta, Jorge Guilherme, Nuno Lourenço 0003	Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling.	SMACD	2022	DBLP DOI BibTeX RDF
18	David Maldonado, Francisco Jiménez-Molinos, Juan Bautista Roldán, M. B. González, Francesca Campabadal	An enhanced Verilog-A compact model for bipolar RRAMs including transient thermal effects and series resistance.	DCIS	2022	DBLP DOI BibTeX RDF
18	Jean-Baptiste Kammerer, Maroua Garci, Achraf Kaïd, Fabrice Roqueta	Multidomain Modeling for Reliability Evaluation of Devices and Microsystems Using Verilog-A.	MIXDES	2022	DBLP DOI BibTeX RDF
18	Mike Brinson, Daniel Tomaszewski	Advances in Qucs-S Schematic Capture for SPICE and Verilog-A Device Modelling and Circuit Simulation.	MIXDES	2022	DBLP DOI BibTeX RDF
18	Angeliki Tataridou, Gérard Ghibaudo, Christoforos G. Theodorou	VERILOR: A Verilog-A Model of Lorentzian Spectra for Simulating Trap-related Noise in CMOS Circuits.	ESSDERC	2021	DBLP DOI BibTeX RDF
18	Jie Liu, Yu Ban	A parametric model for a high speed heterogeneous current-steering digital-to-analog converter based on compiled Verilog-A and SPICE.	ICTA	2021	DBLP DOI BibTeX RDF
18	Md Azmot Ullah Khan, Naheem Olakunle Adesina, Jian Xu	Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design.	CCECE	2021	DBLP DOI BibTeX RDF
18	Binbin Yang, Daniel Arumí, Salvador Manich, Álvaro Gómez-Pau, Rosa Rodríguez-Montañés, Juan Bautista Roldán, Mireia Bargallo González, Francesca Campabadal, Liang Fang	Simulation of serial RRAM cell based on a Verilog-A compact model.	DCIS	2021	DBLP DOI BibTeX RDF
18	Md Jubayer Shawon, Vishal Saxena	Rapid Simulation of Photonic Integrated Circuits Using Verilog-A Compact Models.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
18	Juan Manuel López-Martínez, Ricardo Carmona-Galán, Ángel Rodríguez-Vázquez	Photon-Detection Timing-Jitter Model in Verilog-A.	ISCAS	2020	DBLP DOI BibTeX RDF
18	Renzo Nicolas Alsim, Anastacia Ballesil-Alvarez, Maria Theresa G. de Leon, Marc D. Rosales, Maria Patricia Rouelli Sabino-Santos, Christopher Santos, John Richard E. Hizon	A Top-Down Approach for Low Noise Amplifier Design using Verilog-A.	ISOCC	2020	DBLP DOI BibTeX RDF
18	Arriel Ting, Anastacia B. Alvarez, Maria Theresa G. de Leon, Marc D. Rosales, Maria Patricia Rouelli Sabino-Santos, John Richard E. Hizon, Christopher Santos	Designing a Class E Power Amplifier through Modeling in Verilog-A.	ISOCC	2020	DBLP DOI BibTeX RDF
18	Zoltan Huszka, Kund Molnar	Suppressing derivatives of selected variables in Verilog-A.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
18	Nicola Lupo, Eduardo Pérez, Christian Wenger, Franco Maloberti, Edoardo Bonizzoni	Analysis of Parasitic Effects in Filamentary-Switching Memristive Memories Using an Approximated Verilog-A Memristor Model.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
18	Wladek Grabinski, Ahmed Abo-Elhadid, Marek Mierzwinski, Laurent Lemaitre, Mike Brinson, Christophe Lallement, Jean-Michel Sallese, Sadayuki Yoshitomi, Paul Malisse, Henri Oguey, Stefan Cserveny, Marcelo Antonio Pavanello, Christian C. Enz, François Krummenacher, Eric A. Vittoz, Michelly de Souza, Daniel Tomaszewski, Jolanta Malesinska, Grzegorz Gluszko, Matthias Bucher, Nikolaos Makris, Aristeidis Nikolaou	FOSS EKV2.6 Verilog-A Compact MOSFET Model.	ESSDERC	2019	DBLP DOI BibTeX RDF
18	Faten Ouaja Rziga, Khaoula Mbarek, Sami Ghedira, Kamel Besbes	A Verilog-A based RRAM Switching Model for Simulation and Analysis.	ICCAD	2019	DBLP DOI BibTeX RDF
18	Md Jubayer Shawon, Vishal Saxena	Rapid Simulation of Photonic Integrated Circuits using Verilog-A Compact Models.	MWSCAS	2019	DBLP DOI BibTeX RDF
18	Patrick Döll, Oner Hanay, Erkan Bayram, Renato Negra	Verilog-A based Behavioral Modeling of an FBMC Transmitter.	SMACD	2019	DBLP DOI BibTeX RDF
18	Imran Bashir, Panagiotis Giounanlis, Elena Blokhina, Dirk Leipold, Krzysztof Pomorski, Robert Bogdan Staszewski	A Verilog-A Model of the Shuttle of an Electron in a Two Quantum-Dot System.	NEWCAS	2019	DBLP DOI BibTeX RDF
18	Mike Brinson	FOSS Compact Model Prototyping with Verilog-A Equation-Defined Devices (VAEDD).	MIXDES	2019	DBLP DOI BibTeX RDF
18	Eric Schkufza, Michael Wei, Christopher J. Rossbach	Just-In-Time Compilation for Verilog: A New Technique for Improving the FPGA Programming Experience.	ASPLOS	2019	DBLP DOI BibTeX RDF
18	Ailin Zhang, Guoyong Shi	A fast symbolic SNR computation method and its Verilog-A implementation for Sigma-Delta modulator design optimization.	Integr.	2018	DBLP DOI BibTeX RDF
18	Ioannis Messaris, Alexander Serb, Spyros Stathopoulos, Ali Khiat, Spyridon Nikolaidis 0001, Themistoklis Prodromakis	A Data-Driven Verilog-A ReRAM Model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
18	Juan Manuel Lopez-Martinez, Ion Vornicu, Ricardo Carmona-Galán, Ángel Rodríguez-Vázquez	An Experimentally-Validated Verilog-A SPAD Model Extracted from TCAD Simulation.	ICECS	2018	DBLP DOI BibTeX RDF
18	Charly Meyer, Andre Chanthbouala, Soren Boyn, Jean Tomas, Vincent Garcia, Manuel Bibes, Stephane Fusil, Julie Grollier, Sylvain Saïghi	Verilog-A model of ferroelectric memristors dedicated to neuromorphic design.	ICECS	2018	DBLP DOI BibTeX RDF
18	Nicola Lupo, Edoardo Bonizzoni, Eduardo Pérez, Christian Wenger, Franco Maloberti	An Approximated Verilog-A Model for Memristive Devices.	ISCAS	2018	DBLP DOI BibTeX RDF
18	Gleb Krylov, Eby G. Friedman	Behavioral Verilog-A Model of Superconductor-Ferromagnetic Transistor.	ISCAS	2018	DBLP DOI BibTeX RDF
18	An-Sam Peng, Lin-Kun Wu	An Improved EEHEMT RF Noise Model for 0.25 µm InGaP pHEMT Transistor Using Verilog-A Language.	IEICE Trans. Electron.	2017	DBLP DOI BibTeX RDF
18	Shubhankar Majumdar, Dhrubes Biswas	Evaluating substrate's effect on RF switch performance via Verilog-A GaN HEMT model.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
18	Ioannis Messaris, Alexander Serb, Ali Khiat, Spyridon Nikolaidis 0001, Themistoklis Prodromakis	A compact Verilog-A ReRAM switching model.	CoRR	2017	DBLP BibTeX RDF
18	Jesús M. Muñoz-Pacheco, Víctor R. González-Díaz, Luz del Carmen Gómez-Pavón, Sergio Romero-Camacho, Francisco Sánchez-Guzmán, J. Mateo-Juárez, L. Delgado-Toral, José Arturo Cocoma-Ortega, Arnulfo Luis-Ramos, Plácido Zaca-Morán, Esteban Tlelo-Cuautle	Behavioral Modeling of Chaos-Based Applications by Using Verilog-A.	Fractional Order Control and Synchronization of Chaotic Systems	2017	DBLP DOI BibTeX RDF
18	Colin C. McAndrew	SPICE modeling in Verilog-A: Successes and challenges: Invited paper.	ESSDERC	2017	DBLP DOI BibTeX RDF
18	Francesco Maria Puglisi, Nicolo Zagni, Luca Larcher, Paolo Pavan	A new verilog-A compact model of random telegraph noise in oxide-based RRAM for advanced circuit design.	ESSDERC	2017	DBLP DOI BibTeX RDF
18	Ahmed Zaky, Mohamed Shehata, Yehea Ismail, Hassan Mostafa	Characterization and model validation of triboelectric nanogenerators using Verilog-A.	MWSCAS	2017	DBLP DOI BibTeX RDF
18	Nivasan Yogeswaran, Z. Tang, Vincenzo Vinciguerra, Ravinder Dahiya	Bending effects in a flexible dual gated graphene FET: A Verilog-A model implementation.	ECCTD	2017	DBLP DOI BibTeX RDF
18	Nishtha Sharma, Andrew Marshall, Jonathan Bird	Verilog - A compact model of a ME-MTJ based XNOR/NOR gate.	NANOARCH	2017	DBLP DOI BibTeX RDF
18	Satish Maheshwaram, Om. Prakash, Mohit Sharma 0003, Anand Bulusu, Sanjeev Manhas	Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance.	VDAT	2017	DBLP DOI BibTeX RDF
18	P. Sideris, Stilianos Siskos, George G. Malliaras	Verilog-A modeling of Organic Electrochemical Transistors.	MOCAST	2017	DBLP DOI BibTeX RDF
18	Anindya Mukherjee, Andreas Pawlak, Michael Schröter, Didier Céli, Zoltan Huszka	Implementation and quality testing for compact models implemented in Verilog-A.	DATE	2016	DBLP BibTeX RDF
18	Davide Lena, Michelangelo Grosso, Alberto Bocca, Alberto Macii, Salvatore Rinaudo	A compact IGBT electro-thermal model in Verilog-A for fast system-level simulation.	IECON	2016	DBLP DOI BibTeX RDF
18	Nil Franch, Oscar Alonso, Ángel Diéguez, Salvador Hidalgo, Iván Vila	A Verilog-A model of a silicon resistive strip for particle detectors.	SMACD	2016	DBLP DOI BibTeX RDF
18	Raimon Casanova, Sebastian Grinstein	A Verilog-A model of a charge sensitive amplifier for a HV-CMOS pixel sensor.	SMACD	2016	DBLP DOI BibTeX RDF
18	Gianluca Giustolisi, Gaetano Palumbo, Paolo Finocchiaro, Alfio Pappalardo	Verilog-a modeling of Silicon Photo-Multipliers.	ISCAS	2016	DBLP DOI BibTeX RDF
18	Md. Fahad, Zhou Zhao, Ashok Srivastava, Lu Peng 0001	Modeling of Graphene Nanoribbon Tunnel Field Effect Transistor in Verilog-A for Digital Circuit Design.	iNIS	2016	DBLP DOI BibTeX RDF
18	Maria Helena Fino	Verilog-A compact model of integrated tapered spiral inductors.	MIXDES	2016	DBLP DOI BibTeX RDF
18	Om. Prakash, Satish Maheshwaram, Mohit Sharma 0003, Anand Bulusu, A. K. Saxena, S. K. Manhas	A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation.	VDAT	2016	DBLP DOI BibTeX RDF
18	Oana Moldovan, François Lime, Benjamín Iñíguez	A complete and Verilog-A compatible Gate-All-Around long-channel junctionless MOSFET model implemented in CMOS inverters.	Microelectron. J.	2015	DBLP DOI BibTeX RDF
18	Arnab Biswas, Luca De Michielis, Antonios Bazigos, Adrian Mihai Ionescu	Compact modeling of DG-Tunnel FET for Verilog-A implementation.	ESSDERC	2015	DBLP DOI BibTeX RDF
18	Grazvydas Ziemys, Andrew Giebfried, Markus Becherer, Irina Eichwald, Doris Schmitt-Landsiedel, Stephan Breitkreutz-v. Gamm	Modelling and simulation of nanomagnetic logic with cadence virtuoso using Verilog-A.	ESSDERC	2015	DBLP DOI BibTeX RDF
18	Po-Yu Kuo, Liao-Fong Sie	Analyze the behavior model based on Verilog-A for Sallen-Key low-pass filter.	ICCE-TW	2015	DBLP DOI BibTeX RDF
18	Mike Brinson, Vadim Kuznetsov	Qucs equation-defined and Verilog-A RF device models for harmonic balance circuit simulation.	MIXDES	2015	DBLP DOI BibTeX RDF
18	Elise Rosati, Morgan Madec, Jean-Baptiste Kammerer, Abir Rezgui, Christophe Lallement, Jacques Haiech	Verilog-A compact space-dependent model for biology.	MIXDES	2015	DBLP DOI BibTeX RDF
18	M. Santhanalakshmi, K. Yasoda	Verilog-A implementation of energy-efficient SAR ADCs for biomedical application.	VDAT	2015	DBLP DOI BibTeX RDF
18	Yuanfan Yang, Jimson Mathew, Rishad A. Shafik, Dhiraj K. Pradhan	Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis.	IEEE Embed. Syst. Lett.	2014	DBLP DOI BibTeX RDF
18	Ahmed A. M. Emara, Mohamed M. Aboudina, Hossam A. H. Fahmy	Corrected and accurate Verilog-A for linear dopant drift model of memristors.	MWSCAS	2014	DBLP DOI BibTeX RDF
18	Kehan Zhu, Vishal Saxena, Wan Kuang	Compact Verilog-A modeling of silicon traveling-wave modulator for hybrid CMOS photonic circuit design.	MWSCAS	2014	DBLP DOI BibTeX RDF
18	Maria-Anna Chalkiadaki, Cédric Valla, Frédéric Poullet, Matthias Bucher	Why- and how- to integrate Verilog-A compact models in SPICE simulators.	Int. J. Circuit Theory Appl.	2013	DBLP DOI BibTeX RDF
18	Sandeep Miryala, Mehrdad Montazeri, Andrea Calimera, Enrico Macii, Massimo Poncino	A verilog-a model for reconfigurable logic gates based on graphene pn-junctions.	DATE	2013	DBLP DOI BibTeX RDF
18	George Gal, Omar Abdelfattah, Gordon W. Roberts	A 30-40 GHz fractional-N frequency synthesizer development using a Verilog-A high-level design methodology.	MWSCAS	2012	DBLP DOI BibTeX RDF
18	Darshan A. Dimplu, Fei Wang	Behavior Modeling of Programmable Metallization Cell Using Verilog-A.	ITNG	2012	DBLP DOI BibTeX RDF
18	Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo	Verilog-A modeling of SPAD statistical phenomena.	ISCAS	2011	DBLP DOI BibTeX RDF
18	Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi	Fault injection in mixed-signal environment using behavioral fault modeling in Verilog-A.	BMAS	2010	DBLP DOI BibTeX RDF
18	Colin C. McAndrew, Zoltan Huszka, Geoffrey J. Coram	Bipolar Transistor Excess Phase Modeling in Verilog-A.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
18	Kwan-Hee Jo, Ji-Hye Bong, Kyeong-Sik Min, Sung-Mo Kang	A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs.	IEICE Electron. Express	2009	DBLP DOI BibTeX RDF
18	Mario Auer, Christoph Wurzinger	Verhaltensmodellierung von Delta-Sigma-ADCs unter Verwendung von Verilog-A.	Elektrotech. Informationstechnik	2008	DBLP DOI BibTeX RDF
18	Flavius Gruian, Mark Westmijze	VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture.	SAC	2008	DBLP DOI BibTeX RDF	embedded systems, java processor, Bluespec
18	Susovon Samanta, Srikanth Pam, H. Mohan Geddada, Siddhartha Mukhopadhyay	An Improved Algorithm for Frequency Response Analysis of Switching Convertes and its Implementation in Verilog-A.	ICIIS	2008	DBLP DOI BibTeX RDF
18	Laurent Lemaitre, Colin C. McAndrew	Voltage-controlled-current-source-only verilog-a resistor model for R⩾0.	BMAS	2008	DBLP DOI BibTeX RDF
18	Albrecht Jander, Linda Engelbrecht, Pallavi Dhagat	Dynamic Verilog - A Model of a Magnetoresistive Spin Valve.	BMAS	2008	DBLP DOI BibTeX RDF
18	Keiichiro Ishihara, Takeyuki Tsuruma, Yasuhiko Iguchi, Takeshi Sawada, Makoto Watanabe, Yasuhito Maki	Implementation of Optical Response of Thin Film Transistor with Verilog-A for Mobile LCD Applications.	BMAS	2008	DBLP DOI BibTeX RDF
18	Yi Wang, Yikai Wang, Lenian He	Behavioral modeling for operational amplifier in sigma-delta modulators with Verilog-A.	APCCAS	2008	DBLP DOI BibTeX RDF
18	Hung-Yuan Chu, Chun-Hung Yang, Chi-Wai Leng, Chien-Hung Tsai	A top-down, mixed-level design methodology for CT BP ΔΣ modulator using verilog-A.	APCCAS	2008	DBLP DOI BibTeX RDF
18	Carl Ebeling, Brian French	Abstract Verilog: A Hardware Description Language for Novice Students.	MSE	2007	DBLP DOI BibTeX RDF
18	Walter Fergusson, Rakesh H. Patel, William Bereza	Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A.	CICC	2007	DBLP DOI BibTeX RDF
18	Maher Assaad, David R. S. Cumming	CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC.	SoC	2007	DBLP DOI BibTeX RDF
18	Shengchao Qin, Wei-Ngan Chin, Jifeng He 0001, Zongyan Qiu	From Statecharts to Verilog: a formal approach to hardware/software co-specification.	Innov. Syst. Softw. Eng.	2006	DBLP DOI BibTeX RDF	Operational semantics, Statecharts, Hardware/software partitioning, Homomorphism, Verilog, Algebraic laws
18	Murali Shanmugasundaram, Shanthi Pavan	Rapid Simulation of Current Steering Digital-to-Analog Converters using Verilog-A.	CICC	2006	DBLP DOI BibTeX RDF
18	Takafumi Yamamoto, Tsutomu Suzuki, Hideki Asai	Concurrent Design of Delta-Sigma Modulator Using Behavioral Modeling and Simulation with the Verilog-A.	CICC	2006	DBLP DOI BibTeX RDF
18	S. I. Ahmed, Kent Orthner, Tadeusz Kwasniewski	Behavioral test benches for digital clock and data recovery circuits using Verilog-A.	CICC	2005	DBLP DOI BibTeX RDF
18	Yuan-Bin Sha, Mu-Shun Matt Lee, Chien-Nan Jimmy Liu	On code coverage measurement for Verilog-A.	HLDVT	2004	DBLP DOI BibTeX RDF
18	Junjun Li, Sopan Joshi, Elyse Rosenbaum	A Verilog-A compact model for ESD protection NMOSTs.	CICC	2003	DBLP DOI BibTeX RDF
18	Kenichi Suzuki, Mitsuhiro Takeda, Atsushi Kamo, Hideki Asai	A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-Domain.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2002	DBLP BibTeX RDF
18	Erik Lauwers, Georges G. E. Gielen, Koen Lampaert, Paolo Miliozzi	High-Level Design Case of a Switched-Capacitor Low-Pass Filter Using Verilog-A.	BMAS	2000	DBLP DOI BibTeX RDF
10	Miloslav Kubar, Ondrej Subrt, Pravoslav Martínek, Jiri Jakovenko	Experience in Virtual Testing of RSD cyclic A/D converters.	DDECS	2009	DBLP DOI BibTeX RDF