|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 129 occurrences of 79 keywords
|
|
|
Results
Found 153 publication records. Showing 153 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
49 | Chengying Mao, Yansheng Lu, Jinlong Zhang |
Regression testing for component-based software via built-in test design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), Seoul, Korea, March 11-15, 2007, pp. 1416-1421, 2007, ACM, 1-59593-480-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
built-in test design, method call graph, component, regression testing, test case selection |
41 | Jonathan Vincent, Graham King, Peter Lay, John Kinghorn |
Principles of Built-In-Test for Run-Time-Testability in Component-Based Software Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Qual. J. ![In: Softw. Qual. J. 10(2), pp. 115-133, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
continuous test, component based software engineering, built-in-test, verification and validation |
33 | Donghoon Han, Abhijit Chatterjee |
Robust Built-In Test of RF ICs Using Envelope Detectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 2-7, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Qi Wang, Mani Soma |
RF Front-end System Gain and Linearity Built-in Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 228-233, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
CMOS RF amplitude detector, gfain measurement, linearity measurement, built-in test, RF test |
33 | Irith Pomeranz, Sudhakar M. Reddy |
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(4), pp. 409-419, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
built-in test generation, synchronous sequential circuits, at-speed testing |
33 | Yingxu Wang 0001, Dilip Patel, Graham King, Ian Court, Geoff Staples, Margaret Ross 0001, Mohamed Fayad |
On built-in test reuse in object-oriented framework design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Comput. Surv. ![In: ACM Comput. Surv. 32(1es), pp. 7, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
frameowrk, framework reuse, test reuse, testable software, software engineering, pattern, built-in test, object-oriented technology, code reuse |
31 | Soumendu Bhattacharya, Abhijit Chatterjee |
Use of Embedded Sensors for Built-In-Test of RF Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 801-809, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Irith Pomeranz, Sudhakar M. Reddy |
Built-in test generation for synchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 421-426, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
comparison units, built-in self-test, synchronous sequential circuits, at-speed test |
31 | Kazumi Hatayama, Michinobu Nakao, Yasuo Sato |
At-Speed Built-in Test for Logic Circuits with Multiple Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 292-297, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Irith Pomeranz, Sudhakar M. Reddy |
A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(11), pp. 1282-1293, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
scan circuits, Built-in testing, Cartesian product |
30 | Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar |
Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(5), pp. 633-636, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham |
Efficient multisine testing of analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 234-238, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
waveform analysis, biquadratic filters, multisine testing, test waveform generation, test confidence, fault-based automatic test pattern generator, successive gradient method, sinusoidal signals, fault coverage maximization, biquadratic filter, AC testing, analog IC, fault diagnosis, built-in self test, integrated circuit testing, automatic testing, analog circuits, built-in test, analogue integrated circuits, linear analog circuits |
29 | Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian |
A Test Interface for Built-In Test of Non-Isolated Scanned Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 371-378, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich |
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 12th European Test Symposium, ETS 2007, Freiburg, Germany, May 20, 2007, pp. 91-96, 2007, IEEE Computer Society, 978-0-7695-2827-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský |
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 300-308, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Irith Pomeranz, Sudhakar M. Reddy |
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 110-115, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Irith Pomeranz, Sudhakar M. Reddy |
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 677-682, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Taewoong Jeon, Hyonwoo Seung, Sungyoung Lee |
Embedding built-in tests in hot spots of an object-oriented framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 37(8), pp. 25-34, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
hook classes, testability, object-oriented framework, built-in test (BIT) |
25 | Achintya Halder, Abhijit Chatterjee |
Specification Based Digital Compatible Built-in Test of Embedded Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 344-, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Dimitrios Kagaris, Spyros Tragoudas |
A multiseed counter TPG with performance guarantee. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 34-39, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
built-in test pattern generators, multiseed counter test pattern generator, low hardware overhead, fast CAD tool, ISCAS'85 benchmarks, hardware/time overhead, built-in self test, performance guarantee, test set generation |
23 | Murali M. R. Gala, Don E. Ross, Karan L. Watson, Beena Vasudevan, Peter Utama |
Built-in self test for C-testable ILA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11), pp. 1388-1398, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
23 | Wolfgang O. Budde |
Modular testprocessor for VLSI chips and high-density PC boards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(10), pp. 1118-1124, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
23 | Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo |
Application of High-Quality Built-In Test to Industrial Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 1003-1012, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham |
Low Cost RF Receiver Parameter Measurement with On-Chip Amplitude Detectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 203-208, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Amplitude detector, RF detector, RF receiver, Built-in test, RF test |
23 | Yingxu Wang 0001, Graham King, Hakan Wickburg |
A Method for Built-in Tests in Component-based Software Maintenance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSMR ![In: 3rd European Conference on Software Maintenance and Reengineering (CSMR '99), 3-5 March 1999, Amsterdam, The Netherlands, pp. 186-189, 1999, IEEE Computer Society, 0-7695-0090-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
maintenance mode, normal mode, test component reuse, reengineering maintenance, Software engineering, software maintenance, software components, built-in test |
22 | Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham |
Built-In Test of RF Mixers Using RF Amplitude Detectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 404-409, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Franck Barbier, Nicolas Belloir |
Component Behavior Prediction and Monitoring through Built-In Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 10th IEEE International Conference on Engineering of Computer-Based Systems (ECBS 2003), 7-10 April 2003, Huntsville, AL, USA, pp. 17-22, 2003, IEEE Computer Society, 0-7695-1917-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Matthias Merdes, Rainer Malaka, Dima Suliman, Barbara Paech, Daniel Brenner, Colin Atkinson 0001 |
Ubiquitous RATs: how resource-aware run-time tests can improve ubiquitous software systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEM ![In: Proceedings of the 6th International Workshop on Software Engineering and Middleware, SEM 2006, Portland, Oregon, USA, November 10, 2006, pp. 55-62, 2006, ACM, 1-59593-585-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MORABIT, resource-aware test (RAT), run-time testing, ubiquitous software, built-in test (BIT) |
21 | Kosuke Nanbara, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu |
Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3DIC ![In: 2015 International 3D Systems Integration Conference, 3DIC 2015, Sendai, Japan, August 31 - September 2, 2015, pp. TS8.22.1-TS8.22.5, 2015, IEEE, 978-1-4673-9385-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich |
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007, pp. 185-190, 2007, IEEE Computer Society, 1-4244-1161-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Irith Pomeranz, Sudhakar M. Reddy |
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 754-759, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Ting-Ting Y. Lin, Huoy-Yu Liou |
A New Framework for Designing: Built-in Test Multichip Modules with Pipelined Test Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 10(4), pp. 38-51, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
21 | Magdy S. Abadir, Melvin A. Breuer |
Test Schedules for VLSI Circuits Having Built-In Test Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(4), pp. 361-367, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
testable design methodology, testing, pipelining, Design for testability, test schedules, test plans |
21 | Ramaswami Dandapani, Janak H. Patel, Jacob A. Abraham |
Design of Test Pattern Generators for Built-In Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1984, Philadelphia, PA, USA, October 1984, pp. 315-319, 1984, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP BibTeX RDF |
|
20 | Dongchao Ji, Bifeng Song, Fei Han |
An Improved KNN Algorithm of Intelligent Built-in Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNSC ![In: Proceedings of the IEEE International Conference on Networking, Sensing and Control, ICNSC 2008, Hainan, China, 6-8 April 2008, pp. 442-445, 2008, IEEE, 978-1-4244-1685-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Daniel Brenner, Colin Atkinson 0001, Rainer Malaka, Matthias Merdes, Barbara Paech, Dima Suliman |
Reducing verification effort in component-based software engineering through built-in testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Syst. Frontiers ![In: Inf. Syst. Frontiers 9(2-3), pp. 151-162, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Run-time testing, MORABIT, Built-in test, Integration test |
17 | Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio |
On-Chip Testing Techniques for RF Wireless Transceivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(4), pp. 268-277, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Wireless Transceivers, Loop-back test, Built-in test, RF test |
17 | Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher, Nishant Patil |
X-Tolerant Test Response Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(6), pp. 566-574, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Testability, Built-In Test, VLSI Test |
17 | Irith Pomeranz, Sudhakar M. Reddy |
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(2), pp. 175-181, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
irredundant faults, built-in test generation, test generation, synchronous sequential circuits, Initial states |
17 | James W. Watterson, Jill J. Hallenbeck |
Modulo 3 Residue Checker: New Results on Performance and Cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(5), pp. 608-612, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
modulo-3 residue code checker, pipelined serial multiplier, concurrent self-test, minimum error latency, multiplier input operands, 4- mu m NMOS, standard cell design, performance evaluation, integrated circuit testing, error detection, automatic testing, digital arithmetic, pipeline processing, multiplying circuits, built in test, field effect integrated circuits, error detection coverage |
17 | Wilfried Daehn, Joachim Mucha |
A Hardware Approach to Self-Testing of Large Programmable Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 30(11), pp. 829-833, 1981. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
programmable logic array (PLA), Built-in test, pattern generation, nonlinear feedback shift registers |
17 | Edward J. McCluskey, Saied Bozorgui-Nesbat |
Design for Autonomous Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 30(11), pp. 866-875, 1981. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
CMOS testing, partitioning, design for testability, test pattern generation, self-test, Built-in test, signature analysis, VLSI testing, stuck- open faults, exhaustive testing |
17 | Norman Benowitz, Donald F. Calhoun, Gary E. Alderson, John E. Bauer, Carl T. Joeckel |
An Advanced Fault Isolation System for Digital Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 24(5), pp. 489-497, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
large-scale integration (LSI) testing, subsystem test, self test, built-in test (BIT), Automatic test equipment (ATE), fault isolation, system maintenance, test response |
16 | Selim Sermet Akbay, Abhijit Chatterjee |
Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 273-290, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Uros Kac, Franc Novak, Srecko Macek, Marina Santo Zarnik |
Alternative Test Methods Using IEEE 1149.4. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 463-467, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Congzhi Huang, Yang Yang |
IFCN-BIASN Based Built-In Test Signal State Recognition for Heavy-Duty Gas Turbine Controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 73, pp. 1-11, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Fei Guan, Wei-Wei Cui, Lian-Feng Li, Weikang Xue, Xiaodong Ma, Dongpao Hong |
A Method of False Alarm Recognition in Built-in Test Considering Its Time Series Characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 68(11), pp. 11428-11437, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Congzhi Huang, Yasong Wang, Guolian Hou, Jianhua Zhang 0007 |
An LSTM-BINN Approach for Built-In Test Analog Signal State Recognition of Heavy-Duty Gas Turbine Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 70, pp. 1-11, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Junyou Shi, Qingjie He, Zili Wang |
Integrated Stateflow-based simulation modelling and testability evaluation for electronic built-in-test (BIT) systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Reliab. Eng. Syst. Saf. ![In: Reliab. Eng. Syst. Saf. 202, pp. 107066, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Konstantinos Poulos, Themistoklis Haniotakis |
A Built In Test circuit for waveform classification at high frequencies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NATW ![In: 29th IEEE North Atlantic Test Workshop, NATW 2020, Albany, NY, USA, June 17-24, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-9699-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Irith Pomeranz |
Storage Based Built-In Test Pattern Generation Method for Close-to-Functional Broadside Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 26th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2020, Napoli, Italy, July 13-15, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-8187-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Matthias Kampmann, Michael A. Kochte, Chang Liu 0010, Eric Schneider, Sybille Hellebrand, Hans-Joachim Wunderlich |
Built-In Test for Hidden Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10), pp. 1956-1968, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Thomas Moon, Hyun Woo Choi, David C. Keezer, Abhijit Chatterjee |
Efficient Built-In Test and Calibration of High Speed Serial I/O Systems Using Monobit Signal Acquisition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 35(6), pp. 809-822, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Badi Guibane, Belgacem Hamdi, Brahim Bensalem, Abdellatif Mtibaa |
A novel efficient TSV built-in test for stacked 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Turkish J. Electr. Eng. Comput. Sci. ![In: Turkish J. Electr. Eng. Comput. Sci. 26(4), pp. 1909-1921, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Jun-Yang Lei, Thomas Moon, Justin Chow, Suresh K. Sitaraman, Abhijit Chatterjee |
A Monobit Built-In Test and Diagnostic System for Flexible Electronic Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 27th IEEE Asian Test Symposium, ATS 2018, Hefei, China, October 15-18, 2018, pp. 191-196, 2018, IEEE, 978-1-5386-9466-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Wen-Hsuan Hsu, Michael Andreas Kochte, Kuen-Jong Lee |
Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(6), pp. 1004-1017, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume, Shyue-Kung Lu |
Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 26th IEEE Asian Test Symposium, ATS 2017, Taipei City, Taiwan, November 27-30, 2017, pp. 242-247, 2017, IEEE Computer Society, 978-1-5386-2437-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Sabyasachi Deyati, Barry J. Muldrey, Byunghoo Jung, Abhijit Chatterjee |
Concurrent built in test and tuning of beamforming MIMO systems using learning assisted performance optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2017, Fort Worth, TX, USA, October 31 - Nov. 2, 2017, pp. 1-10, 2017, IEEE, 978-1-5386-3413-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Widianto, Masaki Hashizume, Shohei Suenaga, Hiroyuki Yotsuyanagi, Akira Ono, Shyue-Kung Lu, Zvi Roth |
A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 99-D(11), pp. 2723-2733, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Athanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld |
Built-in test of millimeter-Wave circuits based on non-intrusive sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, pp. 505-510, 2016, IEEE, 978-3-9815-3707-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
16 | Athanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld |
Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 31(4), pp. 381-394, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Li Xu 0006, Marvin Onabajo |
A low-power temperature-compensated relaxation oscillator for built-in test signal generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 58th International Midwest Symposium on Circuits and Systems, MWSCAS 2015, Fort Collins, CO, USA, August 2-5, 2015, pp. 1-4, 2015, IEEE, 978-1-4673-6558-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Xian Wang 0003, Kenfack Blanchard, Estella Silva, Abhijit Chatterjee |
"Safe" built-in test and tuning of boost converters using feedback loop perturbations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 16th Latin-American Test Symposium, LATS 2015, Puerto Vallarta, Mexico, March 25-27, 2015, pp. 1-6, 2015, IEEE Computer Society, 978-1-4673-6710-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Ayssar Serhan, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir |
Low-cost EVM built-in test of RF transceivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDT ![In: 9th International Design and Test Symposium, IDT 2014, Algeries, Algeria, December 16-18, 2014, pp. 51-54, 2014, IEEE, 978-1-4799-8200-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Xian Wang 0003, Blanchard Kenfack, Estella Silva, Abhijit Chatterjee |
Built-In Test of Switched-Mode Power Converters: Avoiding DUT Damage Using Alternative Safe Measurements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013, pp. 56-61, 2013, IEEE Computer Society, 978-0-7695-5080-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir |
True non-intrusive sensors for RF built-in test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2013 IEEE International Test Conference, ITC 2013, Anaheim, CA, USA, September 6-13, 2013, pp. 1-10, 2013, IEEE Computer Society, 978-1-4799-0859-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Miao Zhang 0001, Yi Shen 0001, Xiao-Lei Zhang 0003, Zhi-Bo Wang, Ye Zhang 0008 |
Built-in Test Signal Feature Extraction Method Based on Hilbert-Huang Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Adv. Data Sci. Adapt. Anal. ![In: Adv. Data Sci. Adapt. Anal. 4(1-2), 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Christophe Kelma |
Experiences with non-intrusive sensors for RF built-in test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012, pp. 1-8, 2012, IEEE Computer Society, 978-1-4673-1594-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Manuel J. Barragan Asian, Diego Vázquez, Adoración Rueda |
Analog Sinewave Signal Generators for Mixed-Signal Built-in Test Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 27(3), pp. 305-320, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Masaki Hashizume |
A built-in test circuit for open defects at interconnects between dies in 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3DIC ![In: 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31 - February 2, 2012, pp. 1-5, 2011, IEEE, 978-1-4673-2189-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas |
A Built-In-Test Circuit for RF Differential Low Noise Amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7), pp. 1549-1558, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Wimol San-Um, Masayoshi Tachibana |
A low-jitter supply-regulated charge pump phase-locked loop with built-in test and calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 1931-1934, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Marvin Onabajo, José Silva-Martínez, Félix O. Fernandez-Rodriguez, Edgar Sánchez-Sinencio |
An On-Chip Loopback Block for RF Transceiver Built-In Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 56-II(6), pp. 444-448, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Qais Al-Gayem, Hongyuan Liu 0001, Andrew Richardson 0001, Nick Burd |
Built-in Test Solutions for the Electrode Structures in Bio-Fluidic Microsystems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 14th IEEE European Test Symposium, ETS 2009, Sevilla, Spain, May 25-29, 2009, pp. 73-78, 2009, IEEE Computer Society, 978-0-7695-3703-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
bio-fluidics, MNT, self-test, microfluidics, embedded test |
16 | Vishwanath Natarajan, Rajarajan Senguttuvan, Shreyas Sen, Abhijit Chatterjee |
Built-in Test Enabled Diagnosis and Tuning of RF Transmitter Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2008, pp. 418165:1-418165:10, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Xiaohua Fan, Marvin Onabajo, Félix O. Fernandez-Rodriguez, José Silva-Martínez, Edgar Sánchez-Sinencio |
A Current Injection Built-In Test Technique for RF Low-Noise Amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7), pp. 1794-1804, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Rajarajan Senguttuvan, Hyun Woo Choi, Donghoon Han, Abhijit Chatterjee |
Built-in Test of Frequency Modulated RF Transmitters Using Embedded Low-Pass Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, pp. 41-46, 2008, IEEE Computer Society, 978-0-7695-3150-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Alodeep Sanyal, Sandip Kundu |
A Built-in Test and Characterization Method for Circuit Marginality Related Failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 838-843, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Circuit Marginality, Pseudorandom Pattern Generator (PRPG), Multiple Input Signature Register (MISR), Fmax testing based on frequency shmoo, Built-In Self-Test (BIST), Design-for-Testability (DFT), Linear Feedback Shift Register (LFSR) |
16 | Guoyan Zhang, Ronan Farrell |
Embedded Built-In-Test Detection Circuit for Radio Frequency Systems and Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006, pp. 89-90, 2006, IEEE Computer Society, 1-4244-0185-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Guoyan Zhang, Ronan Farrell |
An Embedded Rectifier-Based Built-In-Test Circuit for CMOS RF Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 612-615, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Zhen Liu, Hui Lin, Xin (Robert) Luo |
Intelligent Built-in Test (BIT) for More-Electric Aircraft Power System Based on Hybrid Generalized LVQ Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2006, Third International Symposium on Neural Networks, Chengdu, China, May 28 - June 1, 2006, Proceedings, Part II, pp. 1409-1415, 2006, Springer, 3-540-34437-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | An Sang Hou |
A built-in-test scheme for evaluating the parameters of floating-gate MOS transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 54(3), pp. 988-995, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Karen Taylor, Bryan Nelson, Alan Chong, Henry C. Lin, Eddie Chan, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz |
Special issue on BIT CMOS built-in test architecture for high-speed jitter measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 54(3), pp. 975-987, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | John W. Sheppard, Mark A. Kaufman |
A Bayesian approach to diagnosis and prognosis using built-in test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 54(3), pp. 1003-1018, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Robert W. Gao |
Guest Editorial Special Section on Built-In-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 54(3), pp. 939-940, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Selim Sermet Akbay, Abhijit Chatterjee |
Built-In Test of RF Components Using Mapped Feature Extraction Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 243-248, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu, Chia-Cheng Liu |
Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 245-269, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
generator, BIST, computer arithmetic, polynomials, VLSI design, multiplication, division |
16 | Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz |
CMOS Built-In Test Architecture for High-Speed Jitter Measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 67-76, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Yingxu Wang 0001, Shushma Patel, Dilip Patel |
On Built-in Test Classes for Object-Oriented and Component-Based Information Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OOIS ![In: 7th International Conference on Object Oriented Information Systems, OOIS 2001, Calgary, Canada, August 27-29, 2001. Proceedings, pp. 307-316, 2001, Springer, 978-1-85233-546-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Irith Pomeranz, Sudhakar M. Reddy |
A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 19th International Conference on Computer Design (ICCD 2001), VLSI in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings, pp. 148-153, 2001, IEEE Computer Society, 0-7695-1200-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Luigi Carro, André C. Nácul, Daniel Janner, Marcelo Lubaszewski |
Built-in Test of Analog Non-Linear Circuits in a SOC Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France, pp. 437-448, 2001, Kluwer, 1-4020-7148-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
|
16 | Irith Pomeranz, Sudhakar M. Reddy |
On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETW ![In: 5th European Test Workshop, ETW 2000, Cascais, Portugal, May 23-26, 2000, pp. 144-149, 2000, IEEE Computer Society, 0-7695-0701-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar |
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 22-27, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Krishnendu Chakrabarty, Brian T. Murray |
Design of built-in test generator circuits using width compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10), pp. 1044-1051, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Irith Pomeranz, Sudhakar M. Reddy |
Improved built-in test pattern generators based on comparison units for synchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA, pp. 26-31, 1998, IEEE Computer Society, 0-8186-9099-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Sybille Hellebrand, Janusz Rajski, Steffen Tarnick, Srikanth Venkataraman, Bernard Courtois |
Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(2), pp. 223-233, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Colin M. Maunder |
A Universal Framework for Managed Built-in Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics - Join Them, Baltimore, Maryland, USA, October 17-21, 1993, pp. 21-29, 1993, IEEE Computer Society, 0-7803-1430-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Michael Zimmermann, Manfred Geilert |
Generation of embedded RAMs with built-in test using object-oriented programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 2-6, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
16 | Fevzi Belli, Ismael Camara, Alfred Schmidt |
A Built-in Test Language for PROLOG to Validate Knowledge-Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEA/AIE (Vol. 2) ![In: Proceedings of the Third International Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems, IEA/AIE 1990, July 15-18, 1990, The Mills House Hotel, Charleston, SC, USA - Volume 2, pp. 726-734, 1990, ACM, 0-89791-372-8. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
Prolog |
16 | Colin Maunder |
Built-in test for VLSI - pseudorandom techniques: Bardell, P H, McArney, W H and Savir, J Wiley, New York, NY, USA (1987) £45.00 pp 354. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 13(1), pp. 62, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #100 of 153 (100 per page; Change: ) Pages: [ 1][ 2][ >>] |
|