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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 10362 publication records. Showing 10361 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
102 | Chia-Ming Chang 0002, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang 0002, Yu-Sheng Lu |
Type-matching clock tree for zero skew clock gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 714-719, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
physical design, gated clock, clock network synthesis |
93 | Xiaohong Jiang 0001, Susumu Horiguchi |
Statistical skew modeling for general clock distribution networks in presence of process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(5), pp. 704-717, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
89 | Mely Chen Chi, Shih-Hsu Huang |
A Reliable Clock Tree Design Methodology for ASIC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 269-274, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Clock tree design, Clock tree synthesis |
82 | Vernon L. Chi |
Salphasic Distribution of Clock Signals for Synchronous Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(5), pp. 597-602, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
transmission line theory, loaded transmission line, printed circuit board clock planes, clock plane, phase skew, salphasic clock, synchronisation, clocks, distribution network, clock skews, synchronous systems, synchronous system, propagation delay, system clock, phase shifts, clock signals, clock signal |
81 | José Luis Neves, Eby G. Friedman |
Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 16(2-3), pp. 149-161, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
80 | Julien Lamoureux, Steven J. E. Wilton |
On the trade-off between power and flexibility of FPGA clock networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(3), pp. 13:1-13:33, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
clock-aware placement, FPGA, low-power design, clock distribution networks |
80 | Amor Bouzelat, Zoubir Mammeri |
Simple reading, implicit rejection and average function for fault-tolerant physical clock synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 524-531, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
simple reading, implicit rejection, average function, fault tolerant physical clock synchronization algorithms, remote clock reading function, fault value rejection function, convergence function, clock adjustment function, clock value reference set, Lundelius algorithm, reference set, maximum skew, fault tolerance, distributed algorithms, synchronization algorithms |
77 | José Luis Neves, Eby G. Friedman |
Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(2), pp. 286-291, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
76 | Hermann Kopetz, Astrit Ademaj, Alexander Hanzlik |
Integration of Internal and External Clock Synchronization by the Combination of Clock-State and Clock-Rate Correction in Fault-Tolerant Distributed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 5-8 December 2004, Lisbon, Portugal, pp. 415-425, 2004, IEEE Computer Society, 0-7695-2247-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
fault-tolerant time base, real-time system, clock synchronization, rate adaptation, global time |
74 | Pei-Hsin Ho |
Industrial clock design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 139-140, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low power, variability, physical design, clock tree synthesis |
74 | Baris Taskin, Ivan S. Kourtev |
Delay insertion method in clock skew scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 47-54, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
delay insertion, re-convergent paths, optimization, linear programming, clock skew |
74 | Joe G. Xi, Wayne Wei-Ming Dai |
Jitter-tolerant clock routing in two-phase synchronous systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 316-320, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Deferred-Merge Embedding framework, clock jitter, clock tree cost, jitter-tolerance, jitter-tolerant clock routing, near-zero skew, nonoverlapping interval, safety margin, system operating conditions, two-phase clocking, two-phase jitter-tolerant useful-skew tree, two-phase synchronous systems, simulated annealing, manufacturing, jitter, zero skew |
73 | Atsushi Takahashi 0001, Kazunori Inoue, Yoji Kajitani |
Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 260-265, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
clock-tree routing, semi-synchronous, deferred-merge-embedding (DME), synchronous, buffer insertion, buffer sizing, clock-schedule |
70 | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu |
Activity and register placement aware gated clock network design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 182-189, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
gated clock tree, low power, placement |
70 | Hong Hao, Kanti Bhabuthmal |
Clock controller design in SuperSPARC II microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 124-129, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
SuperSPARC II, internal clock pulses, internal clock, free running mode, IEEE 1149.1 interface, microprocessor, clocks, microprocessor chips, clock controller |
69 | Shinya Abe, Masanori Hashimoto, Takao Onoye |
Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 520-525, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
mesh-style clock distribution, clock skew, manufacturing variability |
69 | Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal |
Path Delay Testing: Variable-Clock Versus Rated-Clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 470-475, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
rated-clock testing, slow-clock testing, Delay testing, path delay faults, sequential circuit test |
68 | Xin-Wei Shih, Yao-Wen Chang |
Fast timing-model independent buffered clock-tree synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 80-85, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
68 | Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri |
A novel clock distribution and dynamic de-skewing methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 626-631, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
68 | Amir H. Farrahi, Chunhong Chen, Ankur Srivastava 0001, Gustavo E. Téllez, Majid Sarrafzadeh |
Activity-driven clock design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6), pp. 705-714, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
68 | Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang |
Skew-aware polarity assignment in clock tree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(2), pp. 31:1-31:17, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
peak current, polarity assignment, power/ground noise, Clock skew, clock tree |
68 | JeongKi Park, Young-Tak Kim |
An Enhanced SNTP (ESNTP) Clock Synchronization for High-Precision Network QoS Measurements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPOM ![In: IP Operations and Management, 8th IEEE International Workshop, IPOM 2008, Samos Island, Greece, September 22-26, 2008, Proceedings, pp. 91-102, 2008, Springer, 978-3-540-87356-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
delay and jitter, clock drift compensation, QoS, performance measurement, Clock synchronization |
67 | Daniela Tulone |
On the Feasibility of Time Estimation under Isolation Conditions in Wireless Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmica ![In: Algorithmica 49(4), pp. 386-411, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Sensor networks, Energy conservation, Clock synchronization, Clock drift, Time series models, Resource efficiency |
67 | Hermann Kopetz, Astrit Ademaj, Alexander Hanzlik |
Combination of clock-state and clock-rate correction in fault-tolerant distributed systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Real Time Syst. ![In: Real Time Syst. 33(1-3), pp. 139-173, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Fault-tolerant time base, Real-time system, Clock synchronization, Rate adaptation, Global time |
66 | Monica Donno, Enrico Macii, Luca Mazzoni |
Power-aware clock tree planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 138-147, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
clock tree synthesis and routing, physical design and optimization, low-power design, digital design |
64 | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu |
Gate planning during placement for gated clock network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 128-133, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
64 | Kun Sun 0001, Peng Ning, Cliff Wang |
Secure and resilient clock synchronization in wireless sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Sel. Areas Commun. ![In: IEEE J. Sel. Areas Commun. 24(2), pp. 395-408, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
64 | Deshanand P. Singh, Stephen Dean Brown |
Constrained clock shifting for field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 121-126, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
64 | Stuart K. Tewksbury, Lawrence A. Hornak |
Optical Clock Distribution in Electronic Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 16(2-3), pp. 225-246, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
64 | Ashutosh Chakraborty, David Z. Pan |
Skew management of NBTI impacted gated clock trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 127-133, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
clock skew, clock gating, NBTI |
62 | Ying Zhao 0011, Wanlei Zhou 0001, Yingying Zhang, E. J. Lanham, Jiumei Huang |
Clock Synchronization State Graphs Based on Clock Precision Difference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP ![In: Distributed and Parallel Computing, 6th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP, Melbourne, Australia, October 2-3, 2005, Proceedings, pp. 34-39, 2005, Springer, 3-540-29235-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Precision Difference, State graphics, Self-Adaptive, Clock Synchronization |
62 | Monica Donno, Alessandro Ivaldi, Luca Benini, Enrico Macii |
Clock-tree power optimization based on RTL clock-gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 622-627, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
clock-tree synthsis, low-power design |
62 | Julien Lamoureux, Steven J. E. Wilton |
FPGA clock network architecture: flexibility vs. area and power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 101-108, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGA, architecture, low-power, clock network |
61 | Daniel L. Palumbo |
The Derivation and Experimental Verification of Clock Synchronization Theory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(6), pp. 676-686, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
clock synchronization theory, Interactive Convergence Clock Synchronization Algorithm, Mid-Point Algorithm, clock circuitry, operating conditions, worst case failures, experimental verification, formal methods, formal verification, synchronisation, clock synchronization, clock skew, byzantine failure, proof of correctness, failure modes, timing circuits, malicious failures |
61 | Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews |
High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 91-107, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television |
60 | Xiaoji Ye, Peng Li 0001 |
An application-specific adjoint sensitivity analysis framework for clock mesh sensitivity computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 634-640, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
60 | Ariel Daliot, Danny Dolev, Hanna Parnas |
Linear Time Byzantine Self-Stabilizing Clock Synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OPODIS ![In: Principles of Distributed Systems, 7th International Conference, OPODIS 2003 La Martinique, French West Indies, December 10-13, 2003 Revised Selected Papers, pp. 7-19, 2003, Springer, 3-540-22667-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
60 | Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman |
Retiming and clock scheduling for digital circuit optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2), pp. 184-203, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
60 | Qing Zhu, Wayne Wei-Ming Dai |
Planar clock routing for high performance chip and package co-design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(2), pp. 210-226, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
59 | Atanu Chattopadhyay, Zeljko Zilic |
Serial reconfigurable mismatch-tolerant clock distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 611-612, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
process variation, clock skew, clock networks |
59 | Heinrich Moser, Ulrich Schmid 0001 |
Optimal Deterministic Remote Clock Estimation in Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OPODIS ![In: Principles of Distributed Systems, 12th International Conference, OPODIS 2008, Luxor, Egypt, December 15-18, 2008. Proceedings, pp. 363-387, 2008, Springer, 978-3-540-92220-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
optimal clock synchronization, remote clock estimation, real-time systems, Distributed algorithms, computing models |
59 | En-Shou Chang, Daniel Gajski, Sanjiv Narayan |
An optimal clock period selection method based on slack minimization criteria. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 1(3), pp. 352-370, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
clock slack, scheduling, performance estimation, clock period |
59 | Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman |
Timing-driven variation-aware nonuniform clock mesh synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 15-20, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
clock mesh synthesis, non-tree clock networks, vlsi cad, power, process variations, physical design, clock skew, clock distribution |
59 | Alan Olson, Kang G. Shin |
Fault-Tolerant Clock Synchronization in Large Multicomputer Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(9), pp. 912-923, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
fault-tolerant clock synchronization, large multicomputer systems, clock value, maximum skew, maximum time, fault tolerance, reliability, fault tolerant computing, multiprocessing systems, synchronisation, clocks, clock skew, clock drift, synchronization algorithm |
57 | Cliff C. N. Sze |
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 143, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
VLSI, benchmarks, physical design, clock network synthesis |
57 | Anand Rajaram, David Z. Pan |
Variation tolerant buffered clock network synthesis with cross links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 157-164, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
non-tree clocks, physical design, VLSI CAD, clock network |
57 | Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu |
Minimizing peak current via opposite-phase clock tree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 182-185, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low power, physical design, clock network synthesis |
57 | Benjamin R. Hamilton, Xiaoli Ma, Qi Zhao 0006, Jun (Jim) Xu |
ACES: adaptive clock estimation and synchronization using Kalman filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MobiCom ![In: Proceedings of the 14th Annual International Conference on Mobile Computing and Networking, MOBICOM 2008, San Francisco, California, USA, September 14-19, 2008, pp. 152-162, 2008, ACM, 978-1-60558-096-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
clock offset, resource-constrained network, Kalman filter, clock synchronization, clock skew |
57 | Peter Wohl, John A. Waicukauski |
Using ATPG for clock rules checking in complex scan design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 130-136, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
clock rules checking, complex scan designs, structured DFT, automated design-rules-checking, robust set of rules, clock-rule-violation detection, fast clock verification, large microprocessor design, topological circuit analysis, zero delay, user controlled verification, capture ability, port contention, cone tracing, equivalent sources, ATPG, race conditions, computer testing, timing verification |
56 | Bao Liu 0001, Andrew B. Kahng, Xu Xu 0001, Jiang Hu, Ganesh Venkataraman |
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 24-31, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
55 | Ivan S. Kourtev, Eby G. Friedman |
Clock skew scheduling for improved reliability via quadratic programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 239-243, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
55 | Kai Zhu 0001, Martin D. F. Wong |
Clock skew minimization during FPGA placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(4), pp. 376-385, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
55 | Wei-Chung Chao, Wai-Kei Mak |
Low-power gated and buffered clock network construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(1), pp. 20:1-20:20, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
low power, buffer, clock gating, Clock tree, zero-skew |
55 | Malay K. Ganai, Aarti Gupta |
Efficient BMC for Multi-Clock Systems with Clocked Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 310-315, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
OpenCores multiclock system benchmarks, clocked specifications, multiphased clocks, level-sensitive latches, SAT-based bounded model checking, synchronous multiclock systems, clocked LTL properties, clock modeling schemes, clock constraints, loop-checks, gated clocks |
55 | Kursat Kursat Ozenc, James P. Brommer, Bong-keum Jeong, Nina Shih, Karen Au, John Zimmerman |
Reverse alarm clock: a research through design example of designing for the self. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DPPI ![In: Proceedings of the 2007 International Conference on Designing Pleasurable Products and Interfaces, 2007, Helsinki, Finland, August 22-25, 2007, pp. 392-406, 2007, ACM, 978-1-59593-942-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
alarm clock, bedtime, designing for the self, material possession attachment, children, time, clock, consumer behavior, parents, social role, wakeup |
55 | Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Dynamic thermal clock skew compensation using tunable delay buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 162-167, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
temperature aware design methodology, tunable delay buffers, clock skew, clock tree |
55 | Chunhong Chen, Changjun Kang, Majid Sarrafzadeh |
Activity-sensitive clock tree construction for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 279-282, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
low power, clock gating, clock tree, activity pattern |
55 | Min Zhao 0001, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal |
Worst case clock skew under power supply variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 22-28, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
clock skew, power supply noise, clock network |
53 | Xiaoji Ye, Min Zhao 0001, Rajendran Panda, Peng Li 0001, Jiang Hu |
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 627-632, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
clock mesh, dynamic time step rounding, simulation, macromodel |
53 | Anand Rajaram, David Z. Pan |
Robust chip-level clock tree synthesis for SOC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 720-723, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
chip-level CTS, physical design, clock network |
53 | Sherif A. Tawfik, Volkan Kursun |
Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 62-67, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD |
53 | Santashil PalChaudhuri, Amit Kumar Saha, David B. Johnson 0001 |
Adaptive clock synchronization in sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSN ![In: Proceedings of the Third International Symposium on Information Processing in Sensor Networks, IPSN 2004, Berkeley, California, USA, April 26-27, 2004, pp. 340-348, 2004, ACM, 1-58113-846-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
sensor networks, clock synchronization, probabilistic algorithms |
53 | Rui Fan 0004, Nancy A. Lynch |
Gradient clock synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the Twenty-Third Annual ACM Symposium on Principles of Distributed Computing, PODC 2004, St. John's, Newfoundland, Canada, July 25-28, 2004, pp. 320-327, 2004, ACM, 1-58113-802-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ad hoc networks, lower bounds, clock synchronization, local algorithms |
53 | Lain-Chyr Hwang, Steen J. Hsu, San-Yuan Wang, Yong-Hua Huang |
A Hybrid Scheduling Algorithm with Low Complexity: Jumping Virtual Clock Round Robin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS Workshops ![In: 25th International Conference on Distributed Computing Systems Workshops (ICDCS 2005 Workshops), 6-10 June 2005, Columbus, OH, USA, pp. 698-703, 2005, IEEE Computer Society, 0-7695-2328-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Jumping Virtual Clock (JVC), Jumping Virtual Clock Round Robin (JVCRR), Scheduling algorithm, Fair queueing, Round Robin, Virtual clock |
53 | Chung-Seok (Andy) Seo, Abhijit Chatterjee, Sang-Yeon Cho, Nan M. Jokerst |
Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 292-297, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
H-tree, asymmetric structure, optical clock distribution, optical waveguide loss modeling, optoelectronic system-on-a-package, optimization, clock distribution, clock routing |
52 | Vishwanadh Tirumalashetty, Hamid Mahmoodi |
Clock Gating and Negative Edge Triggering for Energy Recovery Clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1141-1144, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Zhengtao Yu 0002, Xun Liu |
Low-Power Rotary Clock Array Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(1), pp. 5-12, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu |
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 383-388, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Zhengtao Yu 0002, Xun Liu |
Design of Rotary Clock Based Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 43-48, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Liang Huang, Yici Cai, Qiang Zhou 0001, Xianlong Hong, Jiang Hu, Yongqiang Lu 0001 |
Clock network minimization methodology based on incremental placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 99-102, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
51 | Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen |
Minimizing coupling jitter by buffer resizing for coupled clock networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 509-512, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
51 | Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen |
Minimizing Inter-Clock Coupling Jitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 333-338, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
51 | Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh |
Activity-driven clock design for low power circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 62-65, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Gated Clock Tree, Sleep Mode, Power minimization, Clock Tree |
51 | Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi 0001 |
A practical clock tree synthesis for semi-synchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000, pp. 159-164, 2000, ACM, 1-58113-191-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
clock-input timing, environmental and manufacturing conditions, semi-synchronous, various timing clock tree, zero skew clock tree, clock scheduling |
50 | Daniela Tulone |
A resource--efficient time estimation for wireless sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DIALM-POMC ![In: Proceedings of the DIALM-POMC Joint Workshop on Foundations of Mobile Computing, Philadelphia, PA, USA, October 1, 2004, pp. 52-59, 2004, ACM, 1-58113-921-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
clock drift rate, clock synchronization, time series forecasting, time estimation, resource efficiency |
50 | Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy 0001 |
Energy recovery clocking scheme and flip-flops for ultra low-energy applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 54-59, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
flip-flop, clock, clock tree, energy recovery, adiabatic |
49 | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu |
A single layer zero skew clock routing in X architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 52(8), pp. 1466-1475, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
single layer, X architecture, zero skew, clock routing |
49 | Christoph Lenzen 0001, Thomas Locher, Roger Wattenhofer |
Tight bounds for clock synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the 28th Annual ACM Symposium on Principles of Distributed Computing, PODC 2009, Calgary, Alberta, Canada, August 10-12, 2009, pp. 46-55, 2009, ACM, 978-1-60558-396-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
gradient property, optimal skew bounds, clock synchronization |
49 | Fabian Kuhn, Rotem Oshman |
Gradient Clock Synchronization Using Reference Broadcasts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OPODIS ![In: Principles of Distributed Systems, 13th International Conference, OPODIS 2009, Nîmes, France, December 15-18, 2009. Proceedings, pp. 204-218, 2009, Springer, 978-3-642-10876-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Gradient Clock Synchronization, Wireless Networks |
49 | Venkatesh Arunachalam, Wayne P. Burleson |
Low-power clock distribution in a multilayer core 3d microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 429-434, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
3D ic's, 3D processor architectures, clock grids |
49 | Rui Fan 0004, Nancy A. Lynch |
Gradient clock synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 18(4), pp. 255-266, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Ad-hoc networks, Lower bounds, Clock synchronization, Indistinguishability |
49 | Xinjie Wei, Yici Cai, Meng Zhao, Xianlong Hong |
Legitimate Skew Clock Routing with Buffer Insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 42(2), pp. 107-116, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
legitimate skew, buffer insertion, clock routing |
49 | Yongqiang Lu 0001, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Liang Huang, Jiang Hu |
Navigating registers in placement for clock network minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 176-181, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low power, placement, clock network, variation tolerance |
49 | Kai Wang 0011, Malgorzata Marek-Sadowska |
Buffer sizing for clock power minimization subject to general skew constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 159-164, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
sequential linear programming, sizing, clock skew scheduling |
49 | Anand Rajaram, Jiang Hu, Rabi N. Mahapatra |
Reducing clock skew variability via cross links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 18-23, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
VLSI, physical design, variation, clock network synthesis |
49 | Jindrich Zejda, Paul Frain |
General framework for removal of clock network pessimism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 632-639, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
clock network reconvergence, voltage and temperature delay variation, process, static timing analysis, deep sub-micron |
49 | Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen |
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 399-404, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
di/dt noise, low-noise digital design, supply current shaping, optimization, substrate noise, clock distribution networks |
49 | Nestoras Tzartzanis, William C. Athas |
Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 137-153, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
low-power digital CMOS, adiabatic switching, clock-powered logic, energy recovery |
49 | Martin Saint-Laurent, Animesh Datta |
A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 159-164, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
clock gater, clock gating cell, local clock buffer, set-reset latch |
48 | Attila Pásztor, Darryl Veitch |
PC based precision timing without GPS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the International Conference on Measurements and Modeling of Computer Systems, SIGMETRICS 2002, June 15-19, 2002, Marina Del Rey, California, USA, pp. 1-10, 2002, ACM, 1-58113-531-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
pc clocks, software clock, synchronization, timing, GPS, network measurement, NTP |
48 | Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi |
Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 794-798, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
48 | Yesin Ryu, Taewhan Kim |
Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 416-419, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
48 | Ashok Narasimhan, Ramalingam Sridhar |
Impact of Variability on Clock Skew in H-tree Clock Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 458-466, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
48 | Shih-Hsu Huang, Yow-Tyng Nieh |
Clock Period Minimization of Non-Zero Clock Skew Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 809-812, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
48 | Haksu Kim, Dian Zhou |
An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 258-261, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
48 | Olivier Bezet, Véronique Berge-Cherfaoui |
On-line and post-processing timestamp correspondence for free-running clock nodes, using a network clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Real Time Syst. ![In: Real Time Syst. 38(3), pp. 191-222, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Timestamping conversion, Timestamping error modeling, Free running clock nodes, Network clock, Distributed architecture |
47 | Qiang Wang, Subodh Gupta, Jason Helge Anderson |
Clock power reduction for virtex-5 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 13-22, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking |
47 | Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay |
Slew-aware clock tree design for reliable subthreshold circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 15-20, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
slew, clocks, subthreshold |
47 | Anand Rajaram, Raguram Damodaran, Arjun Rajagopal |
Practical Clock Tree Robustness Signoff Metrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 676-679, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan |
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 398-403, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
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