Search results for "clock"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
102	Chia-Ming Chang 0002, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang 0002, Yu-Sheng Lu	Type-matching clock tree for zero skew clock gating.	DAC	2008	DBLP DOI BibTeX RDF	physical design, gated clock, clock network synthesis
93	Xiaohong Jiang 0001, Susumu Horiguchi	Statistical skew modeling for general clock distribution networks in presence of process variations.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
89	Mely Chen Chi, Shih-Hsu Huang	A Reliable Clock Tree Design Methodology for ASIC Designs.	ISQED	2000	DBLP DOI BibTeX RDF	Clock tree design, Clock tree synthesis
82	Vernon L. Chi	Salphasic Distribution of Clock Signals for Synchronous Systems.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	transmission line theory, loaded transmission line, printed circuit board clock planes, clock plane, phase skew, salphasic clock, synchronisation, clocks, distribution network, clock skews, synchronous systems, synchronous system, propagation delay, system clock, phase shifts, clock signals, clock signal
81	José Luis Neves, Eby G. Friedman	Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
80	Julien Lamoureux, Steven J. E. Wilton	On the trade-off between power and flexibility of FPGA clock networks.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	clock-aware placement, FPGA, low-power design, clock distribution networks
80	Amor Bouzelat, Zoubir Mammeri	Simple reading, implicit rejection and average function for fault-tolerant physical clock synchronization.	EUROMICRO	1997	DBLP DOI BibTeX RDF	simple reading, implicit rejection, average function, fault tolerant physical clock synchronization algorithms, remote clock reading function, fault value rejection function, convergence function, clock adjustment function, clock value reference set, Lundelius algorithm, reference set, maximum skew, fault tolerance, distributed algorithms, synchronization algorithms
77	José Luis Neves, Eby G. Friedman	Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
76	Hermann Kopetz, Astrit Ademaj, Alexander Hanzlik	Integration of Internal and External Clock Synchronization by the Combination of Clock-State and Clock-Rate Correction in Fault-Tolerant Distributed Systems.	RTSS	2004	DBLP DOI BibTeX RDF	fault-tolerant time base, real-time system, clock synchronization, rate adaptation, global time
74	Pei-Hsin Ho	Industrial clock design.	ISPD	2009	DBLP DOI BibTeX RDF	low power, variability, physical design, clock tree synthesis
74	Baris Taskin, Ivan S. Kourtev	Delay insertion method in clock skew scheduling.	ISPD	2005	DBLP DOI BibTeX RDF	delay insertion, re-convergent paths, optimization, linear programming, clock skew
74	Joe G. Xi, Wayne Wei-Ming Dai	Jitter-tolerant clock routing in two-phase synchronous systems.	ICCAD	1996	DBLP DOI BibTeX RDF	Deferred-Merge Embedding framework, clock jitter, clock tree cost, jitter-tolerance, jitter-tolerant clock routing, near-zero skew, nonoverlapping interval, safety margin, system operating conditions, two-phase clocking, two-phase jitter-tolerant useful-skew tree, two-phase synchronous systems, simulated annealing, manufacturing, jitter, zero skew
73	Atsushi Takahashi 0001, Kazunori Inoue, Yoji Kajitani	Clock-tree routing realizing a clock-schedule for semi-synchronous circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	clock-tree routing, semi-synchronous, deferred-merge-embedding (DME), synchronous, buffer insertion, buffer sizing, clock-schedule
70	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity and register placement aware gated clock network design.	ISPD	2008	DBLP DOI BibTeX RDF	gated clock tree, low power, placement
70	Hong Hao, Kanti Bhabuthmal	Clock controller design in SuperSPARC II microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	SuperSPARC II, internal clock pulses, internal clock, free running mode, IEEE 1149.1 interface, microprocessor, clocks, microprocessor chips, clock controller
69	Shinya Abe, Masanori Hashimoto, Takao Onoye	Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution.	ISQED	2008	DBLP DOI BibTeX RDF	mesh-style clock distribution, clock skew, manufacturing variability
69	Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal	Path Delay Testing: Variable-Clock Versus Rated-Clock.	VLSI Design	1998	DBLP DOI BibTeX RDF	rated-clock testing, slow-clock testing, Delay testing, path delay faults, sequential circuit test
68	Xin-Wei Shih, Yao-Wen Chang	Fast timing-model independent buffered clock-tree synthesis.	DAC	2010	DBLP DOI BibTeX RDF
68	Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri	A novel clock distribution and dynamic de-skewing methodology.	ICCAD	2004	DBLP DOI BibTeX RDF
68	Amir H. Farrahi, Chunhong Chen, Ankur Srivastava 0001, Gustavo E. Téllez, Majid Sarrafzadeh	Activity-driven clock design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
68	Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang	Skew-aware polarity assignment in clock tree.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	peak current, polarity assignment, power/ground noise, Clock skew, clock tree
68	JeongKi Park, Young-Tak Kim	An Enhanced SNTP (ESNTP) Clock Synchronization for High-Precision Network QoS Measurements.	IPOM	2008	DBLP DOI BibTeX RDF	delay and jitter, clock drift compensation, QoS, performance measurement, Clock synchronization
67	Daniela Tulone	On the Feasibility of Time Estimation under Isolation Conditions in Wireless Sensor Networks.	Algorithmica	2007	DBLP DOI BibTeX RDF	Sensor networks, Energy conservation, Clock synchronization, Clock drift, Time series models, Resource efficiency
67	Hermann Kopetz, Astrit Ademaj, Alexander Hanzlik	Combination of clock-state and clock-rate correction in fault-tolerant distributed systems.	Real Time Syst.	2006	DBLP DOI BibTeX RDF	Fault-tolerant time base, Real-time system, Clock synchronization, Rate adaptation, Global time
66	Monica Donno, Enrico Macii, Luca Mazzoni	Power-aware clock tree planning.	ISPD	2004	DBLP DOI BibTeX RDF	clock tree synthesis and routing, physical design and optimization, low-power design, digital design
64	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Gate planning during placement for gated clock network.	ICCD	2008	DBLP DOI BibTeX RDF
64	Kun Sun 0001, Peng Ning, Cliff Wang	Secure and resilient clock synchronization in wireless sensor networks.	IEEE J. Sel. Areas Commun.	2006	DBLP DOI BibTeX RDF
64	Deshanand P. Singh, Stephen Dean Brown	Constrained clock shifting for field programmable gate arrays.	FPGA	2002	DBLP DOI BibTeX RDF
64	Stuart K. Tewksbury, Lawrence A. Hornak	Optical Clock Distribution in Electronic Systems.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
64	Ashutosh Chakraborty, David Z. Pan	Skew management of NBTI impacted gated clock trees.	ISPD	2010	DBLP DOI BibTeX RDF	clock skew, clock gating, NBTI
62	Ying Zhao 0011, Wanlei Zhou 0001, Yingying Zhang, E. J. Lanham, Jiumei Huang	Clock Synchronization State Graphs Based on Clock Precision Difference.	ICA3PP	2005	DBLP DOI BibTeX RDF	Precision Difference, State graphics, Self-Adaptive, Clock Synchronization
62	Monica Donno, Alessandro Ivaldi, Luca Benini, Enrico Macii	Clock-tree power optimization based on RTL clock-gating.	DAC	2003	DBLP DOI BibTeX RDF	clock-tree synthsis, low-power design
62	Julien Lamoureux, Steven J. E. Wilton	FPGA clock network architecture: flexibility vs. area and power.	FPGA	2006	DBLP DOI BibTeX RDF	FPGA, architecture, low-power, clock network
61	Daniel L. Palumbo	The Derivation and Experimental Verification of Clock Synchronization Theory.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	clock synchronization theory, Interactive Convergence Clock Synchronization Algorithm, Mid-Point Algorithm, clock circuitry, operating conditions, worst case failures, experimental verification, formal methods, formal verification, synchronisation, clock synchronization, clock skew, byzantine failure, proof of correctness, failure modes, timing circuits, malicious failures
61	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews	High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips.	ARVLSI	1995	DBLP DOI BibTeX RDF	counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television
60	Xiaoji Ye, Peng Li 0001	An application-specific adjoint sensitivity analysis framework for clock mesh sensitivity computation.	ISQED	2009	DBLP DOI BibTeX RDF
60	Ariel Daliot, Danny Dolev, Hanna Parnas	Linear Time Byzantine Self-Stabilizing Clock Synchronization.	OPODIS	2003	DBLP DOI BibTeX RDF
60	Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman	Retiming and clock scheduling for digital circuit optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
60	Qing Zhu, Wayne Wei-Ming Dai	Planar clock routing for high performance chip and package co-design.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
59	Atanu Chattopadhyay, Zeljko Zilic	Serial reconfigurable mismatch-tolerant clock distribution.	DAC	2009	DBLP DOI BibTeX RDF	process variation, clock skew, clock networks
59	Heinrich Moser, Ulrich Schmid 0001	Optimal Deterministic Remote Clock Estimation in Real-Time Systems.	OPODIS	2008	DBLP DOI BibTeX RDF	optimal clock synchronization, remote clock estimation, real-time systems, Distributed algorithms, computing models
59	En-Shou Chang, Daniel Gajski, Sanjiv Narayan	An optimal clock period selection method based on slack minimization criteria.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	clock slack, scheduling, performance estimation, clock period
59	Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman	Timing-driven variation-aware nonuniform clock mesh synthesis.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	clock mesh synthesis, non-tree clock networks, vlsi cad, power, process variations, physical design, clock skew, clock distribution
59	Alan Olson, Kang G. Shin	Fault-Tolerant Clock Synchronization in Large Multicomputer Systems.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	fault-tolerant clock synchronization, large multicomputer systems, clock value, maximum skew, maximum time, fault tolerance, reliability, fault tolerant computing, multiprocessing systems, synchronisation, clocks, clock skew, clock drift, synchronization algorithm
57	Cliff C. N. Sze	ISPD 2010 high performance clock network synthesis contest: benchmark suite and results.	ISPD	2010	DBLP DOI BibTeX RDF	VLSI, benchmarks, physical design, clock network synthesis
57	Anand Rajaram, David Z. Pan	Variation tolerant buffered clock network synthesis with cross links.	ISPD	2006	DBLP DOI BibTeX RDF	non-tree clocks, physical design, VLSI CAD, clock network
57	Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu	Minimizing peak current via opposite-phase clock tree.	DAC	2005	DBLP DOI BibTeX RDF	low power, physical design, clock network synthesis
57	Benjamin R. Hamilton, Xiaoli Ma, Qi Zhao 0006, Jun (Jim) Xu	ACES: adaptive clock estimation and synchronization using Kalman filtering.	MobiCom	2008	DBLP DOI BibTeX RDF	clock offset, resource-constrained network, Kalman filter, clock synchronization, clock skew
57	Peter Wohl, John A. Waicukauski	Using ATPG for clock rules checking in complex scan design.	VTS	1997	DBLP DOI BibTeX RDF	clock rules checking, complex scan designs, structured DFT, automated design-rules-checking, robust set of rules, clock-rule-violation detection, fast clock verification, large microprocessor design, topological circuit analysis, zero delay, user controlled verification, capture ability, port contention, cone tracing, equivalent sources, ATPG, race conditions, computer testing, timing verification
56	Bao Liu 0001, Andrew B. Kahng, Xu Xu 0001, Jiang Hu, Ganesh Venkataraman	A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield.	ASP-DAC	2007	DBLP DOI BibTeX RDF
55	Ivan S. Kourtev, Eby G. Friedman	Clock skew scheduling for improved reliability via quadratic programming.	ICCAD	1999	DBLP DOI BibTeX RDF
55	Kai Zhu 0001, Martin D. F. Wong	Clock skew minimization during FPGA placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
55	Wei-Chung Chao, Wai-Kei Mak	Low-power gated and buffered clock network construction.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low power, buffer, clock gating, Clock tree, zero-skew
55	Malay K. Ganai, Aarti Gupta	Efficient BMC for Multi-Clock Systems with Clocked Specifications.	ASP-DAC	2007	DBLP DOI BibTeX RDF	OpenCores multiclock system benchmarks, clocked specifications, multiphased clocks, level-sensitive latches, SAT-based bounded model checking, synchronous multiclock systems, clocked LTL properties, clock modeling schemes, clock constraints, loop-checks, gated clocks
55	Kursat Kursat Ozenc, James P. Brommer, Bong-keum Jeong, Nina Shih, Karen Au, John Zimmerman	Reverse alarm clock: a research through design example of designing for the self.	DPPI	2007	DBLP DOI BibTeX RDF	alarm clock, bedtime, designing for the self, material possession attachment, children, time, clock, consumer behavior, parents, social role, wakeup
55	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Dynamic thermal clock skew compensation using tunable delay buffers.	ISLPED	2006	DBLP DOI BibTeX RDF	temperature aware design methodology, tunable delay buffers, clock skew, clock tree
55	Chunhong Chen, Changjun Kang, Majid Sarrafzadeh	Activity-sensitive clock tree construction for low power.	ISLPED	2002	DBLP DOI BibTeX RDF	low power, clock gating, clock tree, activity pattern
55	Min Zhao 0001, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal	Worst case clock skew under power supply variations.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	clock skew, power supply noise, clock network
53	Xiaoji Ye, Min Zhao 0001, Rajendran Panda, Peng Li 0001, Jiang Hu	Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding.	ISQED	2008	DBLP DOI BibTeX RDF	clock mesh, dynamic time step rounding, simulation, macromodel
53	Anand Rajaram, David Z. Pan	Robust chip-level clock tree synthesis for SOC designs.	DAC	2008	DBLP DOI BibTeX RDF	chip-level CTS, physical design, clock network
53	Sherif A. Tawfik, Volkan Kursun	Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution.	ISLPED	2007	DBLP DOI BibTeX RDF	dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD
53	Santashil PalChaudhuri, Amit Kumar Saha, David B. Johnson 0001	Adaptive clock synchronization in sensor networks.	IPSN	2004	DBLP DOI BibTeX RDF	sensor networks, clock synchronization, probabilistic algorithms
53	Rui Fan 0004, Nancy A. Lynch	Gradient clock synchronization.	PODC	2004	DBLP DOI BibTeX RDF	ad hoc networks, lower bounds, clock synchronization, local algorithms
53	Lain-Chyr Hwang, Steen J. Hsu, San-Yuan Wang, Yong-Hua Huang	A Hybrid Scheduling Algorithm with Low Complexity: Jumping Virtual Clock Round Robin.	ICDCS Workshops	2005	DBLP DOI BibTeX RDF	Jumping Virtual Clock (JVC), Jumping Virtual Clock Round Robin (JVCRR), Scheduling algorithm, Fair queueing, Round Robin, Virtual clock
53	Chung-Seok (Andy) Seo, Abhijit Chatterjee, Sang-Yeon Cho, Nan M. Jokerst	Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	H-tree, asymmetric structure, optical clock distribution, optical waveguide loss modeling, optoelectronic system-on-a-package, optimization, clock distribution, clock routing
52	Vishwanadh Tirumalashetty, Hamid Mahmoodi	Clock Gating and Negative Edge Triggering for Energy Recovery Clock.	ISCAS	2007	DBLP DOI BibTeX RDF
51	Zhengtao Yu 0002, Xun Liu	Low-Power Rotary Clock Array Design.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
51	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.	ISVLSI	2007	DBLP DOI BibTeX RDF
51	Zhengtao Yu 0002, Xun Liu	Design of Rotary Clock Based Circuits.	DAC	2007	DBLP DOI BibTeX RDF
51	Liang Huang, Yici Cai, Qiang Zhou 0001, Xianlong Hong, Jiang Hu, Yongqiang Lu 0001	Clock network minimization methodology based on incremental placement.	ASP-DAC	2005	DBLP DOI BibTeX RDF
51	Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen	Minimizing coupling jitter by buffer resizing for coupled clock networks.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
51	Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen	Minimizing Inter-Clock Coupling Jitter.	ISQED	2003	DBLP DOI BibTeX RDF
51	Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh	Activity-driven clock design for low power circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	Gated Clock Tree, Sleep Mode, Power minimization, Clock Tree
51	Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi 0001	A practical clock tree synthesis for semi-synchronous circuits.	ISPD	2000	DBLP DOI BibTeX RDF	clock-input timing, environmental and manufacturing conditions, semi-synchronous, various timing clock tree, zero skew clock tree, clock scheduling
50	Daniela Tulone	A resource--efficient time estimation for wireless sensor networks.	DIALM-POMC	2004	DBLP DOI BibTeX RDF	clock drift rate, clock synchronization, time series forecasting, time estimation, resource efficiency
50	Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Energy recovery clocking scheme and flip-flops for ultra low-energy applications.	ISLPED	2003	DBLP DOI BibTeX RDF	flip-flop, clock, clock tree, energy recovery, adiabatic
49	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	A single layer zero skew clock routing in X architecture.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	single layer, X architecture, zero skew, clock routing
49	Christoph Lenzen 0001, Thomas Locher, Roger Wattenhofer	Tight bounds for clock synchronization.	PODC	2009	DBLP DOI BibTeX RDF	gradient property, optimal skew bounds, clock synchronization
49	Fabian Kuhn, Rotem Oshman	Gradient Clock Synchronization Using Reference Broadcasts.	OPODIS	2009	DBLP DOI BibTeX RDF	Gradient Clock Synchronization, Wireless Networks
49	Venkatesh Arunachalam, Wayne P. Burleson	Low-power clock distribution in a multilayer core 3d microprocessor.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	3D ic's, 3D processor architectures, clock grids
49	Rui Fan 0004, Nancy A. Lynch	Gradient clock synchronization.	Distributed Comput.	2006	DBLP DOI BibTeX RDF	Ad-hoc networks, Lower bounds, Clock synchronization, Indistinguishability
49	Xinjie Wei, Yici Cai, Meng Zhao, Xianlong Hong	Legitimate Skew Clock Routing with Buffer Insertion.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	legitimate skew, buffer insertion, clock routing
49	Yongqiang Lu 0001, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Liang Huang, Jiang Hu	Navigating registers in placement for clock network minimization.	DAC	2005	DBLP DOI BibTeX RDF	low power, placement, clock network, variation tolerance
49	Kai Wang 0011, Malgorzata Marek-Sadowska	Buffer sizing for clock power minimization subject to general skew constraints.	DAC	2004	DBLP DOI BibTeX RDF	sequential linear programming, sizing, clock skew scheduling
49	Anand Rajaram, Jiang Hu, Rabi N. Mahapatra	Reducing clock skew variability via cross links.	DAC	2004	DBLP DOI BibTeX RDF	VLSI, physical design, variation, clock network synthesis
49	Jindrich Zejda, Paul Frain	General framework for removal of clock network pessimism.	ICCAD	2002	DBLP DOI BibTeX RDF	clock network reconvergence, voltage and temperature delay variation, process, static timing analysis, deep sub-micron
49	Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen	Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.	DAC	2002	DBLP DOI BibTeX RDF	di/dt noise, low-noise digital design, supply current shaping, optimization, substrate noise, clock distribution networks
49	Nestoras Tzartzanis, William C. Athas	Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing.	ARVLSI	1999	DBLP DOI BibTeX RDF	low-power digital CMOS, adiabatic switching, clock-powered logic, energy recovery
49	Martin Saint-Laurent, Animesh Datta	A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology.	ISLPED	2010	DBLP DOI BibTeX RDF	clock gater, clock gating cell, local clock buffer, set-reset latch
48	Attila Pásztor, Darryl Veitch	PC based precision timing without GPS.	SIGMETRICS	2002	DBLP DOI BibTeX RDF	pc clocks, software clock, synchronization, timing, GPS, network measurement, NTP
48	Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi	Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks.	ISQED	2009	DBLP DOI BibTeX RDF
48	Yesin Ryu, Taewhan Kim	Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization.	ICCAD	2008	DBLP DOI BibTeX RDF
48	Ashok Narasimhan, Ramalingam Sridhar	Impact of Variability on Clock Skew in H-tree Clock Networks.	ISQED	2007	DBLP DOI BibTeX RDF
48	Shih-Hsu Huang, Yow-Tyng Nieh	Clock Period Minimization of Non-Zero Clock Skew Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF
48	Haksu Kim, Dian Zhou	An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
48	Olivier Bezet, Véronique Berge-Cherfaoui	On-line and post-processing timestamp correspondence for free-running clock nodes, using a network clock.	Real Time Syst.	2008	DBLP DOI BibTeX RDF	Timestamping conversion, Timestamping error modeling, Free running clock nodes, Network clock, Distributed architecture
47	Qiang Wang, Subodh Gupta, Jason Helge Anderson	Clock power reduction for virtex-5 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
47	Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay	Slew-aware clock tree design for reliable subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	slew, clocks, subthreshold
47	Anand Rajaram, Raguram Damodaran, Arjun Rajagopal	Practical Clock Tree Robustness Signoff Metrics.	ISQED	2008	DBLP DOI BibTeX RDF
47	Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan	Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis.	ISQED	2007	DBLP DOI BibTeX RDF