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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2136 occurrences of 698 keywords
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Results
Found 1485 publication records. Showing 1485 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
82 | Ameet Bagwe, Rubin A. Parekhji |
Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 260-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fault coverage enhancement, embedded core based systems, test constraints, Texas Instruments TMS320C27xx, memory wrapper logic, fault diagnosis, logic testing, integrated circuit testing, application specific integrated circuits, functional testing, digital signal processing chips, fault analysis |
80 | Hailong Cui, Sharad C. Seth, Shashank K. Mehta |
Modeling Fault Coverage of Random Test Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 271-284, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
fault-coverage prediction, cost-benefit analysis of fault simulation, variance of fault coverage, BIST, probabilistic model |
74 | Albert F. Myers |
k-out-of-n: G System Reliability With Imperfect Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 56(3), pp. 464-473, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
65 | Gabriel M. Silberman, Ilan Y. Spillinger |
Using functional fault simulation and the difference fault model to estimate implementation fault coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12), pp. 1335-1343, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
64 | Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas |
Statistical path delay fault coverage estimation for synchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 290-295, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
path delay fault coverage estimation, multi-valued algebra, signal statistics, latch updating, fault diagnosis, logic testing, delays, probability, controllability, controllability, statistical analysis, sequential circuits, observability, observabilities, logic simulation, synchronous sequential circuits, statistical estimation |
64 | Peter C. Maxwell, Robert C. Aitken |
IDDQ testing as a component of a test suite: The need for several fault coverage metrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 305-316, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
quality, fault coverage, scan, functional testing, Current testing, physical defects |
61 | Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell |
Statistical methods for delay fault coverage analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 166-170, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
delay fault coverage analysis, true value simulation, multi-value logic system, implicit random path sampling procedure, linear-time estimate, fault coverage estimates, longest path theorem, fanout branches, fault diagnosis, logic testing, delays, probability, statistical analysis, observabilities, multivalued logic, propagation delay, detection probabilities, statistical techniques, transition probabilities |
59 | Kwang-Ting Cheng |
Transition fault testing for sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12), pp. 1971-1983, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
59 | Shanrui Zhang, Minsu Choi, Nohpill Park, Fabrizio Lombardi |
Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 48-56, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
58 | Albert F. Myers, Antoine Rauzy |
Efficient Reliability Assessment of Redundant Systems Subject to Imperfect Fault Coverage Using Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 57(2), pp. 336-348, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
57 | Wangqi Qiu, Xiang Lu, Jing Wang 0006, Zhuo Li 0001, D. M. H. Walker, Weiping Shi |
A Statistical Fault Coverage Metric for Realistic Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 37-42, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
57 | Yi Zhao, Sujit Dey |
Fault-coverage analysis techniques of crosstalk in chip interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6), pp. 770-782, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
57 | Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu |
Defect Level Prediction Using Multi-Model Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 301-, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
57 | Von-Kyoung Kim, Tom Chen 0001, Mick Tegethoff |
Fault Coverage Estimation for Early Stage of VLSI Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 105-108, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
56 | Irith Pomeranz, Sudhakar M. Reddy |
Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1), pp. 137-146, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
54 | Von-Kyoung Kim, Tom Chen 0001 |
On comparing functional fault coverage and defect coverage for memory testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11), pp. 1676-1683, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
53 | Puneet Gupta 0001, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma |
Layout-aware scan chain synthesis for improved path delay fault coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7), pp. 1104-1114, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Abdeslam En-Nouaary, Ferhat Khendek, Rachida Dssouli |
Fault Coverage in Testing Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 6th International Workshop on Real-Time Computing and Applications Symposium (RTCSA '99), 13-16 December 1999, Hong Kong, China, pp. 150-157, 1999, IEEE Computer Society, 0-7695-0306-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Real-Time Systems, Testing, Specification, Implementation, Timed Automata, Fault Coverage |
50 | Jayant Deodhar, Spyros Tragoudas |
Color Counting and its Application to Path Delay Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 378-383, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
49 | Sezer Gören 0001, F. Joel Ferguson |
Test sequence generation for controller verification and test with high coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(4), pp. 916-938, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
finite state machine, Fault coverage, black box testing, X-machine |
49 | Sumit Ghosh, Tapan J. Chakraborty |
On behavior fault modeling for digital designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(2), pp. 135-151, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
fault coverage correlation, fault model, fault simulation, stuck-at fault, behavior model |
49 | Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul |
Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 182-188, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
49 | William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
Delay fault coverage, test set size, and performance trade-offs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1), pp. 32-44, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
48 | Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul |
A test evaluation technique for VLSI circuits using register-transfer level fault modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8), pp. 1104-1113, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
48 | Irith Pomeranz, Sudhakar M. Reddy |
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1166-1171, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
48 | Albert F. Myers |
Achievable Limits on the Reliability of k-out-of-n: G Systems Subject to Imperfect Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 57(2), pp. 349-354, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
Improving accuracy in path delay fault coverage estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 422-425, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
fault coverage estimation, simulated vector pair, exact fault simulation, fixed-length path-segments, fan-in branches, fan-out branches, flagged path-segments, segment lengths, combinational paths, graph theory, fault diagnosis, logic testing, delays, combinational circuits, logic CAD, circuit analysis computing, path delay fault, approximate methods, CPU time |
47 | Dali L. Tao, Carlos R. P. Hartmann |
A Novel Concurrent Error Detection Scheme for FFT Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(2), pp. 198-221, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
concurrent error detection scheme, FFT networks, algorithm-based fault tolerancetechniques, digital signalprocessing chips, fault tolerant computing, fast Fourier transforms, error detection, fault coverage, system performance, roundoff errors, round-off errors |
47 | Yung-Ruei Chang, Suprasad V. Amari, Sy-Yen Kuo |
OBDD-Based Evaluation of Reliability and Importance Measures for Multistate Systems Subject to Imperfect Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Dependable Secur. Comput. ![In: IEEE Trans. Dependable Secur. Comput. 2(4), pp. 336-347, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multistate system, importance measure, Reliability, fault-coverage, OBDD |
47 | V. Prepin, R. David |
Fault coverage of a long random test sequence estimated from a short simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 391-398, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
long random test sequence, short simulation, fault coverage estimation, two-parameter model, fault diagnosis |
47 | Karim Arabi, Bozena Kaminska |
Parametric and Catastrophic Fault Coverage of Analog Circuits in Oscillation-Test Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 166-171, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Oscillation-Test Method, Parametric Fault Coverage, Analog Testing, Mixed-Signal Circuits |
47 | Marc D. Riedel, Janusz Rajski |
Fault coverage analysis of RAM test algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 227-234, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
RAM test algorithms, flexible software analysis program, arbitrary test sequences, coverage statistics, functional cell-array faults, fault state transition conditions, representative fault classes, fault diagnosis, integrated circuit testing, fault coverage, random-access storage, integrated memory circuits, semiconductor memories, test algorithms |
46 | Eun Sei Park, M. Ray Mercer, Thomas W. Williams |
The Total Delay Fault Model and Statistical Delay Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(6), pp. 688-698, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
delay fault model, delay fault coverage, statistical delay fault coverage, defect level model, logic testing, delay testing, delay faults |
46 | Xia Cai, Michael R. Lyu |
The effect of code coverage on fault detection under different testing profiles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGSOFT Softw. Eng. Notes ![In: ACM SIGSOFT Softw. Eng. Notes 30(4), pp. 1-7, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
software testing, fault detection, code coverage |
46 | Xia Cai, Michael R. Lyu |
The effect of code coverage on fault detection under different testing profiles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-MOST ![In: Proceedings of the ICSE 2005 Workshop on Advances in Model-Based Software Testing, A-MOST 2005, St. Louis, Missouri, USA, 2005, ACM, 1-59593-115-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
software testing, fault detection, code coverage |
46 | Wilfried Daehn |
Fault simulation using small fault samples. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(2), pp. 191-203, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
confidence level, sampling, fault simulation, Bayesian estimation |
46 | Thomas W. Williams, Stephen K. Sunter |
How Should Fault Coverage Be Defined? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 325-328, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
46 | Luca Simoncini, Arthur D. Friedman |
Incomplete Fault Coverage In Modular Miltiprocessor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Annual Conference (1) ![In: Proceedings 1978 ACM Annual Conference, Washington, DC, USA, December 4-6, 1978, Volume I, pp. 210-216, 1978, ACM, 978-0-89791-000-2. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
|
45 | Deepinder P. Sidhu, Ting-Kau Leung |
Formal Methods for Protocol Testing: A Detailed Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 15(4), pp. 413-426, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
NBS Class 4 Transport Protocol, protocol-test-sequence generation techniques, real-world communication protocols, protocols, fault detection, fault coverage, fault coverage, conformance testing, Monte Carlo methods, Monte Carlo simulation, failure analysis, test sequences, protocol implementation, protocol testing |
45 | Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi |
Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2954-2964, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
45 | Xiao Sun 0002, Carmie Hull |
Functional Verification Coverage vs. Physical Stuck-at Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 108-116, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
functional property, stuck-at fault coverage, verification coverage, UIO, verification, validation, ATPG, FSM, signature analysis, test application time |
43 | Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas |
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(3), pp. 239-254, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
statistical fault analysis, fault simulation, delay test, path-delay faults, transition faults |
43 | Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges |
Statistical estimation of delay fault detectabilities and fault grading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(1), pp. 47-60, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
transition delay and path delay faults, statistical delay fault analysis, fault detectabilities, fault coverage, random patterns |
43 | K. Vijayananda |
Distributed fault detection in communication protocols using extended finite state machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 310-318, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
distributed fault detection, run-time fault detection, coding defects, memory problems, protocol faults, vocabulary faults, sequencing faults, parallel decomposition method, multiple observers, distributed fault detection mechanism, fault tolerant computing, finite state machines, transport protocols, encoding, communication protocols, fault coverage, extended finite state machines |
43 | Yuyun Liao, D. M. H. Walker |
Optimal voltage testing for physically-based faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 344-353, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise |
43 | Irith Pomeranz, Sudhakar M. Reddy |
Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(7), pp. 931-936, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Mukund Sivaraman, Andrzej J. Strojwas |
Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 494-501, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
fabrication process, coverage, delay testing, delay fault, path sensitization |
42 | Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams |
On the decline of testing efficiency as fault coverage approaches 100%. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 74-83, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
single stuck-at fault model, ISCAS benchmark circuits, nontarget defects, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault coverage, test pattern generation, manufacturing process, test quality, production testing, testing efficiency, circuit sizes |
41 | Sanghyeon Baeg |
Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12), pp. 2215-2221, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Yinan N. Shen, Fabrizio Lombardi, Donatella Sciuto |
Evaluation and improvement of fault coverage for verification and validation of protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPDP ![In: Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, SPDP 1990, Dallas, Texas, USA, December 9-13, 1990., pp. 200-207, 1990, IEEE Computer Society, 0-8186-2087-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
41 | Krishnendu Chakrabarty, John P. Hayes |
On the quality of accumulator-based compaction of test responses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8), pp. 916-922, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
40 | Mitrajit Chatterjee, Dhiraj K. Pradhan |
A BIST Pattern Generator Design for Near-Perfect Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(12), pp. 1543-1558, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
core logic, built-in self-test, synthesis, fault coverage, Linear feedback shift registers, test pattern generation, scan, SOC |
40 | Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das |
Delay Fault Coverage Enhancement Using Variable Observation Times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(2), pp. 131-146, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
statistical delay fault coverage, delay test observation times, delay fault testing |
40 | Mitrajit Chatterjee, Dhiraj K. Pradhan |
A novel pattern generator for near-perfect fault-coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 417-425, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
near-perfect fault-coverage, onchip BIST, GLFSR, logic mapping technique, weighted pattern technique, logic testing, built-in self test, integrated circuit testing, design methodology, combinational circuits, automatic testing, integrated logic circuits, shift registers, combinational logic, digital integrated circuits, pattern generator, single stuck-at fault |
39 | Michael S. Hsiao |
On Non-Statistical Techniques for Fast Fault Coverage Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(3), pp. 239-254, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
fault coverage estimation, hyperactivity reduction, test generation, fault simulation, tolerance |
39 | Zhen Chen, Boxue Yin, Dong Xiang |
Conflict driven scan chain configuration for high transition fault coverage and low test power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 666-671, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
39 | Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte |
On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 143-151, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Chen Fu, Richard P. Martin, Kiran Nagaraja, Thu D. Nguyen, Barbara G. Ryder, David Wonnacott |
Compiler-Directed Program-Fault Coverage for Highly Available Java Internet Services. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2003 International Conference on Dependable Systems and Networks (DSN 2003), 22-25 June 2003, San Francisco, CA, USA, Proceedings, pp. 595-604, 2003, IEEE Computer Society, 0-7695-1952-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
39 | Dimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis |
Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(3), pp. 309-315, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
38 | Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, Kun-Cheng Wu |
Fault modeling and testing of retention flip-flops in low power designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 684-689, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
38 | Alexandre Petrenko |
Fault Model-Driven Test Derivation from Finite State Models: Annotated Bibliography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOVEP ![In: Modeling and Verification of Parallel Processes, 4th Summer School, MOVEP 2000, Nantes, France, June 19-23, 2000, pp. 196-205, 2000, Springer, 3-540-42787-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
38 | Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Mike Rodgers |
Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(2), pp. 195-205, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
static faults, fault models, fault coverage, memory tests, dynamic faults, fault primitives |
38 | Vadim Trenkaev, Myungchul Kim 0001, Soonuk Seol |
Interoperability Testing Based on a Fault Model for a System of Communicating FSMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TestCom ![In: Testing of Communicating Systems, 15th IFIP International Conference, TestCom 2003, Sophia Antipolis, France, May 26-28, 2003, Proceedings, pp. 226-242, 2003, Springer, 3-540-40123-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Jien-Chung Lo |
Analysis of a BICS-Only Concurrent Error Detection Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(3), pp. 241-253, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
unsafe probability, reliability, fault coverage, testability, concurrent error detection, built-in current sensors, operating speed |
37 | Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal |
Compaction-based test generation using state and fault information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 159-164, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
compaction-based test generation, newly-traversed state information, newly-detected fault information, vector compaction iterations, vector sequence bias, biased vectors, compacted test set extension, intelligent vector selection, state analysis, fault diagnosis, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, iterative methods, vectors, fault coverage, circuit analysis computing, fault analysis, benchmark circuits, computing resources, vector generation |
37 | André Postma, Gerie Hartman, Thijs Krol |
Removal of all Faulty Nodes from a Fault-Tolerant Service by means of Distributed Diagnosis with Imperfect Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Dependable Computing - EDCC-2, Second European Dependable Computing Conference, Taormina, Italy, October 2-4, 1996, Proceedings, pp. 385-402, 1996, Springer, 3-540-61772-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
37 | Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche |
Test Challenges in Nanometer Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(3-4), pp. 209-218, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
circuit marginality testing, process marginality testing, defect based testing, path delay testing |
36 | Warren H. Debany Jr., Kevin A. Kwiat, Sami A. Al-Arian |
A Method for Consistent Fault Coverage Reporting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 10(3), pp. 68-79, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
36 | Ad J. van de Goor, Georgi Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik |
March LR: a test for realistic linked faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 272-280, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
disturb faults, March LR, March LRD, March LRDD, fault diagnosis, integrated circuit testing, fault models, fault coverage, march tests, integrated memory circuits, semiconductor memories, linked faults |
36 | C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal |
A STAFAN-like functional testability measure for register-level circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 192-198, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model |
36 | Bjørg Reppen, Einar J. Aas |
Combined probabilistic testability calculation and compact test generation for PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(3), pp. 215-227, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
probabilistic testability, Fault coverage, test pattern generation, programmable logic arrays |
36 | Marie-Lise Flottes, Christian Landrault, A. Petitqueux |
Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 404-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
sequential testability, internal state reseeding, observation points, minimum DFT insertion, non-scan approach, fault efficiency, 100 percent, fault diagnosis, logic testing, controllability, controllability, design for testability, logic design, sequential circuits, automatic test pattern generation, ATPG, observability, fault coverage, flip-flops, at-speed testing, benchmark circuits, CPU time, partial reset |
36 | Michel Renovell, P. Huc, Yves Bertrand |
Bridging fault coverage improvement by power supply control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 338-343, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
bridging fault coverage, power supply control, resistance interval, faulty value, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, automatic testing, logic circuits, parametric model, benchmark circuits |
36 | Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy |
Resource-Constrained Compaction of Sequential Circuit Test Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 398-405, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara |
On Test Generation with A Limited Number of Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 12-15, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
36 | Margot Karam, Gabriele Saucier |
Functional versus random test generation for sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(1), pp. 33-41, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
simulation, Finite state machine, functional testing, graph traversal |
36 | Wei Li 0023, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy |
Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 471-478, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Shambhu J. Upadhyaya, Kewal K. Saluja |
A new approach to the design of built-in self-testing PLAs for high fault coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1), pp. 60-67, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
35 | Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali |
Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 485-492, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee |
SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 274-281, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
SPITFIRE, scalable parallel algorithms, test set partitioned fault simulation, synchronous parallel algorithms, sequential VLSI circuits, VLSI, fault coverage |
35 | Joseph L. A. Hughes |
Multiple fault detection using single fault test sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1), pp. 100-108, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
35 | V. R. Devanathan |
Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 300-305, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng |
An almost full-scan BIST solution-higher fault coverage and shorter test application time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 1065-1073, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
35 | Heidrun Engel |
Data flow transformations to detect results which are corrupted by hardware faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HASE ![In: 1st High-Assurance Systems Engineering Workshop (HASE '96), October 22, 1996, Niagara, Canada, Proceedings, pp. 279-, 1996, IEEE Computer Society, 0-8186-7629-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
data flow transformations, corrupt result detection, hardware fault coverage, modified instruction, diverse data representation, modified instruction sequences, assembler level, high language level, fault tolerant computing, software faults, design diversity, hardware fault detection |
35 | Ajay Khoche, Erik Brunvand |
A partial scan methodology for testing self-timed circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 283-289, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
partial scan methodology, control section testing, macromodule based circuits, sequential network, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault coverage, stuck-at faults, integrated logic circuits, boundary scan testing, self-timed circuits |
34 | Irith Pomeranz, Sudhakar M. Reddy |
Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(3), pp. 269-278, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Salvador Mir, Adoración Rueda, Diego Vázquez, José Luis Huertas |
Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 810-814, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell |
Fault coverage estimation by test vector sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5), pp. 590-596, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
33 | Janusz Sosnowski |
Improving Fault Coverage in System Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 207-213, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
In system testing, test controllability and observability, fault coverage analysis, on-line monitoring |
33 | Nan-Cheng Lai, Sying-Jyan Wang, Y.-H. Fu |
Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2586-2594, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Amitava Majumdar 0001, Sarma B. K. Vrudhula |
Techniques for estimating test length under random test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(2-3), pp. 285-297, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
urn models, test quality, Circuit testing, waiting time distribution |
32 | Ghassan Al Hayek, Chantal Robach |
On the Adequacy of Deriving Hardware Test Data from the Behavioral Specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 337-342, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
hardware test data, behavioral fault modeling, gate-level strategies, high-level fault detection, gate-level fault detection, design automation tools, generated test set, gate-level fault coverage, hardware description languages, hardware description languages, behavioral specification |
32 | Michel Renovell, P. Huc, Yves Bertrand |
The concept of resistance interval: a new parametric model for realistic resistive bridging fault. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 184-189, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
electric resistance, resistance interval, intrinsic resistance, logic behavior, 0 to 500 ohm, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, fault detection, automatic testing, fault coverage, bridging faults, parametric model, logic gates, logic gates, resistive bridging fault, faulty behavior |
32 | Udo Mahlstedt, Jürgen Alt, Matthias Heinitz |
CURRENT: a test generation system for IDDQ testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 317-323, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults |
32 | Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy |
Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 83-94, 2006, ACM, 1-59593-451-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
redundant multithreading, simultaneous multithreading (SMT), slipstream processor, chip multiprocessor (CMP), branch prediction, transient faults, value prediction, time redundancy |
32 | Zhuo Zhang 0008, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi |
Enhancing Delay Fault Coverage through Low Power Segmented Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pp. 21-28, 2006, IEEE Computer Society, 0-7695-2566-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz |
Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 202-207, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Suprasad V. Amari, Hoang Pham, G. Dill |
Optimal design of k-out-of-n: G subsystems subjected to imperfect fault-coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 53(4), pp. 567-575, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Irith Pomeranz, Sudhakar M. Reddy |
Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(7), pp. 780-788, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Junichi Hirase, Shinichi Yoshimura, Tomohisa Sczaki |
Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 13-19, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
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