Search results for "intra-die"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
69	Sani R. Nassif	Design for Variability in DSM Technologies.	ISQED	2000	DBLP DOI BibTeX RDF
62	Qiang Fu, Wai-Shing Luk, Jun Tao 0001, Changhao Yan, Xuan Zeng 0001	Characterizing Intra-Die Spatial Correlation Using Spectral Density Method.	ISQED	2008	DBLP DOI BibTeX RDF	intra-die variation, spectral domain, spectral density, spatial correlation
62	Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao 0001	Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits.	DAC	2006	DBLP DOI BibTeX RDF	Karhunen-Loeve, intra-die, correlations, process variations, statistical, leakage
61	Daniel Iparraguirre-Cardenas, Jose Luis Garcia-Gervacio, Víctor H. Champac	A design methodology for logic paths tolerant to local intra-die variations.	ISCAS	2008	DBLP DOI BibTeX RDF
61	Jianfeng Luo, Subarna Sinha, Qing Su, Jamil Kawa, Charles C. Chiang	An IC manufacturing yield model considering intra-die variations.	DAC	2006	DBLP DOI BibTeX RDF	random variation, systematic variation, CMP, spatial correlation, manufacturing yield
50	Vineeth Veetil, Dennis Sylvester, David T. Blaauw, Saumil Shah, Steffen Rochel	Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence.	DAC	2009	DBLP DOI BibTeX RDF	statistical leakage, Monte Carlo, variance reduction
50	Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril	Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations.	VLSI Design	2007	DBLP DOI BibTeX RDF
45	Abhranil Maiti, Patrick Schaumont	Impact and compensation of correlated process variation on ring oscillator based puf.	FPGA	2009	DBLP DOI BibTeX RDF	correlated process variation, physical unclonable function (puf), ring oscillator (ro), fpga
45	Rajeev R. Rao, Ashish Srivastava, David T. Blaauw, Dennis Sylvester	Statistical estimation of leakage current considering inter- and intra-die process variation.	ISLPED	2003	DBLP DOI BibTeX RDF	variability, Monte Carlo, leakage current
39	Marshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma	A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	current mode singnaling, dynamic overdriving, process variation tolerant
39	Aseem Agarwal, David T. Blaauw, Vladimir Zolotov	Statistical Clock Skew Analysis Considering Intra-Die Process Variations.	ICCAD	2003	DBLP DOI BibTeX RDF
34	Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De	Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.	ISLPED	2006	DBLP DOI BibTeX RDF	intra-die variations, multi-cycle interconnect, parameter fluctuations, time borrowing, interconnect, parameter variations, within-die variations, variation tolerant
33	Bram Kruseman, Stefan van den Oetelaar	Detection of Resistive Shorts in Deep Sub-micron Technologies.	ITC	2003	DBLP DOI BibTeX RDF
33	Aseem Agarwal, David T. Blaauw, Vladimir Zolotov	Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations.	ICCAD	2003	DBLP DOI BibTeX RDF
28	Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy 0001	Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry.	VTS	2008	DBLP DOI BibTeX RDF	Design, yield, failure, SRAM, variation
28	Hongliang Chang, Sachin S. Sapatnekar	Statistical timing analysis under spatial correlations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
28	Paul S. Zuchowski, Peter A. Habitz, J. D. Hayes, J. H. Oppold	Process and environmental variation impacts on ASIC timing.	ICCAD	2004	DBLP DOI BibTeX RDF
28	Amith Singhee, Sonia Singhal, Rob A. Rutenbar	Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing.	DATE	2008	DBLP DOI BibTeX RDF
28	Jeff Mueller, Resve A. Saleh	A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks.	ISQED	2008	DBLP DOI BibTeX RDF
28	Sarvesh Bhardwaj, Sarma B. K. Vrudhula	A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations.	VLSI Design	2007	DBLP DOI BibTeX RDF
28	Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda	Stochastic variational analysis of large power grids considering intra-die correlations.	DAC	2006	DBLP DOI BibTeX RDF	orthonormal polynomials, correlations, process variations, power grids, stochastic analysis, polynomial chaos
28	Hratch Mangassarian, Mohab Anis	On Statistical Timing Analysis with Inter- and Intra-Die Variations.	DATE	2005	DBLP DOI BibTeX RDF
28	M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf	The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
26	Meysam Taassori, Ali Shafiee, Rajeev Balasubramonian	Understanding and alleviating intra-die and intra-DIMM parameter variation in the memory system.	ICCD	2016	DBLP DOI BibTeX RDF
25	Vladimir Pasca, Lorena Anghel, Claudia Rusu, Riccardo Locatelli, Massimo Coppola	Error resilience of intra-die and inter-die communication with 3D spidergon STNoC.	DATE	2010	DBLP DOI BibTeX RDF
23	Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw	Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
23	Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw	A statistical framework for post-silicon tuning through body bias clustering.	ICCAD	2006	DBLP DOI BibTeX RDF
23	Cassondra Neau, Kaushik Roy 0001	Optimal body bias selection for leakage improvement and process compensation over different technology generations.	ISLPED	2003	DBLP DOI BibTeX RDF	band-to-band tunneling, leakage components, process compensation, substrate bias, process variation, leakage current, CMOS scaling, body bias
23	Carlo Guardiani, Sharad Saxena, Patrick McNamara, Phillip Schumaker, Dale Coder	An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
23	Tuna B. Tarim, Mohammed Ismail 0001	Functional yield enhancement and statistical design of a low power transconductor.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
22	Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri	Dynamically De-Skewable Clock Distribution Methodology.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
22	Chintan Patel, Abhishek Singh 0001, Jim Plusquellic	Defect Detection Using Quiescent Signal Analysis.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	multiple current measurements, Quiescent Signal Analysis, IDDQ, current testing, defect-based testing, parametric testing
22	Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri	A novel clock distribution and dynamic de-skewing methodology.	ICCAD	2004	DBLP DOI BibTeX RDF
17	Kiyoo Itoh 0001	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.	ISLPED	2009	DBLP DOI BibTeX RDF	0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
17	Soner Yaldiz, Umut Arslan, Xin Li 0001, Larry T. Pileggi	Efficient statistical analysis of read timing failures in SRAM circuits.	ISQED	2009	DBLP DOI BibTeX RDF
17	Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David T. Blaauw	A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
17	Abu Saad Papa, Madhu Mutyam	Power management of variation aware chip multiprocessors.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	chipmulti-processor, process variation, power-aware, adaptive voltage scaling
17	Shaobo Liu, Qinru Qiu, Qing Wu 0002	Full-chip leakage current estimation based on statistical sampling techniques.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	leakage estimation, statistical sampling, vlsi
17	Amit Goel, Sarma B. K. Vrudhula, Feroze Taraporevala, Praveen Ghanta	A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations.	ISQED	2008	DBLP DOI BibTeX RDF
17	Sebastian Herbert, Diana Marculescu	Characterizing chip-multiprocessor variability-tolerance.	DAC	2008	DBLP DOI BibTeX RDF	frequency islands, chip-multiprocessor, process variability
17	Xiaoji Ye, Frank Liu 0001, Peng Li 0001	Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
17	Francesco Centurelli, Luca Giancane, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti	A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations.	PATMOS	2007	DBLP DOI BibTeX RDF
17	Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Statistical model order reduction for interconnect circuits considering spatial correlations.	DATE	2007	DBLP DOI BibTeX RDF
17	Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan	Voltage drop reduction for on-chip power delivery considering leakage current variations.	ICCD	2007	DBLP DOI BibTeX RDF
17	Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy 0001	Tolerance to Small Delay Defects by Adaptive Clock Stretching.	IOLTS	2007	DBLP DOI BibTeX RDF
17	Sarma B. K. Vrudhula, Sarvesh Bhardwaj	Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations.	VLSI Design	2007	DBLP DOI BibTeX RDF
17	Zhuo Feng, Peng Li 0001, Yaping Zhan	Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction.	DAC	2007	DBLP DOI BibTeX RDF
17	Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy 0001	Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
17	Domenik Helms, Marko Hoyer, Wolfgang Nebel	Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage.	PATMOS	2006	DBLP DOI BibTeX RDF
17	Priya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan	Thermal characterization and optimization in platform FPGAs.	ICCAD	2006	DBLP DOI BibTeX RDF	Virtex4, platform FPGAs, thermal floorplan, placement, temperature, thermal
17	Xiaoji Ye, Peng Li 0001, Frank Liu 0001	Practical variation-aware interconnect delay and slew analysis for statistical timing verification.	ICCAD	2006	DBLP DOI BibTeX RDF
17	Eugenio Culurciello, Andreas G. Andreou	3D integrated sensors in silicon-on-sapphire CMOS.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Kaushik Roy 0001	Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM.	DAC	2006	DBLP DOI BibTeX RDF	adaptive source biasing, hold failures, low power SRAM
17	Xin Li 0001, Jiayong Le, Lawrence T. Pileggi	Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions.	DAC	2006	DBLP DOI BibTeX RDF	statistical analysis, leakage power
17	Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy 0001	Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
17	Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy 0001	Statistical Timing Analysis using Levelized Covariance Propagation.	DATE	2005	DBLP DOI BibTeX RDF
17	Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy 0001	Process Variation Tolerant Online Current Monitor for Robust Systems.	IOLTS	2005	DBLP DOI BibTeX RDF
17	Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Stephen W. Director	Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance.	DAC	2005	DBLP DOI BibTeX RDF	correlation, variability, yield, leakage
17	Jiayong Le, Xin Li 0001, Lawrence T. Pileggi	STAC: statistical timing analysis with correlation.	DAC	2004	DBLP DOI BibTeX RDF	process variation, statistical timing
17	José Pineda de Gyvez, Rosa Rodríguez-Montañés	Threshold Voltage Mismatch (DeltaVT) Fault Modeling.	VTS	2003	DBLP DOI BibTeX RDF
17	Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche	Test Challenges in Nanometer Technologies.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	circuit marginality testing, process marginality testing, defect based testing, path delay testing
17	Wieslaw Kuzmicz	Internet-Based Virtual Manufacturing: A Verification Tool for IC Designs.	ISQED	2000	DBLP DOI BibTeX RDF	analog IC design, statistical simulation, virtual manufacturing
17	Zahira Perez, Hector Villacorta, Víctor H. Champac	An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
17	Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue, Alex Orailoglu	Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection.	ATS	2017	DBLP DOI BibTeX RDF
17	Víctor H. Champac, Alejandra Nicte-ha Reyes, Andres F. Gomez	Circuit performance optimization for local intra-die process variations using a gate selection metric.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
17	Youngok K. Pino, Vinayaka Jyothi, Matthew French	Intra-die process variation aware anomaly detection in FPGAs.	ITC	2014	DBLP DOI BibTeX RDF
17	Jeffrey G. Mueller, Resve A. Saleh	Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
17	Mohd Azman Abdul Latif, Noohul Basheer Zain Ali, Fawnizu Azmadi Hussin	IDVP (Intra-Die Variation Probe) for System-On-Chip (SoC) Infant Mortality screen.	ISCAS	2011	DBLP DOI BibTeX RDF
17	Luís Guerra e Silva, Luís Miguel Silveira	Handling intra-die variations in PSTA.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
17	Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici	Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing.	PATMOS	2010	DBLP DOI BibTeX RDF
17	Qiang Fu, Wai-Shing Luk, Jun Tao 0001, Xuan Zeng 0001, Wei Cai 0003	Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2009	DBLP DOI BibTeX RDF
17	Qiang Fu, Wai-Shing Luk, Jun Tao 0001, Changhao Yan, Xuan Zeng 0001	Characterizing Intra-Die Spatial Correlation Using Spectral Density Fitting Method.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2009	DBLP DOI BibTeX RDF
17	Zhuo Feng, Peng Li 0001, Zhuoxiang Ren	SICE: design-dependent statistical interconnect corner extraction under inter/intra-die variations.	IET Circuits Devices Syst.	2009	DBLP DOI BibTeX RDF
17	David Levacq, Takuya Minakawa, Makoto Takamiya, Takayasu Sakurai	A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS.	CICC	2007	DBLP DOI BibTeX RDF
17	Manjari Agarwal, Praveen Elakkumanan, Ramalingam Sridhar	Intra-die process parameter variation and leakage analysis of cache at the microarchitectural level.	SoCC	2007	DBLP DOI BibTeX RDF
17	Amit Agarwal 0001, Kunhyuk Kang, Kaushik Roy 0001	Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations.	ICCAD	2005	DBLP DOI BibTeX RDF
17	Xin Li 0001, Peng Li 0001, Lawrence T. Pileggi	Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations.	ICCAD	2005	DBLP DOI BibTeX RDF
17	Xin Li 0001, Jiayong Le, Lawrence T. Pileggi, Andrzej J. Strojwas	Projection-based performance modeling for inter/intra-die variations.	ICCAD	2005	DBLP DOI BibTeX RDF
17	José Pineda de Gyvez, Hans Tuinhout	Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
17	Tom W. Chen, Justin Gregg	A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations.	DATE	2004	DBLP DOI BibTeX RDF
17	M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf	The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits.	ISLPED	1996	DBLP DOI BibTeX RDF
11	Zhuo Feng, Peng Li 0001, Yaping Zhan	An On-the-Fly Parameter Dimension Reduction Approach to Fast Second-Order Statistical Static Timing Analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
11	Jifeng Chen, Jin Sun 0006, Janet Meiling Wang	Robust interconnect communication capacity algorithm by geometric programming.	ISPD	2009	DBLP DOI BibTeX RDF	communication capacity, optimization, robust, uncertainty, process variation, geometric programming, ellipsoid
11	Atanu Chattopadhyay, Zeljko Zilic	Serial reconfigurable mismatch-tolerant clock distribution.	DAC	2009	DBLP DOI BibTeX RDF	process variation, clock skew, clock networks
11	Norbert Dumas, Florence Azaïs, Frédérick Mailly, Andrew Richardson 0001, Pascal Nouet	A novel method for test and calibration of capacitive accelerometers with a fully electrical setup.	DDECS	2008	DBLP DOI BibTeX RDF
11	Bao Liu 0001	Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression.	DATE	2008	DBLP DOI BibTeX RDF
11	Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	Failure analysis for ultra low power nano-CMOS SRAM under process variations.	SoCC	2008	DBLP DOI BibTeX RDF
11	Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai	Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM.	ISQED	2008	DBLP DOI BibTeX RDF
11	Muhammad Mudassar Nisar, Abhijit Chatterjee	Test Enabled Process Tuning for Adaptive Baseband OFDM Processor.	VTS	2008	DBLP DOI BibTeX RDF	Adaptive Signal Scaling, Timing test, Low power, OFDM
11	Amir M. Amiri, Abdelhakim Khouas, Mounir Boukadoum	On the Timing Uncertainty in Delay-Line-based Time Measurement Applications Targeting FPGAs.	ISCAS	2007	DBLP DOI BibTeX RDF
11	Antonis Papanikolaou, Miguel Miranda, Hua Wang, Francky Catthoor, M. Satyakiran, Pol Marchal, Ben Kaczer, C. Bruynseraede, Zsolt Tokei	Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
11	Mongkol Ekpanyapong, Thaisiri Watewai, Sung Kyu Lim	Statistical Bellman-Ford algorithm with an application to retiming.	ASP-DAC	2006	DBLP DOI BibTeX RDF
11	Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula	A framework for statistical timing analysis using non-linear delay and slew models.	ICCAD	2006	DBLP DOI BibTeX RDF
11	Domenik Helms, Günter Ehmen, Wolfgang Nebel	Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation.	ISLPED	2006	DBLP DOI BibTeX RDF	modeling, process variation, leakage, state dependence
11	Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, Mahmoud Shahram, Kishore Singhal	Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	measurement, process variations, extraction, VLSI interconnects
11	Young-Gu Kim, Sang-Hoon Lee, Dae-Han Kim, Jae-Woo Im, Sung-Eun Yu, Dae-Wook Kim, Young-Kwan Park, Jeong-Taek Kong	Sensing Margin Analysis of MLC Flash Memories Using a Novel Unified Statistical Model.	ISQED	2006	DBLP DOI BibTeX RDF
11	Aseem Agarwal, Kaviraj Chopra, David T. Blaauw	Statistical Timing Based Optimization using Gate Sizing.	DATE	2005	DBLP DOI BibTeX RDF
11	David T. Blaauw, Anirudh Devgan, Farid N. Najm	Leakage power: trends, analysis and avoidance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
11	Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy 0001	A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
11	Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy 0001	A Feasibility Study of Subthreshold SRAM Across Technology Generations.	ICCD	2005	DBLP DOI BibTeX RDF