Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
91 | Weisheng Zhao, Guillaume Agnus, Vincent Derycke, Arianna Filoramo, Christian Gamrat, Jean-Philippe Bourgoin |
Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings, pp. 105-110, 2009, Springer, 978-3-642-04849-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Hybrid Nano/CMOS circuits, OG-CNTFET, Verilog-A, Carbon Nanotube, Functional Modelling |
74 | Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos |
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 303-308, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dual oxide technology, nano-cmos, performance aware design, vco, process variation, parasitics, power aware design |
60 | Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan |
A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 323-328, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
nano-CMOS, power, leakage, SRAM, static noise margin |
58 | Liangxiu Han, Asen Asenov, Dave Berry, Campbell Millar, Gareth Roy, Scott Roy, Richard O. Sinnott, Gordon Stewart 0002 |
Towards a Grid-Enabled Simulation Framework for Nano-CMOS Electronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
eScience ![In: Third International Conference on e-Science and Grid Computing, e-Science 2007, 10-13 December 2007, Bangalore, India, pp. 305-311, 2007, IEEE Computer Society, 0-7695-3064-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
48 | Wei Zhang 0012, Niraj K. Jha, Li Shang |
A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 5(3), pp. 13:1-13:31, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
design optimization flow, logic folding, Dynamic reconfiguration, NATURE |
47 | Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos |
A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 47-52, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed |
47 | YuHua Cheng |
A glance of technology efforts for design-for-manufacturing in nano-scale CMOS processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 51(6), pp. 807-818, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
nano-CMOS IC design, IC design methodology, CMOS design technology platform, design-for-manufacturing (DFM), design-for-yield |
43 | Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk |
High-Quality Circuit Synthesis for Modern Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 168-173, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
nano CMOS technologies, high-speed and low-power circuits, information-driven synthesis, multi-objective optimization, circuit synthesis |
39 | Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos |
Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 172-178, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Wei Zhang 0012, Li Shang, Niraj K. Jha |
NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 300-305, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos, Bharat Joshi |
A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 673-679, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra |
A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 47-54, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Saraju P. Mohanty |
Unified Challenges in Nano-CMOS High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 531, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Ajith Amerasekera |
Concurrent Optimization of Technology and Design for Nano CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 27, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Alexander Flocke, Tobias G. Noll |
Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 33rd European Solid-State Circuits Conference, ESSCIRC 2007, Munich, Germany, 11-13 September 2007, pp. 328-331, 2007, IEEE, 978-1-4244-1125-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Kazuya Shimizu, Masato Kaneta, HaiJun Lin, Haruo Kobayashi 0001, Nobukazu Takai, Masao Hotta |
A Time-to-Digital Converter with small circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 109-110, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Hei Wong, Shurong Dong, Zehua Chen |
Effects of non-fatal electrostatic discharge on the threshold voltage degradation in nano CMOS devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 65(2), 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Hamed Jooypa, Daryoosh Dideban, Hadi Heidari |
Statistical Strategies to Capture Correlation Between Overshooting Effect and Propagation Delay Time in Nano-CMOS Inverters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 65340-65345, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Xuebing Cao, Liyi Xiao, Linzhe Li, Jie Li 0030, Tianqi Wang |
Simulation of Proton Induced Single Event Upsets in Bulk Nano-CMOS SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: International Conference on IC Design and Technology, ICICDT 2019, Suzhou, China, June 17-19, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-1853-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Shibaji Banerjee, Jimson Mathew |
An Optimal Leakage-Aware Approach for Nano-CMOS Post-Physical-Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 13(4), pp. 642-648, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Vikram B. Suresh, Sandip Kundu |
Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(1), pp. 155-165, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Pengpeng Ren, Runsheng Wang, Ru Huang |
Layout dependent BTI and HCI degradation in nano CMOS technology: A new time-dependent LDE and impacts on circuit at end of life. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: International Conference on IC Design and Technology, ICICDT 2016, Ho Chi Minh, Vietnam, June 27-29, 2016, pp. 1-3, 2016, IEEE, 978-1-5090-0827-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Timothy Ganesan, I. Elamvazuthi, Pandian Vasant |
Multiobjective design optimization of a nano-CMOS voltage-controlled oscillator using game theoretic-differential evolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Soft Comput. ![In: Appl. Soft Comput. 32, pp. 293-299, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Sankit R. Kassa, Rajendra Kumar Nagaria |
A Review on Robust Low Power System Level Digital Circuit Design Approaches in Nano-CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCT ![In: Proceedings of the Sixth International Conference on Computer and Communication Technology 2015, ICCCT 2015, Allahabad, India, September 25-27, 2015, pp. 371-375, 2015, ACM, 978-1-4503-3552-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos |
Nano-CMOS thermal sensor design optimization for efficient temperature measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 47(2), pp. 195-203, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Mehdi Habibi, Hossein Pourmeidani |
A hierarchical defect repair approach for hybrid nano/CMOS memory reliability enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 54(2), pp. 475-484, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Haruo Kobayashi 0001, Hitoshi Aoki, Kentaroh Katoh, Congbing Li |
Analog/mixed-signal circuit design in nano CMOS era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 11(3), pp. 20142001, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Zheng Xie, Doug A. Edwards |
Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2013, pp. 984376:1-984376:22, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Mauro Olivieri, Antonio Mastrandrea |
A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2013, pp. 785281:1-785281:12, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos |
Geostatistical-inspired fast layout optimisation of a nano-CMOS thermal sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 7(5), pp. 253-262, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Dhruva Ghai, Saraju P. Mohanty, Garima Thakral |
Fast optimization of nano-CMOS voltage-controlled oscillator using polynomial regression and genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 44(8), pp. 631-641, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Andrew S. Cassidy, Julius Georgiou, Andreas G. Andreou |
Design of silicon brains in the nano-CMOS era: Spiking neurons, learning synapses and neural architecture optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Networks ![In: Neural Networks 45, pp. 4-26, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Vikram B. Suresh, Sandip Kundu |
Managing test coverage uncertainty due to thermal noise in nano-CMOS: A case-study on an SRAM array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 2013 IEEE 31st International Conference on Computer Design, ICCD 2013, Asheville, NC, USA, October 6-9, 2013, pp. 201-206, 2013, IEEE Computer Society, 978-1-4799-2987-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Dhruva Ghai, Saraju P. Mohanty, Garima Thakral |
Fast analog design optimization using regression-based modeling and genetic algorithm: A nano-CMOS VCO case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, USA, March 4-6, 2013, pp. 406-411, 2013, IEEE, 978-1-4673-4951-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Saraju P. Mohanty, Jawar Singh, Elias Kougianos, Dhiraj K. Pradhan |
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 45(1), pp. 33-45, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Houda Daoud, Samir Ben Salem, Sonia Zouari, Mourad Loulou |
Use of robust Predictive Method for nano-CMOS Process: Application to Basic Block Analog Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 21(7), 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Luo Sun, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty |
Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 8(3), pp. 270-282, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos |
Accurate Polynomial Metamodeling-Based Ultra-Fast Bee Colony Optimization of a Nano-CMOS Phase-Locked Loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 8(3), pp. 317-328, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos |
Geostatistical-Inspired Metamodeling and Optimization of Nano-CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, Amherst, MA, USA, August 19-21, 2012, pp. 326-331, 2012, IEEE Computer Society, 978-1-4673-2234-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov, Geng Zheng |
Stochastic Gradient Descent Optimization for Low Power Nano-CMOS Thermal Sensor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, Amherst, MA, USA, August 19-21, 2012, pp. 285-290, 2012, IEEE Computer Society, 978-1-4673-2234-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Teresa Serrano-Gotarredona, Bernabé Linares-Barranco |
Design of adaptive nano/CMOS neural architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012, pp. 949-952, 2012, IEEE, 978-1-4673-1261-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov, Javier Moreno Molina |
Polynomial-metamodel assisted fast power optimization of Nano-CMOS PLL components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceeding of the 2012 Forum on Specification and Design Languages, Vienna, Austria, September 18-20, 2012, pp. 233-238, 2012, IEEE, 978-1-4673-1240-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
18 | Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Geng Zheng |
Particle swarm optimization over non-polynomial metamodels for fast process variation resilient design of Nano-CMOS PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake City, UT, USA, May 3-4, 2012, pp. 255-258, 2012, ACM, 978-1-4503-1244-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Pedro Pereira 0001, M. Helena Fino, Fernando J. V. Coito, Mário Ventim-Neves |
Optimization-Based Design of Nano-CMOS LC-VCOs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DoCEIS ![In: Technological Innovation for Value Creation - Third IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems, DoCEIS 2012, Costa de Caparica, Portugal, February 27-29, 2012. Proceedings, pp. 453-464, 2012, Springer, 978-3-642-28254-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos |
Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL Design Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 25th International Conference on VLSI Design, Hyderabad, India, January 7-11, 2012, pp. 316-321, 2012, IEEE Computer Society, 978-1-4673-0438-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Cédric Hocquet, Dina Kamel, Francesco Regazzoni 0001, Jean-Didier Legat, Denis Flandre, David Bol, François-Xavier Standaert |
Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Cryptogr. Eng. ![In: J. Cryptogr. Eng. 1(1), pp. 79-86, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski |
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 7(4), pp. 471-481, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Bhavana N. Joshi, Yogesh S. Mhaisagar, Ashok M. Mahajan |
Analysis of interconnect capacitance for sub nano CMOS technology using the low dielectric material. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 51(5), pp. 953-958, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra |
Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: International Symposium on Electronic System Design, ISED 2011, Kochi, Kerala, India, December 19-21, 2011, pp. 6-11, 2011, IEEE Computer Society, 978-1-4577-1880-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Luo Sun, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty |
Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: International Symposium on Electronic System Design, ISED 2011, Kochi, Kerala, India, December 19-21, 2011, pp. 194-199, 2011, IEEE Computer Society, 978-1-4577-1880-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Michal Bryk, Lech Józwiak, Wieslaw Kuzmicz |
Rapid and Accurate Leakage Power Estimation for Nano-CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland, pp. 685-692, 2011, IEEE Computer Society, 978-1-4577-1048-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Feng Hong, Binjie Cheng, Scott Roy, David R. S. Cumming |
An analytical mismatch model of nano-CMOS device under impact of intrinsic device variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, pp. 2257-2260, 2011, IEEE, 978-1-4244-9473-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos, Mahesh Poolakkaparambil |
Towards robust nano-CMOS sense amplifier design: a dual-threshold versus dual-oxide perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011, pp. 145-150, 2011, ACM, 978-1-4503-0667-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos |
Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011, Santa Clara, California, USA, 14-16 March 2011, pp. 405-410, 2011, IEEE, 978-1-61284-914-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Mouna Karmani, Ka Lok Man, Chiraz Khedhiri, Belgacem Hamdi |
Design for testability in nano-CMOS analog integrated circuits using a new design analog checker. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2011, Jeju, South Korea, November 17-18, 2011, pp. 317-320, 2011, IEEE, 978-1-4577-0709-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski |
Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2011: 24th International Conference on VLSI Design, IIT Madras, Chennai, India, 2-7 January 2011, pp. 304-309, 2011, IEEE Computer Society, 978-0-7695-4348-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh |
Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(4), pp. 675-679, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Wei Zhang 0012, Niraj K. Jha, Li Shang |
Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 6(3), pp. 10:1-10:32, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Saraju P. Mohanty, Dhiraj K. Pradhan |
ULS: A dual-Vth/high-kappa nano-CMOS universal level shifter for system-level power management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 6(2), pp. 8:1-8:26, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Garima Thakral, Saraju P. Mohanty, Dhiraj K. Pradhan, Elias Kougianos |
DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 6(3), pp. 390-400, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Zheng Xie, Doug A. Edwards |
Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010, pp. 161-166, 2010, IEEE Computer Society, 978-1-4244-6612-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs |
Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers, pp. 190-199, 2010, Springer, 978-3-642-17751-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Dina Kamel, Cédric Hocquet, François-Xavier Standaert, Denis Flandre, David Bol |
Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 36th European Solid-State Circuits Conference, ESSCIRC 2010, Sevilla, Spain, September 13-17, 2010, pp. 518-521, 2010, IEEE, 978-1-4244-6662-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Touqeer Azam, David R. S. Dimming |
Robust low power design in nano-CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 2466-2469, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan |
P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 11th International Symposium on Quality of Electronic Design (ISQED 2010), 22-24 March 2010, San Jose, CA, USA, pp. 176-183, 2010, IEEE, 978-1-4244-6455-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos |
A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 99-104, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan |
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 45-50, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Nanoscale CMOS, SRAM, Power Dissipation, Static Noise Margin |
18 | Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos |
Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 17(9), pp. 1339-1342, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Wei Zhang 0012, Niraj K. Jha, Li Shang |
Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 5(4), pp. 17:1-17:27, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha |
A hybrid nano-CMOS architecture for defect and fault tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 5(3), pp. 14:1-14:26, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
nanotechnology, Defect tolerance, nanowires |
18 | Wei Zhang 0012, Niraj K. Jha, Li Shang |
A hybrid nano/CMOS dynamically reconfigurable system - Part I: Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 5(4), pp. 16:1-16:30, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Elias Kougianos, Saraju P. Mohanty |
Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 40(1), pp. 95-103, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Ismail Saad, Michael L. P. Tan, Aaron C. E. Lee, Razali Ismail, Vijay K. Arora |
Scattering-limited and ballistic transport in a nano-CMOS circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 40(3), pp. 581-583, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Catherine Dezan, Ciprian Teodorov, Loïc Lagadec, Michael Leuchtenburg, Teng Wang, Pritish Narayanan, Csaba Andras Moritz |
Towards a framework for designing applications onto hybrid nano/CMOS fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 40(4-5), pp. 656-664, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Yu Cao 0001, Jim Tschanz, Pradip Bose |
Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 26(6), pp. 6-7, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Kazuya Masu, Noboru Ishihara, Noriaki Nakayama, Takashi Sato, Shuhei Amakawa |
Physical design challenges to nano-CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 6(11), pp. 703-720, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Sergio Bampi, Ricardo Reis 0001 |
Challenges and Emerging Technologies for System Integration beyond the End of the Roadmap of Nano-CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: VLSI-SoC: Technologies for Systems Integration - 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianópolis, Brazil, October 12-14, 2009, Revised Selected Papers, pp. 21-33, 2009, Springer, 978-3-642-23119-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Alain J. Martin |
Asynchronous logic for high variability nano-CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, Yasmine Hammamet, Tunisia, 13-19 December, 2009, pp. 69-72, 2009, IEEE, 978-1-4244-5090-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Saket Srivastava, Aissa Melouki, Bashir M. Al-Hashimi |
Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: 2009 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2009, San Francisco, CA, USA, July 30-31, 2009, pp. 43-46, 2009, IEEE Computer Society, 978-1-4244-4957-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Saraju P. Mohanty, Bijaya K. Panigrahi |
ILP based Leakage Optimization during Nano-CMOS RTL Synthesis: A DOXCMOS Versus DTCMOS Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NaBIC ![In: World Congress on Nature & Biologically Inspired Computing, NaBIC 2009, 9-11 December 2009, Coimbatore, India, pp. 1367-1372, 2009, IEEE, 978-1-4244-5053-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | B. P. Harish, Navakanta Bhat, Mahesh B. Patil |
Bridging Technology-CAD and Design-CAD for Variability Aware Nano-CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 2309-2312, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Seung-Hyun Song, Jae-Chul Kim, Sung-Woo Jung, Yoon-Ha Jeong |
Junction Depth Dependence of the Gate Induced Drain Leakage in Shallow Junction Source/Drain-Extension Nano-CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 91-C(5), pp. 761-766, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Ranjith Kumar, Volkan Kursun |
Temperature-Adaptive Energy Reduction Techniques for Nano-CMOS Circuits Displaying Reversed temperature Dependence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 17(3), pp. 423-438, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Aswin Sreedhar, Alodeep Sanyal, Sandip Kundu |
On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 616-621, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan |
A nano-CMOS process variation induced read failure tolerant SRAM cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3334-3337, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty |
Failure analysis for ultra low power nano-CMOS SRAM under process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 251-254, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha |
Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 435-440, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Fang-Shi Lai, Chia-Fu Lee |
On-Chip Voltage Down Converter to Improve SRAM Read/Write Margin and Static Power for Sub-Nano CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 42(9), pp. 2061-2070, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Wei Zhao, Yu Cao 0001 |
Predictive technology model for nano-CMOS design exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 3(1), pp. 1, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
early design exploration, process variations, predictive modeling, Technology scaling, FinFET |
18 | Saraju P. Mohanty, Elias Kougianos |
Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 577-582, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Yu Cao 0001, Wei Zhao |
Predictive Technology Model for Nano-CMOS Design Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Nano-Net ![In: 1st International ICST Conference on Nano-Networks, Nano-Net 2006, Lausanne, Switzerland, September 14-16, 2006, pp. 1-5, 2006, IEEE, 1-4244-0391-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Jordan Lai |
SRAM Design Techniques for Sub-nano CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Chung-Yu Wu, Jen-Chieh Wang |
Optimal structure of interconnection lines for GHz giga-scale nano-CMOS system-on-chip design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004, Tel Aviv, Israel, December 13-15, 2004, pp. 191-194, 2004, IEEE, 0-7803-8715-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Leland Chang, Yang-Kyu Choi, Daewon Ha, Pushkar Ranade, Shiying Xiong, Jeffrey Bokor, Chenming Hu, Tsu-Jae King 0001 |
Extremely scaled silicon nano-CMOS devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 91(11), pp. 1860-1873, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Wei Zhang 0012, Niraj K. Jha, Li Shang |
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 711-716, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
NRAM, logic folding, run-time reconfiguration |
13 | Omer Khan, Sandip Kundu |
A model to exploit power-performance efficiency in superscalar processors via structure resizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 215-220, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
modeling, power |
13 | Suman Kalyan Mandal, Ron Denton, Saraju P. Mohanty, Rabi N. Mahapatra |
Low power nanoscale buffer management for network on chip routers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 245-250, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
nanoscale technology noc, soc, noc, router, dynamic power management |
13 | Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 42-51, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Lech Józwiak, Szymon Bieganski |
Technology Library Modelling for Information-driven Circuit Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 480-489, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Optimal sleep transistor synthesis under timing and area constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 177-182, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
row-based, clustering, leakage power, power-gating, standard cell, sleep transistor |