Search results for "nano-cmos"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
91	Weisheng Zhao, Guillaume Agnus, Vincent Derycke, Arianna Filoramo, Christian Gamrat, Jean-Philippe Bourgoin	Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design.	NanoNet	2009	DBLP DOI BibTeX RDF	Hybrid Nano/CMOS circuits, OG-CNTFET, Verilog-A, Carbon Nanotube, Functional Modelling
74	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dual oxide technology, nano-cmos, performance aware design, vco, process variation, parasitics, power aware design
60	Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan	A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	nano-CMOS, power, leakage, SRAM, static noise margin
58	Liangxiu Han, Asen Asenov, Dave Berry, Campbell Millar, Gareth Roy, Scott Roy, Richard O. Sinnott, Gordon Stewart 0002	Towards a Grid-Enabled Simulation Framework for Nano-CMOS Electronics.	eScience	2007	DBLP DOI BibTeX RDF
48	Wei Zhang 0012, Niraj K. Jha, Li Shang	A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	design optimization flow, logic folding, Dynamic reconfiguration, NATURE
47	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed
47	YuHua Cheng	A glance of technology efforts for design-for-manufacturing in nano-scale CMOS processes.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	nano-CMOS IC design, IC design methodology, CMOS design technology platform, design-for-manufacturing (DFM), design-for-yield
43	Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk	High-Quality Circuit Synthesis for Modern Technologies.	ISQED	2008	DBLP DOI BibTeX RDF	nano CMOS technologies, high-speed and low-power circuits, information-driven synthesis, multi-objective optimization, circuit synthesis
39	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments.	ISQED	2009	DBLP DOI BibTeX RDF
34	Wei Zhang 0012, Li Shang, Niraj K. Jha	NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture.	DAC	2007	DBLP DOI BibTeX RDF
32	Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos, Bharat Joshi	A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems.	ISQED	2009	DBLP DOI BibTeX RDF
31	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra	A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS.	ISQED	2009	DBLP DOI BibTeX RDF
31	Saraju P. Mohanty	Unified Challenges in Nano-CMOS High-Level Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
31	Ajith Amerasekera	Concurrent Optimization of Technology and Design for Nano CMOS.	VLSI Design	2007	DBLP DOI BibTeX RDF
29	Alexander Flocke, Tobias G. Noll	Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory.	ESSCIRC	2007	DBLP DOI BibTeX RDF
21	Kazuya Shimizu, Masato Kaneta, HaiJun Lin, Haruo Kobayashi 0001, Nobukazu Takai, Masao Hotta	A Time-to-Digital Converter with small circuitry.	ASP-DAC	2009	DBLP DOI BibTeX RDF
18	Hei Wong, Shurong Dong, Zehua Chen	Effects of non-fatal electrostatic discharge on the threshold voltage degradation in nano CMOS devices.	Sci. China Inf. Sci.	2022	DBLP DOI BibTeX RDF
18	Hamed Jooypa, Daryoosh Dideban, Hadi Heidari	Statistical Strategies to Capture Correlation Between Overshooting Effect and Propagation Delay Time in Nano-CMOS Inverters.	IEEE Access	2021	DBLP DOI BibTeX RDF
18	Xuebing Cao, Liyi Xiao, Linzhe Li, Jie Li 0030, Tianqi Wang	Simulation of Proton Induced Single Event Upsets in Bulk Nano-CMOS SRAMs.	ICICDT	2019	DBLP DOI BibTeX RDF
18	Shibaji Banerjee, Jimson Mathew	An Optimal Leakage-Aware Approach for Nano-CMOS Post-Physical-Optimization.	J. Low Power Electron.	2017	DBLP DOI BibTeX RDF
18	Vikram B. Suresh, Sandip Kundu	Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2016	DBLP DOI BibTeX RDF
18	Pengpeng Ren, Runsheng Wang, Ru Huang	Layout dependent BTI and HCI degradation in nano CMOS technology: A new time-dependent LDE and impacts on circuit at end of life.	ICICDT	2016	DBLP DOI BibTeX RDF
18	Timothy Ganesan, I. Elamvazuthi, Pandian Vasant	Multiobjective design optimization of a nano-CMOS voltage-controlled oscillator using game theoretic-differential evolution.	Appl. Soft Comput.	2015	DBLP DOI BibTeX RDF
18	Sankit R. Kassa, Rajendra Kumar Nagaria	A Review on Robust Low Power System Level Digital Circuit Design Approaches in Nano-CMOS Technologies.	ICCCT	2015	DBLP DOI BibTeX RDF
18	Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos	Nano-CMOS thermal sensor design optimization for efficient temperature measurement.	Integr.	2014	DBLP DOI BibTeX RDF
18	Mehdi Habibi, Hossein Pourmeidani	A hierarchical defect repair approach for hybrid nano/CMOS memory reliability enhancement.	Microelectron. Reliab.	2014	DBLP DOI BibTeX RDF
18	Haruo Kobayashi 0001, Hitoshi Aoki, Kentaroh Katoh, Congbing Li	Analog/mixed-signal circuit design in nano CMOS era.	IEICE Electron. Express	2014	DBLP DOI BibTeX RDF
18	Zheng Xie, Doug A. Edwards	Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits.	VLSI Design	2013	DBLP DOI BibTeX RDF
18	Mauro Olivieri, Antonio Mastrandrea	A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures.	VLSI Design	2013	DBLP DOI BibTeX RDF
18	Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos	Geostatistical-inspired fast layout optimisation of a nano-CMOS thermal sensor.	IET Circuits Devices Syst.	2013	DBLP DOI BibTeX RDF
18	Dhruva Ghai, Saraju P. Mohanty, Garima Thakral	Fast optimization of nano-CMOS voltage-controlled oscillator using polynomial regression and genetic algorithm.	Microelectron. J.	2013	DBLP DOI BibTeX RDF
18	Andrew S. Cassidy, Julius Georgiou, Andreas G. Andreou	Design of silicon brains in the nano-CMOS era: Spiking neurons, learning synapses and neural architecture optimization.	Neural Networks	2013	DBLP DOI BibTeX RDF
18	Vikram B. Suresh, Sandip Kundu	Managing test coverage uncertainty due to thermal noise in nano-CMOS: A case-study on an SRAM array.	ICCD	2013	DBLP DOI BibTeX RDF
18	Dhruva Ghai, Saraju P. Mohanty, Garima Thakral	Fast analog design optimization using regression-based modeling and genetic algorithm: A nano-CMOS VCO case study.	ISQED	2013	DBLP DOI BibTeX RDF
18	Saraju P. Mohanty, Jawar Singh, Elias Kougianos, Dhiraj K. Pradhan	Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM.	Integr.	2012	DBLP DOI BibTeX RDF
18	Houda Daoud, Samir Ben Salem, Sonia Zouari, Mourad Loulou	Use of robust Predictive Method for nano-CMOS Process: Application to Basic Block Analog Circuit Design.	J. Circuits Syst. Comput.	2012	DBLP DOI BibTeX RDF
18	Luo Sun, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits.	J. Low Power Electron.	2012	DBLP DOI BibTeX RDF
18	Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos	Accurate Polynomial Metamodeling-Based Ultra-Fast Bee Colony Optimization of a Nano-CMOS Phase-Locked Loop.	J. Low Power Electron.	2012	DBLP DOI BibTeX RDF
18	Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos	Geostatistical-Inspired Metamodeling and Optimization of Nano-CMOS Circuits.	ISVLSI	2012	DBLP DOI BibTeX RDF
18	Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov, Geng Zheng	Stochastic Gradient Descent Optimization for Low Power Nano-CMOS Thermal Sensor Design.	ISVLSI	2012	DBLP DOI BibTeX RDF
18	Teresa Serrano-Gotarredona, Bernabé Linares-Barranco	Design of adaptive nano/CMOS neural architectures.	ICECS	2012	DBLP DOI BibTeX RDF
18	Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov, Javier Moreno Molina	Polynomial-metamodel assisted fast power optimization of Nano-CMOS PLL components.	FDL	2012	DBLP BibTeX RDF
18	Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Geng Zheng	Particle swarm optimization over non-polynomial metamodels for fast process variation resilient design of Nano-CMOS PLL.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
18	Pedro Pereira 0001, M. Helena Fino, Fernando J. V. Coito, Mário Ventim-Neves	Optimization-Based Design of Nano-CMOS LC-VCOs.	DoCEIS	2012	DBLP DOI BibTeX RDF
18	Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos	Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL Design Optimization.	VLSI Design	2012	DBLP DOI BibTeX RDF
18	Cédric Hocquet, Dina Kamel, Francesco Regazzoni 0001, Jean-Didier Legat, Denis Flandre, David Bol, François-Xavier Standaert	Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags.	J. Cryptogr. Eng.	2011	DBLP DOI BibTeX RDF
18	Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski	A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization.	J. Low Power Electron.	2011	DBLP DOI BibTeX RDF
18	Bhavana N. Joshi, Yogesh S. Mhaisagar, Ashok M. Mahajan	Analysis of interconnect capacitance for sub nano CMOS technology using the low dielectric material.	Microelectron. Reliab.	2011	DBLP DOI BibTeX RDF
18	Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra	Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL.	ISED	2011	DBLP DOI BibTeX RDF
18	Luo Sun, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits.	ISED	2011	DBLP DOI BibTeX RDF
18	Michal Bryk, Lech Józwiak, Wieslaw Kuzmicz	Rapid and Accurate Leakage Power Estimation for Nano-CMOS Circuits.	DSD	2011	DBLP DOI BibTeX RDF
18	Feng Hong, Binjie Cheng, Scott Roy, David R. S. Cumming	An analytical mismatch model of nano-CMOS device under impact of intrinsic device variability.	ISCAS	2011	DBLP DOI BibTeX RDF
18	Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos, Mahesh Poolakkaparambil	Towards robust nano-CMOS sense amplifier design: a dual-threshold versus dual-oxide perspective.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
18	Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos	Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling.	ISQED	2011	DBLP DOI BibTeX RDF
18	Mouna Karmani, Ka Lok Man, Chiraz Khedhiri, Belgacem Hamdi	Design for testability in nano-CMOS analog integrated circuits using a new design analog checker.	ISOCC	2011	DBLP DOI BibTeX RDF
18	Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski	Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization.	VLSI Design	2011	DBLP DOI BibTeX RDF
18	Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh	Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
18	Wei Zhang 0012, Niraj K. Jha, Li Shang	Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture.	ACM J. Emerg. Technol. Comput. Syst.	2010	DBLP DOI BibTeX RDF
18	Saraju P. Mohanty, Dhiraj K. Pradhan	ULS: A dual-Vth/high-kappa nano-CMOS universal level shifter for system-level power management.	ACM J. Emerg. Technol. Comput. Syst.	2010	DBLP DOI BibTeX RDF
18	Garima Thakral, Saraju P. Mohanty, Dhiraj K. Pradhan, Elias Kougianos	DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM.	J. Low Power Electron.	2010	DBLP DOI BibTeX RDF
18	Zheng Xie, Doug A. Edwards	Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuits.	DDECS	2010	DBLP DOI BibTeX RDF
18	Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs	Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations.	PATMOS	2010	DBLP DOI BibTeX RDF
18	Dina Kamel, Cédric Hocquet, François-Xavier Standaert, Denis Flandre, David Bol	Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS circuits.	ESSCIRC	2010	DBLP DOI BibTeX RDF
18	Touqeer Azam, David R. S. Dimming	Robust low power design in nano-CMOS technologies.	ISCAS	2010	DBLP DOI BibTeX RDF
18	Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan	P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP.	ISQED	2010	DBLP DOI BibTeX RDF
18	Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos	A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO.	VLSI Design	2010	DBLP DOI BibTeX RDF
18	Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan	A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM.	VLSI Design	2010	DBLP DOI BibTeX RDF	Nanoscale CMOS, SRAM, Power Dissipation, Static Noise Margin
18	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
18	Wei Zhang 0012, Niraj K. Jha, Li Shang	Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF
18	Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha	A hybrid nano-CMOS architecture for defect and fault tolerance.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	nanotechnology, Defect tolerance, nanowires
18	Wei Zhang 0012, Niraj K. Jha, Li Shang	A hybrid nano/CMOS dynamically reconfigurable system - Part I: Architecture.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF
18	Elias Kougianos, Saraju P. Mohanty	Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO.	Microelectron. J.	2009	DBLP DOI BibTeX RDF
18	Ismail Saad, Michael L. P. Tan, Aaron C. E. Lee, Razali Ismail, Vijay K. Arora	Scattering-limited and ballistic transport in a nano-CMOS circuit.	Microelectron. J.	2009	DBLP DOI BibTeX RDF
18	Catherine Dezan, Ciprian Teodorov, Loïc Lagadec, Michael Leuchtenburg, Teng Wang, Pritish Narayanan, Csaba Andras Moritz	Towards a framework for designing applications onto hybrid nano/CMOS fabrics.	Microelectron. J.	2009	DBLP DOI BibTeX RDF
18	Yu Cao 0001, Jim Tschanz, Pradip Bose	Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design.	IEEE Des. Test Comput.	2009	DBLP DOI BibTeX RDF
18	Kazuya Masu, Noboru Ishihara, Noriaki Nakayama, Takashi Sato, Shuhei Amakawa	Physical design challenges to nano-CMOS circuits.	IEICE Electron. Express	2009	DBLP DOI BibTeX RDF
18	Sergio Bampi, Ricardo Reis 0001	Challenges and Emerging Technologies for System Integration beyond the End of the Roadmap of Nano-CMOS.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
18	Alain J. Martin	Asynchronous logic for high variability nano-CMOS.	ICECS	2009	DBLP DOI BibTeX RDF
18	Saket Srivastava, Aissa Melouki, Bashir M. Al-Hashimi	Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism.	NANOARCH	2009	DBLP DOI BibTeX RDF
18	Saraju P. Mohanty, Bijaya K. Panigrahi	ILP based Leakage Optimization during Nano-CMOS RTL Synthesis: A DOXCMOS Versus DTCMOS Perspective.	NaBIC	2009	DBLP DOI BibTeX RDF
18	B. P. Harish, Navakanta Bhat, Mahesh B. Patil	Bridging Technology-CAD and Design-CAD for Variability Aware Nano-CMOS Circuits.	ISCAS	2009	DBLP DOI BibTeX RDF
18	Seung-Hyun Song, Jae-Chul Kim, Sung-Woo Jung, Yoon-Ha Jeong	Junction Depth Dependence of the Gate Induced Drain Leakage in Shallow Junction Source/Drain-Extension Nano-CMOS.	IEICE Trans. Electron.	2008	DBLP DOI BibTeX RDF
18	Ranjith Kumar, Volkan Kursun	Temperature-Adaptive Energy Reduction Techniques for Nano-CMOS Circuits Displaying Reversed temperature Dependence.	J. Circuits Syst. Comput.	2008	DBLP DOI BibTeX RDF
18	Aswin Sreedhar, Alodeep Sanyal, Sandip Kundu	On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits.	DATE	2008	DBLP DOI BibTeX RDF
18	Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan	A nano-CMOS process variation induced read failure tolerant SRAM cell.	ISCAS	2008	DBLP DOI BibTeX RDF
18	Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	Failure analysis for ultra low power nano-CMOS SRAM under process variations.	SoCC	2008	DBLP DOI BibTeX RDF
18	Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha	Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture.	VLSI Design	2008	DBLP DOI BibTeX RDF
18	Fang-Shi Lai, Chia-Fu Lee	On-Chip Voltage Down Converter to Improve SRAM Read/Write Margin and Static Power for Sub-Nano CMOS Technology.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
18	Wei Zhao, Yu Cao 0001	Predictive technology model for nano-CMOS design exploration.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	early design exploration, process variations, predictive modeling, Technology scaling, FinFET
18	Saraju P. Mohanty, Elias Kougianos	Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis.	VLSI Design	2007	DBLP DOI BibTeX RDF
18	Yu Cao 0001, Wei Zhao	Predictive Technology Model for Nano-CMOS Design Exploration.	Nano-Net	2006	DBLP DOI BibTeX RDF
18	Jordan Lai	SRAM Design Techniques for Sub-nano CMOS Technology.	MTDT	2006	DBLP DOI BibTeX RDF
18	Chung-Yu Wu, Jen-Chieh Wang	Optimal structure of interconnection lines for GHz giga-scale nano-CMOS system-on-chip design.	ICECS	2004	DBLP DOI BibTeX RDF
18	Leland Chang, Yang-Kyu Choi, Daewon Ha, Pushkar Ranade, Shiying Xiong, Jeffrey Bokor, Chenming Hu, Tsu-Jae King 0001	Extremely scaled silicon nano-CMOS devices.	Proc. IEEE	2003	DBLP DOI BibTeX RDF
17	Wei Zhang 0012, Niraj K. Jha, Li Shang	NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture.	DAC	2006	DBLP DOI BibTeX RDF	NRAM, logic folding, run-time reconfiguration
13	Omer Khan, Sandip Kundu	A model to exploit power-performance efficiency in superscalar processors via structure resizing.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	modeling, power
13	Suman Kalyan Mandal, Ron Denton, Saraju P. Mohanty, Rabi N. Mahapatra	Low power nanoscale buffer management for network on chip routers.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	nanoscale technology noc, soc, noc, router, dynamic power management
13	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.	PATMOS	2008	DBLP DOI BibTeX RDF
13	Lech Józwiak, Szymon Bieganski	Technology Library Modelling for Information-driven Circuit Synthesis.	DSD	2008	DBLP DOI BibTeX RDF
13	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Optimal sleep transistor synthesis under timing and area constraints.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor