Search results for "scan-test"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
85	Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
76	Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara	Improving test effectiveness of scan-based BIST by scan chain partitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
71	Diogo José Costa Alves, Edna Barros	A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns.	SBCCI	2009	DBLP DOI BibTeX RDF	LBIST, compressed test patterns, test, SoC, self-test
69	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001	Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms.	VLSI Design	2007	DBLP DOI BibTeX RDF
65	Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara	Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
63	Markus Seuring	Combining Scan Test and Built-in Self Test.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	MBIST, BIST, scan test, production test, stress test
62	Dong Xiang, Ming-Jing Chen, Kaiwei Li, Yu-Liang Wu	Scan-Based BIST Using an Improved Scan Forest Architecture.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
62	Irith Pomeranz, Sudhakar M. Reddy	Improved n-Detection Test Sequences Under Transparent Scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
57	Michael Cogswell, Shazia Mardhani, Kevin Melocco, Hina Arora	A Structured Graphical Tool for Analyzing Boundary Scan Violations.	ITC	2002	DBLP DOI BibTeX RDF
57	Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi	Scan Test of IP Cores in an ATE Environment.	DELTA	2004	DBLP DOI BibTeX RDF
56	Sverre Wichlund, Frank Berntsen, Einar J. Aas	Scan Test Response Compaction Combined with Diagnosis Capabilities.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Scan compression, Diagnosis, ATPG, Yield, Design for test, ATE
56	Nuno Cardoso, Carlos Beltrán Almeida, José Carlos da Silva 0001	A System Level Boundary Scan Controller Board for VME Applications.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	IEEE 1149.1 boundary scan test, board level test and system level test, ATPG
51	Sverre Wichlund, Frank Berntsen, Einar J. Aas	Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor.	DFT	2006	DBLP DOI BibTeX RDF
51	Chris Feige, Jan Ten Pierick, Clemens Wouters, Ronald J. W. T. Tangelder, Hans G. Kerkhoff	Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	bus-transfer, core reuse, test protocol, TIC, TTM, vector transfer, design-for-testability, ATPG, scan-test, AMBA
49	Masayuki Tsukisaka, Masashi Imai, Takashi Nanya	Asynchronous Scan-Latch controller for Low Area Overhead DFT.	ICCD	2004	DBLP DOI BibTeX RDF
49	Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic	Securing Designs against Scan-Based Side-Channel Attacks.	IEEE Trans. Dependable Secur. Comput.	2007	DBLP DOI BibTeX RDF	Security and Privacy Protection, Scan-Based Design, Secure Design, Reliability and Testing
49	Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey	Optimized reseeding by seed ordering and encoding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
47	Ching-Hwa Cheng	Design Scan Test Strategy for Single Phase Dynamic Circuits.	DFT	2003	DBLP DOI BibTeX RDF
46	Frans Jong, José S. Matos, José M. Ferreira	Boundary scan test, test methodology, and fault modeling.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	BST-net, PCB testing, diagnosis, fault modeling, test-pattern generation, boundary scan test
45	Subhrajit Bhattacharya, Sujit Dey, Bhaskar Sengupta	An RTL methodology to enable low overhead combinational testing.	ED&TC	1997	DBLP DOI BibTeX RDF
45	Irith Pomeranz	N-detection under transparent-scan.	DAC	2005	DBLP DOI BibTeX RDF	test generation, scan design, n-detection test sets
44	Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler	Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
44	Frank Poehl, Jan Rzeha, Matthias Beck, Michael Gössel, Ralf Arnold, Peter Ossimitz	On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture.	ETS	2006	DBLP DOI BibTeX RDF
42	Joep Aerts, Erik Jan Marinissen	Scan chain design for test time reduction in core-based ICs.	ITC	1998	DBLP DOI BibTeX RDF
40	Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar	A critical-path-aware partial gating approach for test power reduction.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	partial gating, scan cell gating, Low-power testing, scan testing
40	Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar	Partial Gating Optimization for Power Reduction During Test Application.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
40	Dong Hyun Baik, Kewal K. Saluja	State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
40	Ad J. van de Goor, Said Hamdioui, Zaid Al-Ars	The Effectiveness of the Scan Test and Its New Variants.	MTDT	2004	DBLP DOI BibTeX RDF
39	Hiroyuki Yotsuyanagi, Masayuki Yamamoto, Masaki Hashizume	Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops.	IEICE Trans. Inf. Syst.	2010	DBLP DOI BibTeX RDF
39	Dong Xiang, Shan Gu, Jia-Guang Sun, Yu-Liang Wu	A cost-effective scan architecture for scan testing with non-scan test power and test application cost.	DAC	2003	DBLP DOI BibTeX RDF
39	Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay	Flip-flop chaining architecture for power-efficient scan during test application.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
39	Jing Wang, Shengbing Zhang, Zhang Meng	Testing of a 32-bit High Performance Embedded Microprocessor.	SIES	2007	DBLP DOI BibTeX RDF
38	Josef Schmid, Joachim Knäblein	Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs.	VTS	1999	DBLP DOI BibTeX RDF
37	Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee	An SOC Test Integration Platform and Its Industrial Realization.	ITC	2004	DBLP DOI BibTeX RDF
36	Jacob Savir	Module level weighted random patterns.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	module level self-test architecture, pseudorandom pattern generator, universal weighting generator, scan latch, near-optimal weight, signal pins, weight control function, self-test time, logic testing, probability, integrated circuit testing, automatic testing, multivalued logic circuits, boundary scan testing, scan test, weighted random patterns, multiple input signature register
35	Ho Fai Ko, Nicola Nicolici	Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
34	Hyungil Woo, Seokjun Jang, Sungho Kang 0001	A Secure Scan Architecture Protecting Scan Test and Scan Dump Using Skew-Based Lock and Key.	IEEE Access	2021	DBLP DOI BibTeX RDF
33	Shih Ping Lin 0001, Chung-Len Lee 0001, Jwu E. Chen	Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
33	Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee 0001	Embedded deterministic test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
32	Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier	Enhanced Reduced Pin-Count Test for Full-Scan Design.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	reduced pin-count test, core test, design for testability, ATE, boundary-scan test, scan test
32	Praveen Parvathala	High Level Test Generation / SW based Embedded Test.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
32	Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic	Securing Scan Design Using Lock and Key Technique.	DFT	2005	DBLP DOI BibTeX RDF
32	Tian-Wei Huang, Pei-Si Wu, Ren-Chieh Liu, Jeng-Han Tsai, Huei Wang, Tzi-Dar Chiueh	Boundary Scan for 5-GHz RF Pins Using LC Isolation Networks.	VTS	2004	DBLP DOI BibTeX RDF
32	Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai	VirtualScan: A New Compressed Scan Technology for Test Cost Reduction.	ITC	2004	DBLP DOI BibTeX RDF
32	Ching-Hwa Cheng	Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits.	DFT	2002	DBLP DOI BibTeX RDF
31	Christian Galke, René Kothe, Sabine Schultke, K. Winkler, Jeanette Honko, Heinrich Theodor Vierhaus	Embedded Scan Test with Diagnostic Features for Self-Testing SoCs.	IOLTS	2006	DBLP DOI BibTeX RDF
31	O. A. Petlin, Stephen B. Furber	Scan testing of micropipelines.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines
31	Chao-Wen Tzeng, Shi-Yu Huang	UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	multicasting, broadcasting, DFT, test compression, scan test
31	Octavian Petre, Hans G. Kerkhoff	Scan Test Strategy for Asynchronous-Synchronous Interfaces.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	globally asynchronous locally synchronous (GALS), asynchronous synchronous interface, synchronizers, scan test
30	Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng	A Test Synthesis Approach to Reducing BALLAST DFT Overhead.	DAC	1997	DBLP DOI BibTeX RDF
30	Tsuyoshi Shinogi, Hiroyuki Yamada, Terumine Hayashi, Shinji Tsuruoka, Tomohiro Yoshikawa	A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
29	Frank te Beest, Ad M. G. Peeters	A Multiplexor Based Test Method for Self-Timed Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
29	Nitin Parimi, Xiaoling Sun	Toggle-Masking for Test-per-Scan VLSI Circuits.	DFT	2004	DBLP DOI BibTeX RDF
26	Scott Davidson 0001	What's the problem?	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	full-scan test, design for testability, delay test, defects, IC
25	Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu	An Improved Soft-Error Rate Measurement Technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
25	Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz	On test data volume reduction for multiple scan chain designs.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Decompressor, Don't care identification, Encoding techniques, Design for testability, Test data compression
25	Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz	On Test Data Volume Reduction for Multiple Scan Chain Designs.	VTS	2002	DBLP DOI BibTeX RDF
25	Irith Pomeranz, Sudhakar M. Reddy	Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
25	Bernd Könemann, Carl Barnhart, Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, Donald L. Wheater	A SmartBIST Variant with Guaranteed Encoding.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
25	Hsiang-Huang Wu, Jih-Nung Lee, Ming-Cheng Chiang, Po-Wei Liu, Chi-Feng Wu	A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design.	ITC	2009	DBLP DOI BibTeX RDF
24	Sungyoul Seo, Keewon Cho, Young-Woo Lee, Sungho Kang 0001	A Statistic-Based Scan Chain Reordering for Energy-Quality Scalable Scan Test.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2018	DBLP DOI BibTeX RDF
24	Mahshid Mojtabavi Naeini, Sreedharan Baskara Dass, Chia Yee Ooi, Tomokazu Yoneda, Michiko Inoue	An integrated DFT solution for power reduction in scan test applications by low power gating scan cell.	Integr.	2017	DBLP DOI BibTeX RDF
24	Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh	A high performance scan flip-flop design for serial and mixed mode scan test.	IOLTS	2016	DBLP DOI BibTeX RDF
24	Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi 0001	Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test.	J. Low Power Electron.	2011	DBLP DOI BibTeX RDF
24	Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara	F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG.	ETS	2011	DBLP DOI BibTeX RDF	automatic test pattern generation, scan-based test, high-level testing
24	Dong Xiang, Mingjing Chen, Jia-Guang Sun	Scan BIST with biased scan test signals.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	random testability, test signal, biased random testing, scan-based BIST
24	Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Erik Chmelar, M. Grinchuk, Arun Gunda	Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
24	V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti 0001	PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test.	ITC	2007	DBLP DOI BibTeX RDF
24	Nabil Badereddine, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault	Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
24	Kenneth P. Parker	Defect Coverage of Boundary-Scan Tests: What does it mean when a Boundary-Scan test passes?	ITC	2003	DBLP DOI BibTeX RDF
24	Anthony P. Ambler	The application and use of boundary scan: Bleeker, H, van den Eijnden, P and de Jong, FBoundary-scan test - a practical approach Kluwer Academic (1992) ISBN 0 7923 9296 5, £50.75, pp 222.	Microprocess. Microsystems	1993	DBLP DOI BibTeX RDF
23	Thomas A. Ziaja, Earl E. Swartzlander Jr.	Boundary scan in board manufacturing.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Board and system test, boundary scan description language, design-for-test, boundary scan
23	Roberto Bevacqua, Luca Guerrazzi, Fabrizio Ferrandi, Franco Fummi	Implicit Test Sequences Compaction for Decreasing Test Application Cos.	ICCD	1996	DBLP DOI BibTeX RDF
23	Frans P. M. Beenker, Barry J. Dekker, Richard Stans, Max van der Star	Implementing Macro Test in Silicon Compiler Design.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
22	Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara	New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
22	Mehrdad Nourani, Mohammad H. Tehranipour	RL-huffman encoding for test compression and power reduction in scan applications.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Huffman encoding, scan applications, scan-in test power, test pattern compression, power reduction, switching activities, test compression, Compression ratio, run-length encoding, decompression
20	Edward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov	Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture.	VLSI Design	2007	DBLP DOI BibTeX RDF
20	Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone	Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits.	DFT	2000	DBLP DOI BibTeX RDF
20	Stephen Pateras	Security vs. Test Quality: Fully Embedded Test Approaches Are the Key to Having Both.	ITC	2004	DBLP DOI BibTeX RDF
20	Janusz Rajski, Jerzy Tyszer	Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs.	ICCD	2003	DBLP DOI BibTeX RDF
20	Mohsen Nahvi, André Ivanov	An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC Cores.	VTS	2003	DBLP DOI BibTeX RDF
20	Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee 0001, Janusz Rajski	Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions.	ITC	2003	DBLP DOI BibTeX RDF
20	Sanghyeon Baeg	Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
20	Peter Muhmenthaler	New on-Chip DFT and ATE Features for Efficient Embedded Memory Test.	MTDT	2006	DBLP DOI BibTeX RDF
20	Jung-Cheun Lien, Melvin A. Breuer	Test program synthesis for modules and chips having boundary scan.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	Board and system test, test controllers, test program synthesis, built-in self-test, design-for-test, boundary scan
20	Bo Ye	A Low Power Test Data Compression Scheme for Scan Test.	CECNet	2022	DBLP DOI BibTeX RDF
20	Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen	Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test.	ATS	2016	DBLP DOI BibTeX RDF
20	Shengjian Chen, Lei Xu	A boundary-scan test bus controller design for mixed-signal test.	WCNIS	2010	DBLP DOI BibTeX RDF
20	Masashi Ishikawa, Hiroyuki Yotsuyanagi, Masaki Hashizume	Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
20	Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang	AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects.	DFT	2010	DBLP DOI BibTeX RDF
20	Ozgur Sinanoglu	Low Cost Scan Test by Test Correlation Utilization.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	test correlation, scan architecture design, test data compression, scan-based testing
20	Ozgur Sinanoglu, Alex Orailoglu	Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
20	Takahisa Hiraide, Kwame Osei Boateng, Hideaki Konishi, Koichi Itaya, Michiaki Emori, Hitoshi Yamanaka, Takashi Mochiyama	BIST-Aided Scan Test - A New Method for Test Cost Reduction.	VTS	2003	DBLP DOI BibTeX RDF	ATPG, BIST, fault coverage, ATE, test cost reduction
20	Jamie Cullen	Scan test sequencing hardware for structural test.	ITC	2001	DBLP DOI BibTeX RDF
20	Math Muris, Alex S. Biewenga	Using Boundary Scan Test to Test Random Access Memory Clusters.	ITC	1993	DBLP DOI BibTeX RDF
18	Jaehoon Song, Piljae Min, Hyunbean Yi, Sungju Park	Design of Test Access Mechanism for AMBA-Based System-on-a-Chip.	VTS	2007	DBLP DOI BibTeX RDF
18	Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil	Compressing Functional Tests for Microprocessors.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
18	Chen-Huan Chiang, Paul J. Wheatley, Kenneth Y. Ho, Ken L. Cheung	Testing and Remote Field Update of Distributed Base Stations in a Wireless Network.	ITC	2004	DBLP DOI BibTeX RDF
18	Robert Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina	Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture.	ITC	2002	DBLP DOI BibTeX RDF
18	Zhaoliang Pan, Melvin A. Breuer	Estimating Error Rate in Defective Logic Using Signature Analysis.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Binning integrated circuits, effective yield, signature testing, error rate, error tolerance, yield loss