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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 54 occurrences of 38 keywords
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Results
Found 662 publication records. Showing 662 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
182 | Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan |
TSV stress aware timing analysis with applications to 3D-IC layout optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 803-806, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
mobility variation, timing analysis, stress, TSV, 3DIC |
138 | Sudeep Pasricha |
Exploring serial vertical interconnects for 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 581-586, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
serial interconnect, VLSI, networks on chip, 3D ICs |
106 | Vassilios Gerousis |
Physical design implementation for 3D IC: methodology and tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 57, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
3D IC stack, micro-bump, physical design tools, silicon interposer, methodology, tsv |
99 | Koichi Sato, J. K. Aggarwal |
Tracking soccer players using broadcast TV images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AVSS ![In: Advanced Video and Signal Based Surveillance, 2005 IEEE International Conference on Video and Signal Based Surveillance (AVSS'05), 15-16 September 2005, Como, Italy., pp. 546-551, 2005, IEEE Computer Society, 0-7803-9385-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
83 | Zongwu Tang |
Efficient design practices for thermal management of a TSV based 3D IC system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 59, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
thermal gradient, placement, design rule, TSV |
79 | Tae-Yong Kim 0002, Ulrich Neumann |
A Thin Shell Volume for Modeling Human Hair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CA ![In: Computer Animation 2000, CA 2000, Philadelphia, Pennsylvania, USA, May 3-5, 2000, pp. 104-111, 2000, IEEE Computer Society, 0-7695-0683-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
67 | Dae Hyun Kim 0004, Saibal Mukhopadhyay, Sung Kyu Lim |
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 85-92, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
wirelength distribution, rent's rule, 3d ic, tsv, interconnect prediction, through silicon via |
64 | Khaled Salah 0001 |
A TSV to TSV, A TSV to Metal interconnects, and A TSV to active device coupling capacitance: Analysis and recommendations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2015, Napoli, Italy, April 21-23, 2015, pp. 1-2, 2015, IEEE, 978-1-4799-1999-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
48 | Caleb Serafy, Ankur Srivastava 0001 |
TSV Replacement and Shield Insertion for TSV-TSV Coupling Reduction in 3-D Global Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4), pp. 554-562, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
48 | Khaled Salah 0001, Yehea I. Ismail |
Design of adiabatic TSV, SWCNT TSV, and Air-Gap Coaxial TSV. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 1953-1956, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
48 | Weng Hong Teh, Raymond Caramto, Jamal Qureshi, Sitaram Arkalgud, M. O'Brien, T. Gilday, Kou Maekawa, T. Saito, Kouichi Maruyama, Thenappan Chidambaram, Wei Wang 0003, David Marx, David Grant, Russ Dudley |
A route towards production-worthy 5 µm × 25 µm and 1 µm × 20 µm non-Bosch through-silicon-via (TSV) etch, TSV metrology, and TSV integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3DIC ![In: IEEE International Conference on 3D System Integration, 3DIC 2009, San Francisco, California, USA, 28-30 September 2009, pp. 1-5, 2009, IEEE, 978-1-4244-4511-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
47 | DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De |
Analytical Model for the Propagation Delay of Through Silicon Vias. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 553-556, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
3D integrated circuits, propagation delay model, dimensional analysis, TSV |
47 | Paul D. Franzon, W. Rhett Davis, Michael B. Steer, Steve Lipa, Eun Chu Oh, Thorlindur Thorolfsson, Samson Melamed, Sonali Luniya, Tad Doxsee, Stephen Berkeley, Ben Shani, Kurt Obermiller |
Design and CAD for 3D integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 668-673, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
thermal modeling, TSV, through silicon via, 3DIC |
40 | Tak-Yung Kim, Taewhan Kim |
Clock tree synthesis with pre-bond testability for 3D stacked IC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 723-728, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
optimization, routing, buffer insertion, 3D ICs, clock tree |
40 | Xiang Zhang, Hongda Li, Yuzhong Qu |
Finding Important Vocabulary Within Ontology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASWC ![In: The Semantic Web - ASWC 2006, First Asian Semantic Web Conference, Beijing, China, September 3-7, 2006, Proceedings, pp. 106-112, 2006, Springer, 3-540-38329-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini |
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 598-602, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Jinhyung Lee, Kyungjun Cho, Chang Kwon Lee, Yeonho Lee 0002, Jae-Hyung Park, Su-Hyun Oh, Yucheon Ju, Chunseok Jeong, Ho Sung Cho, Jaeseung Lee, Tae-Sik Yun, Jin Hee Cho, Sangmuk Oh, Junil Moon, Young-Jun Park, Hong-Seok Choi, In-Keun Kim, Seung Min Yang, Sun-Yeol Kim, Jaemin Jang, Jinwook Kim, Seong-Hee Lee, Younghyun Jeon, Juhyung Park, Tae-Kyun Kim, Dongyoon Ka, Sanghoon Oh, Jinse Kim, Junyeol Jeon, Seonhong Kim, Kyeong Tae Kim, Taeho Kim, Hyeonjin Yang, Dongju Yang, Minseop Lee, Heewoong Song, Dongwook Jang, Junghyun Shin, Hyunsik Kim, Chang-Ki Baek, Hajun Jeong, Jongchan Yoon, Seung-Kyun Lim, Kyo Yun Lee, Young Jun Koo, Myeong-Jae Park, Joohwan Cho, Jonghwan Kim |
13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 238-240, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
32 | Kangkang Xu, Yang Yu 0015, Xiyuan Peng |
TSV Fault Modeling and A BIST Solution for TSV Pre-bond Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 39th IEEE VLSI Test Symposium, VTS 2021, San Diego, CA, USA, April 25-28, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1949-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
32 | Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran |
TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(3), pp. 672-685, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
32 | Tianming Ni, Yao Yao, Hao Chang, Lin Lu, Huaguo Liang, Aibin Yan, Zhengfeng Huang, Xiaoqing Wen |
LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10), pp. 2938-2951, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
32 | Tanusree Kaibartta, G. P. Biswas, Debesh Kumar Das |
Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 36(2), pp. 239-253, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
32 | Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran |
TSV-IaS: Analytic Analysis and Low-Cost Non-Preemptive on-Line Detection and Correction Method for TSV Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, FL, USA, July 15-17, 2019, pp. 501-506, 2019, IEEE, 978-1-7281-3391-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
32 | Raviteja P. Reddy, Amit Acharyya, S. Saqib Khursheed |
A Framework for TSV Based 3D-IC to Analyze Aging and TSV Thermo-Mechanical Stress on Soft Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC-Asia ![In: IEEE International Test Conference in Asia, ITC-Asia 2019, Tokyo, Japan, September 3-5, 2019, pp. 121-126, 2019, IEEE, 978-1-7281-4718-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
32 | Jaeseok Park, Minho Cheong, Sungho Kang |
R2-TSV: A Repairable and Reliable TSV Set Structure Reutilizing Redundancies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 66(2), pp. 458-466, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
32 | Saikat Mondal, Sang-Bock Cho, Bruce C. Kim |
Modeling and Crosstalk Evaluation of 3-D TSV-Based Inductor With Ground TSV Shielding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(1), pp. 308-318, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
32 | Sudeep Ghosh, Surajit Kumar Roy, Hafizur Rahaman 0001, Chandan Giri |
TSV repairing for 3D ICs using redundant TSV. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: 7th International Symposium on Embedded Computing and System Design, ISED 2017, Durgapur, India, December 18-20, 2017, pp. 1-5, 2017, IEEE, 978-1-5386-3032-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
32 | Pooria M. Yaghini, Ashkan Eghbal, Siavash S. Yazdi, Nader Bagherzadeh, Michael M. Green |
Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 65(3), pp. 693-705, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
32 | Yarui Peng, Dusan Petranovic, Sung Kyu Lim |
Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12), pp. 1964-1976, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
32 | Pooria M. Yaghini, Ashkan Eghbal, Siavash S. Yazdi, Nader Bagherzadeh |
Accurate System-level TSV-to-TSV Capacitive Coupling Fault Model for 3D-NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Proceedings of the 9th International Symposium on Networks-on-Chip, NOCS 2015, Vancouver, BC, Canada, September 28-30, 2015, pp. 3:1-3:8, 2015, ACM, 978-1-4503-3396-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
32 | Joke De Messemaeker, O. Varela Pedreira, A. Moussa, Nabi Nabiollahi, Kris Vanstreels, Stefaan Van Huylenbroeck, Harold Philipsen, Patrick Verdonck, Bart Vandevelde, Ingrid De Wolf, Eric Beyne, Kris Croes |
Impact of oxide liner properties on TSV Cu pumping and TSV stress. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 4, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
32 | Quan Deng, Minxuan Zhang, Zhenyu Zhao, Peng Li |
Mitigation Techniques Against TSV-to-TSV Coupling in 3DIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCCET ![In: Computer Engineering and Technology - 19th CCF Conference, NCCET 2015, Hefei, China, October 18-20, 2015, Revised Selected Papers, pp. 182-190, 2015, Springer, 978-3-662-49282-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
32 | Caleb Serafy, Bing Shi, Ankur Srivastava 0001 |
A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 47(3), pp. 307-317, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
32 | Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim |
Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12), pp. 1900-1913, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
32 | Fu-Wei Chen, Hui-Ling Ting, TingTing Hwang |
Fault-tolerant TSV by using scan-chain test TSV. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Singapore, January 20-23, 2014, pp. 658-663, 2014, IEEE, 978-1-4799-2816-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
32 | Ashkan Eghbal, Pooria M. Yaghini, Siavash S. Yazdi, Nader Bagherzadeh |
TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, The Netherlands, October 1-3, 2014, pp. 92-97, 2014, IEEE Computer Society, 978-1-4799-6155-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
32 | Khaled Salah 0001 |
Performance comparison between air-gap based coaxial TSV and conventional circular TSV in 3D-ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDT ![In: 8th International Design and Test Symposium, IDT 2013, Marrakesh, Morocco, 16-18 December, 2013, pp. 1-3, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
32 | Zao Liu, Sahana Swarup, Sheldon X.-D. Tan |
Compact lateral thermal resistance modeling and characterization for TSV and TSV array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 2013, pp. 275-280, 2013, IEEE, 978-1-4799-1069-4. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
32 | Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim |
On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 2013, pp. 281-288, 2013, IEEE, 978-1-4799-1069-4. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
32 | Byunghyun Lee, Taewhan Kim |
High-level TSV resource sharing and optimization for TSV based 3D IC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2013 IEEE International SOC Conference, Erlangen, Germany, September 4-6, 2013, pp. 153-158, 2013, IEEE, 978-1-4799-1166-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
32 | Caleb Serafy, Bing Shi, Ankur Srivastava 0001 |
Geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Great Lakes Symposium on VLSI 2013 (part of ECRC), GLSVLSI'13, Paris, France, May 2-4, 2013, pp. 275-280, 2013, ACM, 978-1-4503-2032-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
32 | Shu-Han Wei, Yu-Min Lee, Chia-Tung Ho, Chih-Ting Sun, Liang-Chia Cheng |
Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013, pp. 1-4, 2013, IEEE, 978-1-4673-4435-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
32 | Taigon Song, Chang Liu 0034, Yarui Peng, Sung Kyu Lim |
Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: The 50th Annual Design Automation Conference 2013, DAC '13, Austin, TX, USA, May 29 - June 07, 2013, pp. 180:1-180:7, 2013, ACM, 978-1-4503-2071-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
32 | Patrick Le Maitre, Melanie Brocard, Alexis Farcy, Jean-Claude Marin |
Device and electromagnetic co-simulation of TSV: Substrate noise study and compact modeling of a TSV in a matrix. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012, pp. 404-411, 2012, IEEE, 978-1-4673-1034-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
32 | Wen-Pin Tu, Yen-Hsin Lee, Shih-Hsu Huang |
TSV sharing through multiplexing for TSV count minimization in high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, September 26-28, 2011, pp. 156-159, 2011, IEEE, 978-1-4577-1616-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
32 | Taigon Song, Chang Liu 0034, Dae Hyun Kim 0004, Sung Kyu Lim, Jonghyun Cho, Joohee Kim, Junso Pak, Seungyoung Ahn, Joungho Kim, Kihyun Yoon |
Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011, Santa Clara, California, USA, 14-16 March 2011, pp. 122-128, 2011, IEEE, 978-1-61284-914-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
32 | Chang Liu 0034, Taigon Song, Jonghyun Cho, Joohee Kim, Joungho Kim, Sung Kyu Lim |
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011, pp. 783-788, 2011, ACM, 978-1-4503-0636-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
27 | Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu |
DfT Architecture for 3D-SICs with Multiple Towers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, pp. 51-56, 2011, IEEE Computer Society, 978-0-7695-4433-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
three-dimensional stacking, 3D-SIC, multi-tower, DfT, wrapper, design-for-test, TSV, through-silicon via |
27 | Thorlindur Thorolfsson, Kiran Gonsalves, Paul D. Franzon |
Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 51-56, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FFT, SAR, TSV, 3DIC |
20 | Hsiu-Ming Chang 0001, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu |
An error tolerance scheme for 3D CMOS imagers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 917-922, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
image sensor, error tolerance, 3D IC |
20 | Samta Bansal, Juan C. Rey, Andrew Yang, Myung-Soo Jang, L. C. Lu, Philippe Magarshack, Pol Marchal, Riko Radojcic |
3-D stacked die: now or future? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 298-299, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
integrated circuits, 3-D |
20 | Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka |
Three-dimensional integration technology and integrated systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 409-415, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Nobuaki Miyakawa |
A 3D prototyping chip based on a wafer-level stacking technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 416-420, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan Arani, A. Ege Engin, Chung-Kuan Cheng |
Predicting the worst-case voltage violation in a 3D power network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 93-98, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
worst case violation prediction, integer linear programming, leakage, clock gating, power networks |
20 | Cesare Ferri, Sherief Reda, R. Iris Bahar |
Parametric yield management for 3D ICs: Models and strategies for improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(4), pp. 19:1-19:22, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
performance, process variations, leakage, 3D integration, yield management |
20 | Nobuaki Miyakawa, Eiri Hashimoto, Takanori Maebashi, Natsuo Nakamura, Yutaka Sacho, Shigeto Nakayama, Shinjiro Toyoda |
Multilayer stacking technology using wafer-to-wafer stacked method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(4), pp. 20:1-20:15, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
stacking process, design, hardware, 3D integration |
20 | Cesare Ferri, Sherief Reda, R. Iris Bahar |
Strategies for improving the parametric yield and profits of 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 220-226, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Chen Wei, Xiaole Cui, Xiaoxin Cui |
Dy-MFNS-CAC: An Encoding Mechanism to Suppress the Crosstalk and Repair the Hard Faults in Rectangular TSV Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 73(1), pp. 622-636, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Jun Liu 0070, Songren Cheng, Tian Chen, Xi Wu 0003, Huaguo Liang |
A Self-Biased Current Reference Source-Based Pre-Bond TSV Test Solution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 32(4), pp. 774-781, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Yanan Tao, Chao Liang, Ziqi Mei, Zhiqiang Song, Yu Wu, Yunna Sun, Wenqiang Zhang, Yong Ruan, Xiaoguang Zhao |
Numerical simulation of copper electrodeposition for Through Silicon Via (TSV) with SPS-PEG-Cl additive system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 144, pp. 106089, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Fengjuan Wang, Jilin Kou, Xiangkun Yin, Jiangfan Liu, Kai Jing, Ningmei Yu, Yuan Yang 0006, Qian Li |
A compact fifth-order SIW BPF based on TSV technology with high selectivity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 144, pp. 106067, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Myeong-Jae Park, Jinhyung Lee, Kyungjun Cho, Ji Hwan Park, Junil Moon, Sung-Hak Lee, Tae-Kyun Kim, Sanghoon Oh, Seokwoo Choi, Yongsuk Choi, Ho Sung Cho, Tae-Sik Yun, Young Jun Koo, Jae-Seung Lee, Byung Kuk Yoon, Young Jun Park, Sangmuk Oh, Chang Kwon Lee, Seong-Hee Lee, Hyun-Woo Kim, Yucheon Ju, Seung-Kyun Lim, Kyo Yun Lee, Sang-Hoon Lee, Woo Sung We, Seungchan Kim, Seung Min Yang, Keonho Lee, In-Keun Kim, Younghyun Jeon, Jae-Hyung Park, Jong Chan Yun, Seonyeol Kim, Dong-Yeol Lee, Su-Hyun Oh, Junghyun Shin, Yeonho Lee 0002, Jieun Jang, Joohwan Cho |
A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(1), pp. 256-269, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Ji-Young Kim, Taeryeong Kim, Jeonghyeok You, Ki-Ryong Kim, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung |
An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(11), pp. 3242-3252, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Jindong Zhou, Yuyang Chen, Youliang Jing, Pingqiang Zhou |
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 88, pp. 196-202, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Peng Xu, Huan Huang, Bing-Qi Zhang, Zheng-Hua Tang |
Thermal Performance Analysis of Carbon Materials Based TSV in Three Dimensional Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 75285-75294, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Huangyin Wang, Yikai Xiong, Liming Geng |
Modeling and Thermal Stress Coupling Optimization Design of TSV Inductors in On-Chip DC/DC Converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 133189-133198, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Wenbo Guan, Xiaoyan Tang, Hongliang Lu, Yuming Zhang, Yimen Zhang |
ATT-TA: A Cooperative Multiagent Deep Reinforcement Learning Approach for TSV Assignment in 3-D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 31(12), pp. 1905-1917, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Youngkwang Lee, Donghyun Han, Sungho Kang 0001 |
TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 31(4), pp. 578-590, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Yang Ge, Tejinder Singh Sandhu, Dmitri V. Truhachev, Kamal El-Sankary |
A Single-TSV and Single-DCDL Approach for Skew Compensation of Multi-Dies Clock Synchronization in 3-D-ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 31(4), pp. 567-577, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Wenbo Guan, Xiaoyan Tang, Hongliang Lu, Yuming Zhang, Yimen Zhang |
A Novel Thermal-Aware Floorplanning and TSV Assignment With Game Theory for Fixed-Outline 3-D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 31(11), pp. 1639-1652, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Xianglong Wang, Dongdong Chen 0010, Di Li 0003, Chen Kou, Yintang Yang |
The Development and Progress of Multi-Physics Simulation Design for TSV-Based 3D Integrated System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Symmetry ![In: Symmetry 15(2), pp. 418, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Xianglong Wang, Yintang Yang, Dongdong Chen 0010, Di Li 0003 |
A High-Efficiency Design Method of TSV Array for Thermal Management of 3-D Integrated System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6), pp. 1733-1741, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Xiaole Cui, Chen Wei, Xu Feng, Xiaoxin Cui |
Mosaic-3C1S: A Low Overhead Crosstalk Suppression Scheme for Rectangular TSV Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5), pp. 1380-1392, May 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Tao Gong, Si Chen, Kai Li, Guoyuan Li, Zhizhe Wang, Xiaofeng Yang, Xiaodong Jian, Zhiwei Fu |
Study on the electrical breakdown failure mode transition of TSV-RDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 141, pp. 105982, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Fengjuan Wang, Zhuoyu Yang, Xiangkun Yin, Ningmei Yu, Yuan Yang |
TSV-based SIW bandpass filter with adjustable transmission zeros for D-band applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 20(10), pp. 20230116, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Tsague Cathy, Medjo Astrid, Jean Seutche, Tchinda Rene |
Assessment of Thermal Comfort Using PMV, aPMV, ePMV and TSV Indices in a Naturally Ventilated Building. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAFER-TEA ![In: Safe, Secure, Ethical, Responsible Technologies and Emerging Applications - First EAI International Conference, SAFER-TEA 2023, Yaoundé, Cameroon, October 25-27, 2023, Proceedings, pp. 200-215, 2023, Springer, 978-3-031-56395-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Jiayi Shen, Chang Liu, Tadaaki Hoshi, Atsushi Sinoda, Hisashi Kino, Tetsu Tanaka, Mariappan Murugesan, Mitsumasa Koyanagi, Takafumi Fukushima |
Impact of Super-long-throw PVD on TSV Metallization and Die-to-Wafer 3D Integration Based on Via-last. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3DIC ![In: IEEE International 3D Systems Integration Conference, 3DIC 2023, Cork, Ireland, May 10-12, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-1137-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Song Wang, Bing Yu, Wenwu Xiao, Fujun Bai, Xiaodong Long, Liang Bai, Xuerong Jia, Fengguo Zuo, Jie Tan, Yixin Guo, Peng Sun, Jun Zhou, Qiong Zhan, Sheng Hu, Yu Zhou, Yi Kang, Qiwei Ren, Xiping Jiang |
A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | C.-L. Lu, C.-H. Chuang, C.-H. Huang, S.-C. Lin, Y.-H. Chang, W.-Y. Lai, M.-H. Chiu, Ming Han Liao, S.-Z. Chang |
4-Layer Wafer on Wafer Stacking Demonstration with Face to Face/Face to Back Stacked Flexibility Using Hybrid Bond/TSV-Middle for Various 3D Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Taeryeong Kim, Ji-Young Kim, Jeonghyeok You, Hohyun Chae, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung |
A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Takeshi Ohkawa, Masahiro Aoyagi |
FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COOL CHIPS ![In: IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2023, Tokyo, Japan, April 19-21, 2023, pp. 1-3, 2023, IEEE, 979-8-3503-3201-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | He Junsen, Dong-Hyun Yoon, Tony Tae-Hyoung Kim |
An Effective Faulty TSV Detection Scheme for TSVs in High Bandwidth Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, pp. 1-5, 2023, IEEE, 978-1-6654-5109-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Sunghoon Kim, Donghyun Han, Seokjun Jang, Sungho Kang 0001 |
LOTS: Low Overhead TSV Repair Method Using IEEE-1838 Standard Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 20th International SoC Design Conference, ISOCC 2023, Jeju, Republic of Korea, October 25-28, 2023, pp. 289-290, 2023, IEEE, 979-8-3503-2703-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Junpeng Wang, Christoph Neuhauser, Jun Wu 0005, Xifeng Gao, Rüdiger Westermann |
3D-TSV: The 3D trajectory-based stress visualizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Adv. Eng. Softw. ![In: Adv. Eng. Softw. 170, pp. 103144, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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16 | Yingbo Zhao, Qingyang Fan |
Frequency-Dependent Characteristics and Parametric Modeling of the Silicon Substrate in TSV-Based 3-D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 134349-134355, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Xiangliang Li, Peng Zhao 0003, Shichang Chen, Kuiwen Xu, Gaofeng Wang |
A Deep-Learning Approach for Wideband Design of 3D TSV-Based Inductors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 133673-133681, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Fengjuan Wang, Kai Zhang, Xiangkun Yin, Ningmei Yu, Yuan Yang 0006 |
A Miniaturized Wideband Interdigital Bandpass Filter With High Out-Band Suppression Based on TSV Technology for W-Band Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 30(7), pp. 989-992, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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16 | Qi Xu, Hao Geng, Tianming Ni, Song Chen 0001, Bei Yu 0001, Yi Kang, Xiaoqing Wen |
Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10), pp. 3182-3187, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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16 | Sangmin Park, Minho Cheong, Donghyun Han, Sungho Kang 0001 |
Herringbone-Based TSV Architecture for Clustered Fault Repair and Aging Recovery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4), pp. 1142-1153, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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16 | Qi Xu, Wenhao Sun, Song Chen 0001, Yi Kang, Xiaoqing Wen |
Cellular Structure-Based Fault-Tolerance TSV Configuration in 3D-IC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5), pp. 1196-1208, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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16 | Kangkang Xu, Yang Yu 0015, Xu Fang |
The Detection of Open and Leakage Faults for Prebond TSV Test Based on Weak Current Source. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9), pp. 2768-2779, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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16 | Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri |
A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 18(4), pp. 70:1-70:23, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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16 | Fengjuan Wang, Ruiqi Li, Xiangkun Yin, Ningmei Yu, Yuan Yang 0006 |
Compact high-performance dual-frequency power divider based on TSV. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 129, pp. 105580, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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16 | Chenyi Wen, Xiao Dong, Baixin Chen, Umamaheswara Rao Tida, Yiyu Shi 0001, Cheng Zhuo |
Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 27(5), pp. 52:1-52:23, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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16 | Shashikiran Venkatesha, Ranjani Parthasarathi |
A Survey of fault models and fault tolerance methods for 2D bus-based multi-core systems and TSV based 3D NOC many-core systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2203.07830, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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16 | Chen Wei, Xiaole Cui, Xiaoxin Cui |
A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 39(5), pp. 26-33, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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16 | Tianming Ni, Jingchang Bian, Zhao Yang, Mu Nie, Liang Yao, Zhengfeng Huang, Aibin Yan, Xiaoqing Wen |
Broadcast-TDMA: A Cost-Effective Fault-Tolerance Method for TSV Lifetime Reliability Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 39(5), pp. 34-42, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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16 | Fengjuan Wang, Sa Xiao, Xiangkun Yin, Ningmei Yu, Yuan Yang 0006 |
A miniature TSV-based branch line coupler using π equivalent circuit model for transmission line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 19(3), pp. 20210515, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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16 | Fengjuan Wang, Quan Peng, Ningmei Yu, Yuan Yang |
TSV-based SIW bandpass filter for W-band mobile communication applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 19(12), pp. 20220187, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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16 | Yuchen Wu, Yao Liu, Zhao Zhao, Chunfeng Liu 0001, Wenyu Qu |
TSV-MAC: Time Slot Variable MAC Protocol Based on Deep Reinforcement Learning for UASNs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WASA (3) ![In: Wireless Algorithms, Systems, and Applications - 17th International Conference, WASA 2022, Dalian, China, November 24-26, 2022, Proceedings, Part III, pp. 225-237, 2022, Springer, 978-3-031-19210-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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16 | H. Zheng, Y. S. Sun, J. L. Huang |
Impact of TSV on TDDB Performance of Neighboring FinFET with HK/IL Gate Stacking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2022, Dallas, TX, USA, March 27-31, 2022, pp. 4, 2022, IEEE, 978-1-6654-7950-9. The full citation details ...](Pics/full.jpeg) |
2022 |
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