Search results for "benchmark"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth	Synthesis for Testability by Two-Clock Control.	VLSI Design	1997	DBLP DOI BibTeX RDF	two-clock control scheme, split coding system, FSM benchmark, timing, finite state machine, sequential circuit, encoding, logic synthesis, Hamiltonian cycle, synthesis for testability, state transition graph
16	Jianzhong Shi, Akash Randhar, Dinesh Bhatia	Macro Block Based FPGA Floorplanning.	VLSI Design	1997	DBLP DOI BibTeX RDF	macro block based FPGA floorplanning, FPGA based designs, very large designs, performance driven designs, constraint-based FPGA floorplanning, flexible macro blocks, fixed macro blocks, input constraint set, topological placement, FPGA architectural constraints, large benchmark examples, VLSI floorplanning, heuristic algorithm, integrated circuit layout, ASIC design
16	Elizabeth M. Rudnick, Janak H. Patel	Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation.	VLSI Design	1997	DBLP DOI BibTeX RDF	serial logic simulation bottleneck, parallel fault simulation, sequential circuit fault simulation algorithms, fault-partitioning approach, test set partitioning, parallel architectures, logic CAD, fault coverage, speedup, benchmark circuits
16	Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler	Deriving Signal Constraints to Accelerate Sequential Test Generation.	VLSI Design	1997	DBLP DOI BibTeX RDF	sequential test generation algorithm acceleration, signal constraints, large sequential circuits, deterministic sequential test generation, signal constraint computation technique, line probabilities, line justification techniques, benchmark sequential circuits, test generation time reduction, production sequential circuits, 3-valued signal probabilities, fault diagnosis, fault coverage, symbolic simulation, truth table
16	Edward D. Moreno, Sergio Takeo Kofuji	Efficiency of remote access caches in future SMP-based CC-NUMA multiprocessors: initial results.	ISPAN	1997	DBLP DOI BibTeX RDF	shared remote access cache, future SMP based CC-NUMA multiprocessors, symmetric multiprocessor nodes, future architectures, realistic hardware parameters, state of the art systems components, SPLASH-2 benchmark suite, performance application, baseline architecture, approach-1, slow network, approach-2, fast network, 32-processor system, four-processor SMP nodes, two-processor SMP nodes, multiprocessing systems, execution time, cost effectiveness
16	Akira Koseki, Hideaki Komatsu, Yoshiaki Fukazawa	A method for estimating optimal unrolling times for nested loops.	ISPAN	1997	DBLP DOI BibTeX RDF	reuse of data, benchmark tests, parallelization, parallelism, heuristic algorithm, heuristic programming, nested loops, loop unrolling
16	Volker F. Märgner, P. Karcher, A.-K. Pawlowski	On Benchmarking of Document Analysis Systems.	ICDAR	1997	DBLP DOI BibTeX RDF	evaluation, image processing, benchmark, document analysis, ground truth
16	Wolfgang K. Giloi, Ulrich Brüning 0001, Wolfgang Schröder-Preikschat	MANNA: Prototype of a Distributed Memory Architecture with Maximized Sustained Performance.	PDP	1996	DBLP DOI BibTeX RDF	maximized sustained performance, compiler problem, innovative architectural solutions, overlapping communication, MANNA computer, benchmark performance, performance evaluation, parallel computers, operating system, parallel machines, distributed memory systems, parallelizing compilers, operating systems (computers), programmability, virtual storage, parallelising compilers, latency hiding, distributed memory parallel computer, distributed memory architecture, virtual shared memory, global address space, superscalar microprocessors
16	Erich Schikuta, Peter Kirkovits	Analysis and Evaluation of Sorting on Hypercube-Based Systems.	PDP	1996	DBLP DOI BibTeX RDF	hypercube-based systems, disk based sorting, parallel merge sort, bitonic sort algorithms, performance, parallel algorithms, benchmark, distributed databases, sorting, sorting, database theory, hypercube networks, software performance evaluation, merging, parallel database systems, database operations
16	Shlomit S. Pinter, Adi Yoaz	Tango: A Hardware-Based Data Prefetching Technique for Superscalar Processors.	MICRO	1996	DBLP DOI BibTeX RDF	LRU mechanism, SPEC92 benchmark, Tango, base line architecture, hardware-based data prefetching technique, memory reference instructions, program progress graph, performance, parallel processing, instruction level parallelism, simulation results, superscalar processors, branch target buffer, instruction prefetching, hardware resources, slack time
16	M. D. Baba, Hsmail Ekiz, A. Kutlu, E. T. Powner	Toward adaptable distributed real-time computer systems.	RTCSA	1996	DBLP DOI BibTeX RDF	adaptable distributed real-time computer systems, processing nodes, environmental changes, imprecise technique, fault tolerance mechanism, automotive benchmark signals, performance, distributed processing, timing constraints, controller area network, simulation study, communication channel, safety critical application, real-time computer system, scheduling strategy, component failures
16	Shantanu Dutt, Wenyong Deng	VLSI circuit partitioning by cluster-removal using iterative improvement techniques.	ICCAD	1996	DBLP DOI BibTeX RDF	ACM/SIGDA benchmark circuits, Fiduccia-Mattheyses algorithm, VLSI circuit partitioning, cluster-removal, iterative improvement techniques, look-ahead algorithm, partition quality, spectral partitioner MELO, VLSI, CAD
16	Anthony-Trung Nguyen, Maged M. Michael, Arun Sharma, Josep Torrellas	The Augmint multiprocessor simulation toolkit for Intel x86 architectures.	ICCD	1996	DBLP DOI BibTeX RDF	Augmint multiprocessor simulation toolkit, Intel x86 architectures, publicly available simulation tools, instruction mix, memory reference patterns, CISC architectures, execution driven multiprocessor simulation toolkit, m4 macro extended C, C++ applications, SPLASH-2 benchmark suites, thread based programming model, shared global address space, private stack space, simulator interface, MINT simulation toolkit, x8d based uniprocessor systems, multiprocessing systems, trace driven simulation, architecture simulators, uniprocessors
16	Sung-Kwan Kim, Sang Lyul Min, Rhan Ha	Efficient worst case timing analysis of data caching.	IEEE Real Time Technology and Applications Symposium	1996	DBLP DOI BibTeX RDF	efficient worst case timing analysis, accurate timing analysis, pipelined execution, multiple memory locations, pointer based references, dynamic load/store instructions, WCET overestimation, global data flow analysis, benchmark programs, real-time systems, computational complexity, data caching, cache storage, instruction sets, reduced instruction set computing, data dependence analysis, cache block
16	Mukund Sivaraman, Andrzej J. Strojwas	A diagnosability metric for parametric path delay faults.	VTS	1996	DBLP DOI BibTeX RDF	diagnosability metric, parametric path delay faults, test vector pairs, chip failure, fabrication process parameter variations, diagnosis framework, ISCAS'89 benchmark circuits, VLSI, fault diagnosis, logic testing, delays, timing, integrated circuit testing, failure analysis, diagnosability, delay fault testing, test set
16	Michel Renovell, P. Huc, Yves Bertrand	Bridging fault coverage improvement by power supply control.	VTS	1996	DBLP DOI BibTeX RDF	bridging fault coverage, power supply control, resistance interval, faulty value, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, automatic testing, logic circuits, parametric model, benchmark circuits
16	Mukund Sivaraman, Andrzej J. Strojwas	Diagnosis of parametric path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	parametric path delay faults, chip failure, fabrication process parameter values, path sensitization mechanism, path delay conditions, ISCAS'89 benchmark circuits, path segment, circuit failure, fault diagnosis, logic testing, logic testing, delays, probability, probability, statistical analysis, statistical analysis, integrated circuit testing, failure analysis, diagnosability, delay fault testing, IC testing, production testing
16	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	On test coverage of path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	two-pass test generation method, falling transition, line delay test, longest sensitizable path, decreasing length, redundant stuck-at fault, computational complexity, fault diagnosis, logic testing, delays, redundancy, combinational circuits, fault simulation, circuit analysis computing, test coverage, path delay faults, benchmark circuits, coverage metric, combinational logic circuits, longest paths
16	Axel van Lamsweerde, Robert Darimont, Philippe Massonet	Goal-directed elaboration of requirements for a meeting scheduler: problems and lessons learnt.	RE	1995	DBLP DOI BibTeX RDF	goal-directed elaboration, requirements engineering languages, nontrivial benchmark, complex requirements engineering tasks, distributed meeting scheduler system, KAOS goal directed language, goal identification, deidelization, interfering goals, abstract descriptions, retractable assumptions, hybrid acquisition strategies, scheduling, formal specification, groupware, case study, specification languages, requirements traceability, formal reasoning, meeting scheduler
16	Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu	ARAS: asynchronous RISC architecture simulator.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous RISC architecture simulator, ARAS, pipeline instruction simulator, benchmark programs, pipeline configuration, asynchronous pipeline architectures, performance evaluation, parallel architectures, virtual machines, performance measurements, pipeline processing
16	Debesh K. Das, Bhargab B. Bhattacharya	Testable design of non-scan sequential circuits using extra logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, sequentially redundant faults, multiple stuck-at-fault model, augmented logic, performance evaluation, logic testing, redundancy, test generation, design for testability, logic design, sequential circuits, logic synthesis, synchronous sequential circuits, benchmark circuits, testable design
16	Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck	Deterministic test generation for non-classical faults on the gate level.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
16	Eiji Harada, Janak H. Patel	Overhead reduction techniques for hierarchical fault simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	overhead reduction techniques, hierarchical fault simulation, simulation overhead, concurrent method, multi-list-traversal method, one-pass fault simulation strategy, characteristic vectors, contiguous concurrent machines, ISCAS benchmark circuits, fault ordering, logic test sequences, fault diagnosis, logic testing, combinational circuits, logic CAD, digital simulation, circuit analysis computing, concurrent engineering, multivalued logic circuits, ULSI, ULSI
16	Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu	Generation of tenacious tests for small gate delay faults in combinational circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	tenacious tests, small gate delay faults, single gate delay fault, ISCAS'85 benchmark circuits, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuits, fault coverage
16	Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey	A simple technique for locating gate-level faults in combinational circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	electron probe analysis, optical microscopy, gate-level faults, error sources, fault deduction, fault elimination, ISCAS'85 benchmark circuits, physical defect analysis, electron beam probing, light emission microscopy, computational complexity, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, digital simulation, circuit analysis computing, computation time, scanning electron microscopy, scanning electron microscopy, diagnostic resolution
16	Hiroshi Date, Michinobu Nakao, Kazumi Hatayama	A parallel sequential test generation system DESCARTES based on real-valued logic simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	parallel sequential test generation system, DESCARTES, real-valued logic simulation, redundant fault identification program, algorithmic test generation program, ISCAS '89 benchmark sequential circuits, distributed processing environment oriented system, concurrent accelerative test generation, parallel algorithms, computational complexity, VLSI, fault diagnosis, logic testing, redundancy, design for testability, sequential circuits, logic CAD, VLSI design, stuck-at faults, automatic test generation, synchronous sequential circuits, automatic test software, test quality
16	Sundeep Prakash, Rajive L. Bagrodia	An adaptive synchronization method for unpredictable communication patterns in dataparallel programs.	IPPS	1995	DBLP DOI BibTeX RDF	adaptive synchronization method, unpredictable communication patterns, dataparallel programs, inspector-executor method, IBM SP1 multicomputer, synthetic benchmark codes, performance, parallel programming, compiler, code generation, synchronisation, program compilers, software performance evaluation, communication patterns
16	Gyungho Lee	An assessment of COMA multiprocessors.	IPPS	1995	DBLP DOI BibTeX RDF	Cache Only Memory Architecture, Perfect Club Benchmark Suite, coherence policy, performance evaluation, performance, discrete event simulation, memory hierarchy, shared memory systems, distributed memory systems, update, trace driven simulations, cache storage, network traffic, miss ratio, distributed shared memory multiprocessors, shared address space, invalidate
16	Pranav Ashar, Sharad Malik	Fast functional simulation using branching programs.	ICCAD	1995	DBLP DOI BibTeX RDF	compiled code simulation, cycle-based functional simulation, fast functional simulation, functional delay-independent logic simulation, levelized compiled-code, switch level functional simulation, synchronous digital systems, Boolean functions, system design, logic design, logic CAD, decision theory, circuit analysis computing, benchmark circuits, branching programs
16	Sudhakar M. Reddy	Testing-what's missing? An incomplete list of challenges.	ICCD	1995	DBLP DOI BibTeX RDF	testing area, quality guarantees, special-purpose procedures, integrated design and test, high-level failure models, program testing, computer testing, benchmark circuits, design cycle
16	Yu Fang, Alexander Albicki	Efficient testability enhancement for combinational circuit.	ICCD	1995	DBLP DOI BibTeX RDF	testability enhancement, combinational circuit testing, XOR Chain Structure, insertion points, random pattern resistant node source tracking, ISCAS85, performance evaluation, VLSI, VLSI, logic testing, controllability, built-in self test, combinational circuits, automatic testing, automatic testing, observability, testability analysis, benchmark circuits, hardware overhead, performance penalty
16	Steven Parkes, Prithviraj Banerjee, Janak H. Patel	A parallel algorithm for fault simulation based on PROOFS .	ICCD	1995	DBLP DOI BibTeX RDF	fault partitioning, dynamic partitioning schemes, compute intensive task, integrated circuit design process, rapid design turn around, ProperPROOFS, parallel extension, PROOFS fault simulation package, distributed method, fault redistribution, ISCAS-89 benchmark set, high performance serial fault simulation applications, parallel algorithms, parallel algorithm, parallel architectures, parallel architectures, fault diagnosis, logic testing, sequential circuits, sequential circuits, circuit analysis computing, logic partitioning
16	John Drummond, Michael Wu	A low level analysis of the realtime Mach distributed operating system.	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	real-time Mach distributed operating system, low level analysis, real-time operating system software development arena, segmented appraisal, specific element analysis, Rhealstone benchmark, task switch time, preemption time, interrupt latency time, semaphore shuffling time, deadlock breaking time, interprocess communication latency time, conditioned environment, evaluation, real-time systems, distributed processing, software performance evaluation, operating systems (computers), network operating systems, measuring techniques
16	Ted Stanion, Carl Sechen	Quasi-algebraic decompositions of switching functions.	ARVLSI	1995	DBLP DOI BibTeX RDF	quasi-algebraic decompositions, algebraic product, binary Boolean operation, canonical manner, SSL testable, logic testing, testability, switching functions, switching functions, state assignment, minimisation of switching nets, benchmark circuits, circuit size
16	Mårten Björkman, Fredrik Dahlgren, Per Stenström	Using hints to reduce the read miss penalty for flat COMA protocols.	HICSS (1)	1995	DBLP DOI BibTeX RDF	read miss penalty, flat COMA protocols, flat cache-only memory architectures, attraction-memory miss, directory interrogation, network traversals, data copy holder identity tracking, benchmark applications, protocol complexity, performance evaluation, transaction processing, memory architecture, cache storage, performance improvement, hints, architectural simulations, memory protocols
16	Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges	Statistical estimation of delay fault detectabilities and fault grading.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	delay fault detectabilities, fault grading, STAFAN, transition observabilities, fanout stems, fanout free region, gate line transition controllabilities, VLSI, fault diagnosis, logic testing, logic testing, statistical analysis, fault coverage, benchmark circuits, statistical estimation
16	Mark C. Hansen, John P. Hayes	High-level test generation using physically-induced faults.	VTS	1995	DBLP DOI BibTeX RDF	high-level test generation, physically-induced faults, industry-standard single stuck-line faults, independent functional faults, near-minimal size, fault diagnosis, logic testing, integrated circuit testing, design for testability, automatic testing, functional tests, failure analysis, benchmark circuits, circuit under test
16	Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel	Cyclic stress tests for full scan circuits.	VTS	1995	DBLP DOI BibTeX RDF	cyclic stress tests, fully testable unpackaged dies, burn-in process, cyclic input sequences, stress related problems, ISCAS89 benchmark circuits, monitored burn-in problems, IC reliability, VLSI, VLSI, logic testing, integrated circuit testing, CMOS, CMOS logic circuits, boundary scan testing, MCMs, integrated circuit reliability, full scan circuits
16	Rajesh Nair, Dong Sam Ha	VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	parallel pattern fault simulator, VLSI, VLSI, fault diagnosis, heuristics, logic testing, integrated circuit testing, sequential circuits, digital simulation, VISION, circuit analysis computing, flip-flops, synchronous sequential circuits, benchmark circuits
16	Mahsa Vahidi, Alex Orailoglu	Testability metrics for synthesis of self-testable designs and effective test plans.	VTS	1995	DBLP DOI BibTeX RDF	testability metrics, self-testable designs, effective test plans, unified metrics, synthesis phases, VLSI, VLSI, built-in self test, high level synthesis, high level synthesis, design for testability, BIST, DFT, logic CAD, integrated circuit design, benchmark designs
16	Ting-Yu Kuo, Chun-Yeh Liu, Kewal K. Saluja	An optimized testable architecture for finite state machines.	VTS	1995	DBLP DOI BibTeX RDF	optimized testable architecture, FSM synthesis, testable machine, transfer sequences, synthesis benchmark circuits, logic testing, finite state machines, finite state machines, sequential circuits, logic CAD, sequences, circuit optimisation, distinguishing sequences, synchronizing sequence
16	Tomoo Inoue, Hironori Maeda, Hideo Fujiwara	A scheduling problem in test generation.	VTS	1995	DBLP DOI BibTeX RDF	test generation schedule, testing cost, dominating probability, ISCAS'85 benchmark circuits, combinational logic circuit testing, scheduling, logic testing, probability, integrated circuit testing, combinational circuits, automatic testing, test-pattern generation, processing time, scheduling problem
16	Alessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò	Reliability evaluation of combinational logic circuits by symbolic simulation.	VTS	1995	DBLP DOI BibTeX RDF	mcnc benchmark circuits, fault-tolerant combinational logic circuits, circuit functionality, fault indicators, control variables, BDD-based symbolic simulation, undetectable multiple faults, VLSI, VLSI, combinational circuits, logic CAD, digital simulation, circuit analysis computing, reliability evaluation, integrated circuit reliability
16	Andrej Zemva, Franc Brglez	Detectable perturbations: a paradigm for technology-specific multi-fault test generation.	VTS	1995	DBLP DOI BibTeX RDF	detectable perturbations, technology-specific multi-fault test generation, multiple bridging, open faults, single-output modules, multi-output modules, mutation faults, technology-mapped cells, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, stuck-at faults, cellular arrays, benchmark circuits, generic system
16	Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams	On the decline of testing efficiency as fault coverage approaches 100%.	VTS	1995	DBLP DOI BibTeX RDF	single stuck-at fault model, ISCAS benchmark circuits, nontarget defects, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault coverage, test pattern generation, manufacturing process, test quality, production testing, testing efficiency, circuit sizes
16	A. Pal, R. K. Gorai, V. V. S. S. Raju	Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs.	VLSI Design	1995	DBLP DOI BibTeX RDF	multiplexing equipment, multiplexer network, ratio parameters, Actel ACT1, MCNC benchmark problems, field programmable gate arrays, FPGAs, VLSI, Boolean functions, Boolean functions, logic design, iterative methods, combinational circuits, combinational circuits, logic CAD, multiplexing, search space, tree network, iterative approach
16	Alok Kumar, Anshul Kumar, M. Balakrishnan	Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis.	VLSI Design	1995	DBLP DOI BibTeX RDF	heuristic search based approach, VITAL, partial binding sub-tasks, design styles, component types, scheduling, scheduling, computational complexity, VLSI, high level synthesis, search problems, cost estimates, allocation, computation time, binding, design constraints, solution quality, data path synthesis, benchmark designs
16	Khushro Shahookar, Pinaki Mazumder	Genetic multiway partitioning.	VLSI Design	1995	DBLP DOI BibTeX RDF	genetic multiway partitioning, result quality, binary chromosome, bit-mask operations, net cut evaluation, MCNC benchmark circuits, cut size, genetic algorithms, VLSI, VLSI, CAD, software tools, software tool, logic CAD, mutation, circuit CAD, crossover, cellular arrays, cost function, circuit optimisation, logic partitioning, multiple objectives, bipartitioning
16	Robert A. Basta, William H. Greene	A system engineering methodology for predicting scalability of very large real-time databases.	ICECCS	1995	DBLP DOI BibTeX RDF	system engineering methodology, scalable system design, scalability prediction, very large real-time databases, real-time access, accurate performance analysis, implementation alternative evaluation, physical benchmark configuration, subset functionality, database configuration, upscale model, simulation, model, real-time systems, query processing, systems analysis, iterative methods, reconfigurable architectures, systems engineering, software performance evaluation, simulation results, very large databases, iterative process, performance data
16	Philip S. Yu, Ming-Syan Chen, Hans-Ulrich Heiss, Sukho Lee	On Workload Characterization of Relational Database Environments.	IEEE Trans. Software Eng.	1992	DBLP DOI BibTeX RDF	relational database workload analyzer, REDWAR, DB2 environment, database catalog, run-time behavior, benchmark workload, relational databases, SQL, query languages, systems analysis, database theory, views, DP management, design tradeoffs, structured query language
16	Jayantha A. Herath, Yoshinori Yamaguchi, Nobuo Saito, Toshitsugu Yuba	Dataflow Computing Models, Languages, and Machines for Intelligence Computations.	IEEE Trans. Software Eng.	1988	DBLP DOI BibTeX RDF	intelligence computations, dataflow computing models, dataflow computing machines, high-level-language-graph transformations, dataflow computing environment, DCBL, benchmark programs, EM-3, performance evaluation, performance evaluation, parallel programming, parallel programming, functional programming, parallel machines, Lisp, LISP, high level languages, ETL, dataflow languages
15	Martin Schoeberl, Thomas B. Preußer, Sascha Uhrig	The embedded Java benchmark suite JemBench.	JTRES	2010	DBLP DOI BibTeX RDF
15	Jerry Rolia, Diwakar Krishnamurthy, Giuliano Casale, Stephen Dawson	BAP: a benchmark-driven algebraic method for the performance engineering of customized services.	WOSP/SIPEW	2010	DBLP DOI BibTeX RDF	design
15	Anthony Danalis, Gabriel Marin, Collin McCurdy, Jeremy S. Meredith, Philip C. Roth, Kyle Spafford, Vinod Tipparaju, Jeffrey S. Vetter	The Scalable Heterogeneous Computing (SHOC) benchmark suite.	GPGPU	2010	DBLP DOI BibTeX RDF	performance, benchmarking, GPGPU, graphics processors
15	Tilmann Rabl, Andreas Lang, Thomas Hackl, Bernhard Sick, Harald Kosch	Generating Shifting Workloads to Benchmark Adaptability in Relational Database Systems.	TPCTC	2009	DBLP DOI BibTeX RDF	Time Series Generation, Adaptability, Benchmarking, Polynomial Approximation
15	Karl Huppler	The Art of Building a Good Benchmark.	TPCTC	2009	DBLP DOI BibTeX RDF
15	Carsten Binnig, Donald Kossmann, Tim Kraska, Simon Loesing	How is the weather tomorrow?: towards a benchmark for the cloud.	DBTest	2009	DBLP DOI BibTeX RDF
15	Ningfang Mi, Giuliano Casale, Ludmila Cherkasova, Evgenia Smirni	Injecting realistic burstiness to a traditional client-server benchmark.	ICAC	2009	DBLP DOI BibTeX RDF	client-server benchmarks, index of dispersion, performance evaluation of self-managed systems, burstiness
15	Javier Carranza-Tresoldi	Argentine subnational case and Chilean national case of revenue internet services: is there a new e-tax benchmark arising in South America?	ICEGOV	2009	DBLP DOI BibTeX RDF	South America, e-filing, e-tax system, web service, e-government, transparency
15	Benoît Le Bonhomme, Marius Preda, Françoise J. Prêteux	MyMultiMediaWorld.com: A benchmark platform for 3D compression algorithms.	ICIP	2008	DBLP DOI BibTeX RDF
15	Michael Schmidt 0002, Thomas Hornung 0001, Norbert Küchlin, Georg Lausen, Christoph Pinkel	An Experimental Comparison of RDF Data Management Approaches in a SPARQL Benchmark Scenario.	ISWC	2008	DBLP DOI BibTeX RDF
15	Lajos Jeno Fülöp, Péter Hegedüs, Rudolf Ferenc, Tibor Gyimóthy	Towards a Benchmark for Evaluating Reverse Engineering Tools.	WCRE	2008	DBLP DOI BibTeX RDF
15	Larry D. Gray, Anil Kumar, Harry H. Li	Workload Characterization of the SPECpower_ssj2008 Benchmark.	SIPEW	2008	DBLP DOI BibTeX RDF
15	Kiyoung Kim, Kyungho Jeon, Hyuck Han, Shin Gyu Kim, Hyungsoo Jung 0001, Heon Young Yeom	MRBench: A Benchmark for MapReduce Framework.	ICPADS	2008	DBLP DOI BibTeX RDF
15	Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii	CHStone: A benchmark program suite for practical C-based high-level synthesis.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Christian Bienia, Sanjeev Kumar, Kai Li 0001	PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors.	IISWC	2008	DBLP DOI BibTeX RDF
15	Olivier Michel, Fabien Rohrer, Yvan Bourquin	Rat's Life: A Cognitive Robotics Benchmark.	EUROS	2008	DBLP DOI BibTeX RDF
15	Nicolas Bruno	A critical look at the TAB benchmark for physical design tools.	SIGMOD Rec.	2007	DBLP DOI BibTeX RDF
15	Gareth W. Morris, Matthew Aubury	Design Space Exploration of the European Option Benchmark Using HyperStreams.	FPL	2007	DBLP DOI BibTeX RDF
15	Alexander C. Loui, Jiebo Luo, Shih-Fu Chang, Dan Ellis, Wei Jiang 0001, Lyndon S. Kennedy, Keansub Lee, Akira Yanagawa	Kodak's consumer video benchmark data set: concept definition and annotation.	Multimedia Information Retrieval	2007	DBLP DOI BibTeX RDF	consumer video indexing, semantic indexing, video classification, multimedia ontology
15	Andrew D. Ker	The ultimate steganalysis benchmark?	MM&Sec	2007	DBLP DOI BibTeX RDF	steganographic capacity, benchmarking, steganalysis
15	Hui Zhang, Martin Schmucker, Xiamu Niu	The Design and Application of PHABS: A Novel Benchmark Platform for Perceptual Hashing Algorithms.	ICME	2007	DBLP DOI BibTeX RDF
15	Rachid Guerraoui, Michal Kapalka, Jan Vitek	STMBench7: a benchmark for software transactional memory.	EuroSys	2007	DBLP DOI BibTeX RDF	benchmarks, software transactional memory
15	Markos Markou, Maneesha Singh, Peng Wang 0002	Neural network analysis of MINERVA scene image benchmark.	Neural Comput. Appl.	2006	DBLP DOI BibTeX RDF
15	Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Heng Wai Leong	FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach.	FPL	2006	DBLP DOI BibTeX RDF
15	Oguz Altun, Nilgun Dursunoglu, Mehmet Fatih Amasyali	Clustering Application Benchmark.	IISWC	2006	DBLP DOI BibTeX RDF
15	Frank Chiang, Robin Braun	Towards a Management Paradigm with a Constrained Benchmark for Autonomic Communications.	CIS	2006	DBLP DOI BibTeX RDF
15	Steven J. Plimpton, Ron Brightwell, Courtenay T. Vaughan, Keith D. Underwood, Mike Davis	A Simple Synchronous Distributed-Memory Algorithm for the HPCC RandomAccess Benchmark.	CLUSTER	2006	DBLP DOI BibTeX RDF
15	Itamar Elhanany, Derek Chiou, Vahid Tabatabaee, Raffaele Noro, Ali Poursepanj	The Network Processing Forum switch fabric benchmark specifications: an overview.	IEEE Netw.	2005	DBLP DOI BibTeX RDF
15	Pedro J. Ballester, John Stephenson, Jonathan N. Carter, Kerry Gallagher	Real-parameter optimization performance study on the CEC-2005 benchmark with SPC-PNX.	Congress on Evolutionary Computation	2005	DBLP DOI BibTeX RDF
15	Hoe Jin Jeong, Sang Ho Lee	An Integrated Database Benchmark Suite.	SKG	2005	DBLP DOI BibTeX RDF
15	Lingjun Meng, Peter van der Putten, Haiyang Wang	A Comprehensive Benchmark of the Artificial Immune Recognition System (AIRS).	ADMA	2005	DBLP DOI BibTeX RDF
15	Narada Wickramage, Sanjiva Weerawarana	A Benchmark for Web Service Frameworks.	IEEE SCC	2005	DBLP DOI BibTeX RDF
15	Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha	GraalBench: a 3D graphics benchmark suite for mobile phones.	LCTES	2004	DBLP DOI BibTeX RDF	3D graphics benchmarking, embedded 3D graphics architectures
15	Benjamin Bin Yao, M. Tamer Özsu, Nitin Khandelwal	XBench Benchmark and Performance Testing of XML DBMSs.	ICDE	2004	DBLP DOI BibTeX RDF
15	Liang Peng, Simon See, Jie Song 0005, Appie Stoelwinder, Hoon Kang Neo	Benchmark Performance on Cluster Grid with NGB.	IPDPS	2004	DBLP DOI BibTeX RDF
15	Philip Shilane, Patrick Min, Michael M. Kazhdan, Thomas A. Funkhouser	The Princeton Shape Benchmark.	SMI	2004	DBLP DOI BibTeX RDF	geometric matching, shape database, benchmarks, shape retrieval
15	Carsten Carstensen, K. Jochimsen	Adaptive Finite Element Methods for Microstructures? Numerical Experiments for a 2-Well Benchmark.	Computing	2003	DBLP DOI BibTeX RDF	minimisation problem, relaxation, a posteriori error estimate, convexification, adaptive finite element method, microstructures
15	Klaus Havelund, Scott D. Stoller, Shmuel Ur	Benchmark and Framework for Encouraging Research on Multi-Threaded Testing Tools .	IPDPS	2003	DBLP DOI BibTeX RDF
15	Emin Erkan Korkmaz, Göktürk Üçoluk	Design and Usage of a New Benchmark Problem for Genetic Programming.	ISCIS	2003	DBLP DOI BibTeX RDF
15	Nobuhiko Tsuruoka, Motoyoshi Kurokawa, Ryutaro Himeno	Evaluation of High-Speed VPN Using CFD Benchmark.	ISHPC	2003	DBLP DOI BibTeX RDF
15	Michele Kirchner	A Benchmark for Testing the Evaluation Tools for Web Pages Accessibility.	WSE	2003	DBLP DOI BibTeX RDF
15	Byeong Kil Lee, Lizy Kurian John	NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors.	ICCD	2003	DBLP DOI BibTeX RDF
15	Albrecht Schmidt 0002, Florian Waas, Stefan Manegold, Martin L. Kersten	A Look Back on the XML Benchmark Project.	Intelligent Search on XML Data	2003	DBLP DOI BibTeX RDF
15	B. Chandrasekaran 0001, Pete Wyckoff, Dhabaleswar K. Panda 0001	MIBA: A Micro-Benchmark Suite for Evaluating InfiniBand Architecture Implementations.	Computer Performance Evaluation / TOOLS	2003	DBLP DOI BibTeX RDF
15	Michael D. Hutton, Jonathan Rose, Derek G. Corneil	Automatic generation of synthetic sequential benchmark circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
15	William Lawry, Christopher Wilson, Arthur B. Maccabe, Ron Brightwell	COMB: A Portable Benchmark Suite for Assessing MPI Overlap.	CLUSTER	2002	DBLP DOI BibTeX RDF
15	Albrecht Schmidt 0002, Florian Waas, Martin L. Kersten, Daniela Florescu, Michael J. Carey 0001, Ioana Manolescu, Ralph Busse	Why And How To Benchmark XML Databases.	SIGMOD Rec.	2001	DBLP DOI BibTeX RDF	XML
15	Jan Lindström, Tiina Niklander	Benchmark for Real-Time Database Systems for Telecommunications.	Databases in Telecommunications	2001	DBLP DOI BibTeX RDF
15	Charlie Daly, Jane Horgan, James F. Power, John Waldron	Platform independent dynamic Java virtual machine analysis: the Java Grande Forum Benchmark suite.	Java Grande	2001	DBLP DOI BibTeX RDF	Java Grande, Java, Java Virtual Machine