Search results for "circuit"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dysart, Xiaobo Sharon Hu, Andrew B. Kahng, Peter M. Kogge, Richard C. Murphy, Michael T. Niemier	Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions.	DAC	2004	DBLP DOI BibTeX RDF	quantum-dot cellular automata (QCA), computer aided design, circuit partitioning
19	Signe J. Silver, Janusz A. Brzozowski	True Concurrency in Models of Asynchronous Circuit Behavior.	Formal Methods Syst. Des.	2003	DBLP DOI BibTeX RDF	multiple-winner, single-winner, semi-modular, asynchronous, circuit, interleaving, true concurrency, delay-insensitive
19	Luís Guerra e Silva, João Marques-Silva 0001, Luís Miguel Silveira, Karem A. Sakallah	Satisfiability models and algorithms for circuit delay computation.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	circuit delay computation, timing analysis, Boolean satisfiability, delay modeling, false path
19	Syed M. Alam, Donald E. Troxel, Carl V. Thompson	A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits.	ISQED	2002	DBLP DOI BibTeX RDF	3D integrated circuit, 3D IC layout, inter-wafer via, reliability CAD tool, FPGA, performance analysis, reliability analysis
19	Martin Foltin, Brian Foutz, Sean Tyler	Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency.	DAC	2002	DBLP DOI BibTeX RDF	timing analysis, VLSI design, timing model, circuit optimization
19	Massimiliano Goldwurm, Beatrice Palano, Massimo Santini 0001	On the Circuit Complexity of Random Generation Problems for Regular and Context-Free Languages.	STACS	2001	DBLP DOI BibTeX RDF	Uniform random generation, ambiguous context-free languages, auxiliary pushdown automata, circuit complexity
19	K. Wayne Current	Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch.	ISMVL	2000	DBLP DOI BibTeX RDF	quaternary, memory, circuit, latch
19	Lifeng Wu, Jingkun Fang, Heting Yan, Ping Chen, Alvin I-Hsien Chen, Yoshifumi Okamoto, Chune-Sin Yeh, Zhihong Liu, Nobufusa Iwanishi, Norio Koike, Hirokazu Yonezawa, Yoshiyuki Kawakami	GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design.	ISQED	2000	DBLP DOI BibTeX RDF	Hot Carrier Effect, Gate level modeling, Gate level simulation, Circuit reliability simulation, VLSI
19	Tertulien Ndjountche, Rolf Unbehauen, Fa-Long Luo	A 1.5V VLSI Circuit for the Co-Channel Signal Separation.	IJCNN (4)	2000	DBLP DOI BibTeX RDF	channel deconvolution, signal separation, second-order statistic algorithm, analog VLSI circuit
19	Mayukh Bhattacharya, Pinaki Mazumder	Convergence Issues in Resonant Tunneling Diode Circuit Simulation.	VLSI Design	2000	DBLP DOI BibTeX RDF	negative differential resistance, convergence, SPICE, circuit simulation, resonant tunneling diode, Newton-Raphson
19	Pierre-Yves Calland, Alain Darte, Yves Robert	Circuit Retiming Applied to Decomposed Software Pipelining.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	circuit retiming, Software pipelining, list scheduling, modulo scheduling, cyclic scheduling
19	Vishal Sharma, Emmanouel A. Varvarigos	Circuit Switching with Input Queuing: An Analysis for the d-Dimensional Wraparound Mesh and the Hypercube.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	input queuing, wraparound meshes, connection delay, stability region, interconnection networks, hypercubes, Circuit switching, queuing delay
19	Hiroshi Yokoyama, Xiaoqing Wen, Hideo Tamamoto	Random Pattern Testable Design with Partial Circuit Duplication.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Partial circuit duplication, Random testing Built-in self test, Design for testability
19	Joseph G. Peters, Michel Syska	Circuit-Switched Broadcasting in Torus Networks.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	circuit-switched routing, Broadcasting, pipelining, tilings, torus networks
19	Yirng-An Chen, Randal E. Bryant	ACV: an arithmetic circuit verifier.	ICCAD	1996	DBLP DOI BibTeX RDF	Binary Moment Diagram, Formal Verification, Arithmetic circuit, BMD, Hierarchical Verification
19	João M. S. Alcântara, Carlo E. T. de Oliveira, Manuel L. Anido	A Novel Circuit Extraction Tool Based on X-Spans and Y-Spans.	EUROMICRO	1996	DBLP DOI BibTeX RDF	circuit extraction tool, X-Spans, Y-Spans, maximally-horizontal layout regions, contiguous vertical regions, VLSI, data structure
19	B. D. Cook, Soo-Young Lee	Fast exposure simulation for large circuit patterns in electron beam lithography.	ICIP	1995	DBLP DOI BibTeX RDF	electron beam lithography, proximity effect (lithography), fast exposure simulation, large circuit patterns, electron beam lithography, global exposure, local exposure, proximity effect, simulation
19	Bruno Codenotti, Peter Gemmell, Janos Simon	Average Circuit Depth and Average Communication Complexity.	ESA	1995	DBLP DOI BibTeX RDF	parallel time, lower bounds, communication complexity, circuit complexity
18	Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma	Leakage reduction, delay compensation using partition-based tunable body-biasing techniques.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	low-power design, process variations, leakage current, Body biasing
18	Gang Jin, Lei Wang 0011, Zhiying Wang	The Design of Asynchronous Microprocessor Based on Optimized NCL_X Design-Flow.	NAS	2009	DBLP DOI BibTeX RDF
18	Koustav Bhattacharya, Nagarajan Ranganathan	RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits.	VLSI Design	2009	DBLP DOI BibTeX RDF
18	Yung-Chih Chen, Chun-Yao Wang	An Implicit Approach to Minimizing Range-Equivalent Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
18	Soman Purushothaman	A simple 4 quadrant NMOS analog multiplier with input range equal to +/-VDD and very low THD.	EIT	2008	DBLP DOI BibTeX RDF
18	Yu Wang 0002, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie 0001	Temperature-aware NBTI modeling and the impact of input vector control on performance degradation.	DATE	2007	DBLP DOI BibTeX RDF
18	Ying Wei 0002, Alex Doboli	Library of structural analog cell macromodels for design of continuous-time reconfigurable Delta Sigma modulators.	ISCAS	2006	DBLP DOI BibTeX RDF
18	K. H. Abed, K. Y. Wong, Marian K. Kazimierczuk	CMOS zero cross-conduction low-power driver and power MOSFETs for integrated synchronous buck converter.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Le Jin, Hanqing Xing, Degang Chen 0001, Randall L. Geiger	A self-calibrated bandgap voltage reference with 0.5 ppm/°C temperature coefficient.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi	A design approach for radiation-hard digital electronics.	DAC	2006	DBLP DOI BibTeX RDF	radiation-hard, SEU
18	Ricardo Salem Zebulum, Adrian Stoica, Didier Keymeulen, Lukás Sekanina, Rajeshuni Ramesham, Xin Guo 0002	Evolvable Hardware System at Extreme Low Temperatures.	ICES	2005	DBLP DOI BibTeX RDF
18	Hiroyuki Yokoyama, Kenji Toda	FPGA-Based Content Protection System for Embedded Consumer Electronics.	RTCSA	2005	DBLP DOI BibTeX RDF
18	Joel Coburn, Srivaths Ravi 0001, Anand Raghunathan	Power emulation: a new paradigm for power estimation.	DAC	2005	DBLP DOI BibTeX RDF	simulation, FPGA, design, design methodologies, emulation, hardware acceleration, power estimation, register-transfer level, macromodels
18	Richard Ruzicka, Pavel Tupec	Formal Approach to Synthesis of a Test Controller.	ECBS	2004	DBLP DOI BibTeX RDF
18	Hideki Fukuda	Signed Digit CMOS (SD-CMOS) Logic Circuits with Static Operation.	ISMVL	2004	DBLP DOI BibTeX RDF
18	Kazuyuki Amano, Akira Maruoka	Some Properties of MODm Circuits Computing Simple Functions.	CIAC	2003	DBLP DOI BibTeX RDF	modular circuits, composite modulus, lower bounds, Fourier analysis, symmetric functions
18	Khanittha Kaewdang, Chalermpan Fongsamut, Wanlop Surakampontorn	A wide-band current-mode OTA-based analog multiplier-divider.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
18	Stephen A. Edwards	Making cyclic circuits acyclic.	DAC	2003	DBLP DOI BibTeX RDF	acyclic circuits, cyclic circuits, constructiveness, resynthesis
18	Svetlana N. Yanushkevich, Piotr Dziurzanski, Vlad P. Shmerko	The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 1: LAR Based Model.	ISMVL	2002	DBLP DOI BibTeX RDF	multiple-valued logic functions, linear word-level expressions, word-level decision diagrams
18	Afshin Abdollahi, Massoud Pedram, Farzan Fallah	Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1, 2.	ISLPED	2002	DBLP DOI BibTeX RDF
18	Rajesh Ramadoss, Michael L. Bushnell	Test Generation for Mixed-Signal Devices Using Signal Flow Graphs.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	analog test generation, mixed-signal test generation, back tracing, parametric faults, catastrophic faults
18	Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell	A Complete Characterization of Path Delay Faults through Stuck-at Faults.	VLSI Design	1999	DBLP DOI BibTeX RDF
18	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik	A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis.	DAC	1998	DBLP DOI BibTeX RDF
18	Ping-Chung Li, Ibrahim N. Hajj	Computer-aided redesign of VLSI circuits for hot-carrier reliability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
18	Alper Demir 0001, Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli	Time-domain non-Monte Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
18	Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah	Optimization of custom MOS circuits by transistor sizing.	ICCAD	1996	DBLP DOI BibTeX RDF	simulation, optimization, Circuits, gradients, transistor sizing
18	Irith Pomeranz, Sudhakar M. Reddy	On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF
18	S. C. Leung, Hon Fung Li	On the realizability and synthesis of delay-insensitive behaviors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
18	Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich	Design based analog testing by Characteristic Observation Inference.	ICCAD	1995	DBLP DOI BibTeX RDF
18	Alper Demir 0001, Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli	Time-domain non-Monte Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations.	ICCAD	1994	DBLP DOI BibTeX RDF
18	Abhijit Chatterjee	Concurrent error detection and fault-tolerance in linear analog circuits using continuous checksums.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
18	A. Salz, Mark Horowitz	IRSIM: An Incremental MOS Switch-Level Simulator.	DAC	1989	DBLP DOI BibTeX RDF
18	Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong Ken Yang	Device-circuit co-optimization for mixed-mode circuit design via geometric programming.	ICCAD	2007	DBLP DOI BibTeX RDF
18	Jian Ruan, Zhiying Wang 0003, Kui Dai, Yong Li 0006	Design and Test of Self-checking Asynchronous Control Circuit.	PATMOS	2007	DBLP DOI BibTeX RDF
18	Bart R. Zeydel, Vojin G. Oklobdzija	Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations.	PATMOS	2006	DBLP DOI BibTeX RDF
18	Rosario Mita, Gaetano Palumbo	Modeling of Propagation Delay of a First Order Circuit with a Ramp Input.	PATMOS	2002	DBLP DOI BibTeX RDF
18	Timót Hidvégi, Péter Szolgay	Short Circuit Detection on Printed Circuit Boards during the Manufacturing Process by Using an Analogic CNN Algorithm.	IEA/AIE	2001	DBLP DOI BibTeX RDF
18	Guohui Wang, David G. Andersen, Michael Kaminsky, Konstantina Papagiannaki, T. S. Eugene Ng, Michael Kozuch, Michael P. Ryan	c-Through: part-time optics in data centers.	SIGCOMM	2010	DBLP DOI BibTeX RDF	optical circuit switching, hybrid network, data center networking
18	Meng-Hui Wang, Yu-Kuo Chung, Wen-Tsai Sung	The Fault Diagnosis of Analog Circuits Based on Extension Theory.	ICIC (1)	2009	DBLP DOI BibTeX RDF	Extension theory (ET), Fault diagnosis, Analog circuit
18	Suraj Sindia, Virendra Singh, Vishwani D. Agrawal	Polynomial coefficient based DC testing of non-linear analog circuits.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	DC test, non-linear circuit test, polynomial, curve fitting, parametric faults
18	Jens Groth	Linear Algebra with Sub-linear Zero-Knowledge Arguments.	CRYPTO	2009	DBLP DOI BibTeX RDF	Sub-linear size zero-knowledge arguments, public-coin special honest verifier zero-knowledge, Pedersen commitments, linear algebra, circuit satisfiability
18	Nobuaki Okada, Michitaka Kameyama	Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells.	ISMVL	2008	DBLP DOI BibTeX RDF	Field-programmable VLSI, Multiple-valued source-coupled logic, Differential-Pair circuit, Bit-serial architecture
18	Cüneyt F. Bazlamaçci, Fatih Say	Minimum concave cost multicommodity network design.	Telecommun. Syst.	2007	DBLP DOI BibTeX RDF	Concave cost network design, Circuit switching and packet switching network design, Multicommodity flow problem
18	Houjun Liang, Wenjian Luo, Xufa Wang	Designing Polymorphic Circuits with Evolutionary Algorithm Based on Weighted Sum Method.	ICES	2007	DBLP DOI BibTeX RDF	Polymorphic Circuit, Weighted Sum, Evolutionary Algorithm
18	Yan Liu 0007, Liujun Chen, Jiawei Chen 0005, Fangfeng Zhang, Fukang Fang	Discussion on the Spike Train Recognition Mechanisms in Neural Circuits.	International Conference on Computational Science (4)	2007	DBLP DOI BibTeX RDF	inter-spike intervals, response delay time, neural circuit, spike train
18	Maria José Pereira Dantas, Leonardo da C. Brito, Paulo Henrique Portela de Carvalho	Multi-objective Memetic Algorithm Applied to the Automated Synthesis of Analog Circuits.	IBERAMIA-SBIA	2006	DBLP DOI BibTeX RDF	multi-objective memetic algorithm, 2D representation, analog circuit, building-blocks, automated synthesis
18	Sani R. Nassif	The impact of variability on power.	ISLPED	2004	DBLP DOI BibTeX RDF	power, variability, integrated circuit
18	Shantanu Dutt, Wenyong Deng	Cluster-aware iterative improvement techniques for partitioning large VLSI circuits.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	VLSI circuit partitioning, mincut, physical design/layout, Clusters, iterative-improvement
18	Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj	Estimation of state line statistics in sequential circuits.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	signal statistics, transition density, finite-state machine, sequential circuit, Power estimation, switching activity, signal probability
18	Charles E. Molnar, Ian W. Jones	Simple Circuits that Work for Complicated Reasons.	ASYNC	2000	DBLP DOI BibTeX RDF	MUTEX, Delay measurement technique, Latch control circuit, Charlie Box, Asynchronous, FIFO, Arbiter, Micropipeline
18	Shiyi Xu, Wei Cen	Forecasting the efficiency of test generation algorithms for digital circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms
18	Ecevit Yilmaz, Michael M. Green	Applying Globally Convergent Techniques to Conventional DC Operating Point Analyses.	Annual Simulation Symposium	1999	DBLP DOI BibTeX RDF	Circuit simulation, Nonlinear circuits
18	Joseph C. W. Pang, Mike W. T. Wong, Yim-Shu Lee	Design and Implementation of Strongly Code-Disjoint CMOS Built-in Intermediate Voltage Sensor for Totally Self-Checking Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Built-in intermediate voltage sensor, bridging fault, totally self-checking circuit
18	Lieven Vandenberghe, Stephen P. Boyd, Abbas El Gamal	Optimal wire and transistor sizing for circuits with non-tree topology.	ICCAD	1997	DBLP DOI BibTeX RDF	optimal circuit sizing, crosstalk, Elmore delay, clock distribution networks
18	Soon-Jyh Chang, Chung-Len Lee 0001, Jwu E. Chen	Functional test pattern generation for CMOS operational amplifier.	VTS	1997	DBLP DOI BibTeX RDF	functional test pattern generation, CMOS operational amplifier, programmable gain/loss mixed signal circuit, op amp testing, IC testing, CMOS analogue integrated circuits
18	J. van Spaandonk, Tom A. M. Kevenaar	Selecting measurements to test the functional behavior of analog circuits.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	automatic testing, analogue circuits, circuit testing
18	Shujian Zhang, Jon C. Muzio	Evaluating the safety of self-checking circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	fail-safe evaluation, TSC, Markov model, self-checking circuit
18	Fa-Long Luo, Rolf Unbehauen, Hongqin Xue	Continuous-time computation of the eigenvectors of a class of positive definite matrices.	PDP	1995	DBLP DOI BibTeX RDF	analogue computers, continuous-time computation, analog circuit approach, specialized analog computers, asynchronous parallel processing, continuous-time dynamics, high-speed computational capability, real-time applications fields, parallel processing, neural nets, matrix algebra, eigenvectors, special purpose computers, eigenvalues and eigenfunctions, neural chips, positive definite matrices
18	M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor	Compact test sets for industrial circuits.	VTS	1995	DBLP DOI BibTeX RDF	compact test sets, industrial circuits, binary logic elements, three-state elements, compaction oriented decision making, heuristics, logic testing, integrated circuit testing, automatic test pattern generation, combinational circuits, automatic testing, multivalued logic circuits, test patterns, bidirectionals, xor gates, or gates, test set size
18	C. P. Ravikumar, Hemant Joshi	HISCOAP: a hierarchical testability analysis tool.	VLSI Design	1995	DBLP DOI BibTeX RDF	HISCOAP, hierarchical testability analysis tool, SCOAP measure, gate-level netlist, SCOAP expression diagrams, VLSI, logic testing, controllability, controllability, sequential circuits, sequential circuits, combinational circuits, combinational circuits, observability, observability, circuit analysis computing, integrated logic circuits, VLSI circuits, functional modules, stuck at fault model
18	George Karakostas	General Pseudo-random Generators from Weaker Models of Computation.	ISAAC	2009	DBLP DOI BibTeX RDF	monotone circuit complexity, circuit complexity, Pseudo-random generators
18	Yu Yu, Jussipekka Leiwo, A. Benjamin Premkumar	Securely Utilizing External Computing Power.	ITCC (1)	2005	DBLP DOI BibTeX RDF	program encryption, circuit encryption, Boolean circuit, secure function evaluation, biometric identification
18	Michiko Inoue, Emil Gizdarski, Hideo Fujiwara	Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	internally balanced structure, test generation, sequential circuit, combinational circuit, balanced structure
18	Elena Dubrova, Jon C. Muzio	Easily Testable Multiple-Valued Logic Circuits Derived from Reed-Muller Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Reed-Muller circuit, easily testable circuit, stuck-at fault, Multiple-valued function
18	André Ivanov, Vikram Devdas	Catastrophic Short and Open Fault Detection in Bipolar CML Circuits: A Case Study.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	current mode logic (CML), CML circuit testing, bipolar circuit testing, catastrophic fault detection, defect-based testing
18	Chih-Wen Lu, Chauchin Su, Chung-Len Lee 0001, Jwu E. Chen	Is IDDQ testing not applicable for deep submicron VLSI in year 2011?	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	deep submicron VLSI, IDDQ current estimation, random process deviations, IDDQ distributions, VLSI, statistical analysis, integrated circuit testing, CMOS integrated circuits, leakage currents, IDDQ testing, statistical approach, standard deviation, input vectors, circuit size
18	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for SRAM cluster interconnect testing at board level.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
18	Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José L. Huertas	Testing mixed-signal cores: practical oscillation-based test in an analog macrocell.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	analog macrocell, mixed signal integrated circuit, OBT, mixed-signal macrocell, integrated circuit testing, mixed analogue-digital integrated circuits, oscillation-based test
18	Hsin-Po Wang 0002, Jon Turino	DFT and BIST techniques for the future.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	multimillion gate system-on-chip, multinational design, logic testing, built-in self test, design for testability, quality, BIST, economics, DFT, integrated circuit design, time to market, production testing, IC design, integrated circuit economics
18	Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang	A realistic fault model for flash memories.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	NAND circuits, faulty behavior classification, NAND-type flash memory, SPICE models, flash cell models, circuit-level faulty behavior simulation, testing, fault model, fault modeling, fault simulation, flash memories, flash memories, circuit analysis computing, SPICE, integrated memory circuits
18	Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian	TOF: a tool for test pattern generation optimization of an FPGA application oriented test.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	TOF tool, test pattern generation optimization, FPGA application oriented test, application-oriented test procedure, RAM-based FPGAs, AC nonredundant fault coverage, circuit netlist, TPG optimisation tool, field programmable gate arrays, logic testing, optimisation, integrated circuit testing, automatic test pattern generation, ATPG
18	Rong Lin, Kevin E. Kerr, André S. Botha	A Novel Approach for CMOS Parallel Counter Design.	EUROMICRO	1999	DBLP DOI BibTeX RDF	parallel counter and compressor, low power high speed CMOS circuit design, VLSI design, Arithmetic circuit, partial product reduction
18	Joe Kilian, Erez Petrank	An Efficient Noninteractive Zero-Knowledge Proof System for NP with General Assumptions.	J. Cryptol.	1998	DBLP DOI BibTeX RDF	Efficient proofs, Noninteractive zero knowledge, Efficient proofs, Noninteractive zero knowledge, Zero knowledge, Zero knowledge, Key words, One-way permutations, One-way permutations, Circuit satisfiability, Circuit satisfiability
18	Michel Renovell, Florence Azaïs, Yves Bertrand	Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits.	DATE	1998	DBLP DOI BibTeX RDF	VLSI, Test, Analog Circuit, Mixed Signal Circuit
18	Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya	Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic.	ASYNC	1998	DBLP DOI BibTeX RDF	pulse-driven logic, Josephson junction device, RSFQ device, pipeline, asynchronous circuit, delay-insensitive circuit
18	Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi	PRIMA: passive reduced-order interconnect macromodeling algorithm.	ICCAD	1997	DBLP DOI BibTeX RDF	MPVL, PRIMA, RLC interconnect circuits, block Arnoldi technique, driver-load models, guaranteed passivity, macromodel passivity, macromodel stability, passive reduced-order interconnect macromodeling algorithm, path tracing algorithm, reduced order N-port models, simulation, CAD, integrated circuit layout, frequency domain, circuit stability
18	Sharad Kapur, David E. Long	IES3: a fast integral equation solver for efficient 3-dimensional extraction.	ICCAD	1997	DBLP DOI BibTeX RDF	3-dimensional extraction, IES/sup 3/, arbitrary kernels, integral equation solver, integrated circuit structures, circuit CAD
18	Guowu Zheng, Qi-Jun Zhang, Michel S. Nakhla, Ramachandra Achar	An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data.	ICCAD	1996	DBLP DOI BibTeX RDF	complex frequency hopping algorithm, generalized stencil, linear subnetworks, measured data, moment-generation algorithm, moment-matching simulation, tabulated data, circuit analysis computing, circuit simulators, time-domain analysis
18	Peter Wohl, John A. Waicukauski, Matthew Graf	Testing "untestable" faults in three-state circuits.	VTS	1996	DBLP DOI BibTeX RDF	three-state circuits, complex CMOS designs, nonconventional circuits, test generation techniques, circuit particularities, fault diagnosis, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, test coverage, multivalued logic circuits, computer testing, CPU time, test vector generation, untestable faults, automatic learning
18	Masaru Sanada	A CAD-based approach to failure diagnosis of CMOS LSI's using abnormal Iddq.	VTS	1996	DBLP DOI BibTeX RDF	CAD-based failure diagnosis technology, CMOS LSI, abnormal Iddq phenomenon, physical damage detection, faulty blocks, failure point localization, Iddq test patterns, fault diagnosis, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, circuit CAD, large scale integration
18	Francesco Gregoretti, Claudio Passerone	Using a massively parallel architecture for integrated circuits testing.	PDP	1995	DBLP DOI BibTeX RDF	VLSI integrated circuit, low level image processing, image processing, parallel architectures, prototype, integrated circuit testing, integrated circuits testing, Integrated Circuits, massively parallel architecture, Scanning Electron Microscopy
18	Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey	A simple technique for locating gate-level faults in combinational circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	electron probe analysis, optical microscopy, gate-level faults, error sources, fault deduction, fault elimination, ISCAS'85 benchmark circuits, physical defect analysis, electron beam probing, light emission microscopy, computational complexity, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, digital simulation, circuit analysis computing, computation time, scanning electron microscopy, scanning electron microscopy, diagnostic resolution