Search results for "ATPG"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Sanjay Srinivasan, Gnanasekaran Swaminathan, James H. Aylor, M. Ray Mercer	Combinational circuit ATPG using binary decision diagrams.	VTS	1993	DBLP DOI BibTeX RDF
17	Haluk Konuk, Tracy Larrabee	Explorations of sequential ATPG using Boolean satisfiability.	VTS	1993	DBLP DOI BibTeX RDF
17	Maria José Aguado, Eduardo de la Torre, Miguel Miranda, Carlos A. López-Barrio	Distributed Implementation of an ATPG System Using Dynamic Fault Allocation.	ITC	1993	DBLP DOI BibTeX RDF
17	Eun Sei Park, M. Ray Mercer	Switch-Level ATPG Using Constraint-Guided Line Justification.	ITC	1993	DBLP DOI BibTeX RDF
17	Yves Bertrand, Frédéric Bancel, Michel Renovell	A DFT Technique to Improve ATPG Efficiency for Sequential Circuits.	VLSI Design	1993	DBLP DOI BibTeX RDF
17	Gopi Ganapathy, Jacob A. Abraham	Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor.	DAC	1993	DBLP DOI BibTeX RDF
17	Enrico Macii, Angelo Raffaele Meo	Techniques to increase sequential ATPG performance.	VTS	1992	DBLP DOI BibTeX RDF
17	Weiwei Mao, Michael D. Ciletti	Robustness Enhancement and Detection Threshold Reduction in ATPG for Gate Delay Faults.	ITC	1992	DBLP DOI BibTeX RDF
17	Wei-Cheng Her, Lin-Ming Jin, Yacoub M. El-Ziq	An ATPG Driver Selection Algorithm for Interconnect Test with Boundary Scan.	ITC	1992	DBLP DOI BibTeX RDF
17	Kwang-Ting Cheng, Hi-Keung Tony Ma	On the Over-Specification Problem in Sequential ATPG Algorithms.	DAC	1992	DBLP BibTeX RDF
17	Kwang-Ting Cheng	An ATPG-Based Approach to Sequential Logic Optimization.	ICCAD	1991	DBLP DOI BibTeX RDF
17	Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi	Fast Sequential ATPG Based on Implicit State Enumeration.	ITC	1991	DBLP DOI BibTeX RDF
17	Susheel J. Chandra, Tom Ferry, Tushar Gheewala, Kerry Pierce	ATPG Based on a Novel Grid-Addressable Latch Element.	DAC	1991	DBLP DOI BibTeX RDF
17	Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda	Model Checking and Graph Theory in Sequential ATPG.	CAV (DIMACS/AMS volume)	1990	DBLP DOI BibTeX RDF
17	Hyunwoo Cho, Gary D. Hachtel, Seh-Woong Jeong, Bernard Plessier, Eric M. Schwarz, Fabio Somenzi	Results on the Interface between Formal Verification and ATPG.	CAV (DIMACS/AMS volume)	1990	DBLP DOI BibTeX RDF
17	Hyunwoo Cho, Gary D. Hachtel, Seh-Woong Jeong, Bernard Plessier, Eric M. Schwarz, Fabio Somenzi	ATPG Aspects of FSM Verification.	ICCAD	1990	DBLP DOI BibTeX RDF
17	Udo Mahlstedt, Torsten Grüning, Cengiz Özcan, Wilfried Daehn	Contest: A Fast ATPG Tool for Very Large Combinatorial Circuits.	ICCAD	1990	DBLP DOI BibTeX RDF
17	Don Sterba, Andy Halliday, Don McClean	ATPG issues for board designs implementing boundary scan.	ITC	1990	DBLP DOI BibTeX RDF
17	C. Thomas Glover	Mixed-mode ATPG under input constraints.	ITC	1990	DBLP DOI BibTeX RDF
17	John A. Waicukauski, Paul A. Shupe, David Giramma, Arshad Matin	ATPG for ultra-large structured designs.	ITC	1990	DBLP DOI BibTeX RDF
17	Reily M. Jacoby, P. Moceyunas, Hyunwoo Cho, Gary D. Hachtel	New ATPG techniques for logic optimization.	ICCAD	1989	DBLP DOI BibTeX RDF
17	Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh	Compaction of ATPG-generated test sequences for sequential circuits.	ICCAD	1988	DBLP DOI BibTeX RDF
17	Antonio Lioy	Adaptative backtrace and dynamic partitioning enhance ATPG.	ICCD	1988	DBLP DOI BibTeX RDF
17	Tom E. Kirkland, M. Ray Mercer	A Topological Search Algorithm for ATPG.	DAC	1987	DBLP DOI BibTeX RDF
17	André Ivanov, Vinod K. Agarwal	Testability Measures : What Do They Do for ATPG ?	ITC	1986	DBLP BibTeX RDF
17	Tom E. Kirkland, M. Ray Mercer	A Two-Level Guidance Heuristic for ATPG.	FJCC	1986	DBLP BibTeX RDF
17	Franc Brglez, Philip Pownall, Robert Hum	Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing.	ITC	1984	DBLP BibTeX RDF
17	Alexander Miczo	The Sequential ATPG: A Theoretical Limit.	ITC	1983	DBLP BibTeX RDF
17	Mats Johansson	The GENESYS-Algorithm for ATPG without Fault Simulation.	ITC	1983	DBLP BibTeX RDF
17	Glenn A. Kramer	Employing Massive Parallelism in Digital ATPG Algorithms.	ITC	1983	DBLP BibTeX RDF
17	Harold Levin	ATPG and Simulation Systems : The State of the Art.	ITC	1982	DBLP BibTeX RDF
17	Samiha Mourad	An optimized ATPG.	DAC	1980	DBLP DOI BibTeX RDF
14	Hratch Mangassarian, Andreas G. Veneris, Marco Benedetti	Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	k-induction, sequential ATPG, SAT, QBF, design debugging, BMC
14	Stephan Eggersglüß, Rolf Drechsler	Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques.	ETS	2009	DBLP DOI BibTeX RDF	ATPG, SAT, Delay Test, Boolean Satisfiability, Dynamic Learning
14	Lei Fang 0002, Michael S. Hsiao	Bilateral Testing of Nano-scale Fault-Tolerant Circuits.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Bilateral fault model, Fault-tolerant, ATPG, Nanoelectronics
14	Sverre Wichlund, Frank Berntsen, Einar J. Aas	Scan Test Response Compaction Combined with Diagnosis Capabilities.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Scan compression, Diagnosis, ATPG, Yield, Design for test, ATE
14	Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski	Timing-Aware Multiple-Delay-Fault Diagnosis.	ISQED	2008	DBLP DOI BibTeX RDF	defect-diagnosis, diagnosis, ATPG, DFT, delay-testing
14	Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi 0001, Rubin A. Parekhji	A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips.	VTS	2008	DBLP DOI BibTeX RDF	Tester, ATPG, Estimation, ATE, Test Time, Test Data Volume
14	Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal	Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults.	VTS	2008	DBLP DOI BibTeX RDF	Diagnosis, ATPG, Fault Model, Fault Collapsing, Implication Graph
14	Hans G. Kerkhoff, Jarkko J. M. Huijts	Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications.	DELTA	2008	DBLP DOI BibTeX RDF	reconfigurable multi-processor-cores SoC, embedded system test, dependable SoCs, ATPG, Design-for-Test, self-repair
14	Donghwi Lee, Erik H. Volkerink, Intaik Park, Jeff Rearick	Empirical Validation of Yield Recovery Using Idle-Cycle Insertion.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	false failure, ATPG, delay testing, functional test, structural test, IR drop, yield loss
14	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001	Variation-Tolerant, Power-Safe Pattern Generation.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	low-power ATPG, process variation, IR drop, peak power, power profiling
14	Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu	Accelerating Soft Error Rate Testing Through Pattern Selection.	IOLTS	2007	DBLP DOI BibTeX RDF	soft error rate (SER), simulation, automatic test pattern generation (ATPG), Soft error
14	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001	Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.	VTS	2007	DBLP DOI BibTeX RDF	Low Power ATPG, Glitch Power, IR Drop, Peak Power, Power-profiling
14	Qingwei Wu, Michael S. Hsiao	A New Simulation-Based Property Checking Algorithm Based on Partitioned Alternative Search Space Traversal.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	verification, Automatic test pattern generation (ATPG), satisfiability, logic-simulation
14	Zhong-Zhen Wu, Shih-Chieh Chang	Multiple wire reconnections based on implication flow graph.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	global flow optimization (GFO), implication flow graph (IFG), mandatory assignment, multiple wire reconnection, redundant wire, Automatic test pattern generation (ATPG)
14	Amitava Majumdar 0002, Wei-Yu Chen, Jun Guo	Hold time validation on silicon and the relevance of hazards in timing analysis.	DAC	2006	DBLP DOI BibTeX RDF	hold time validation, ATPG, timing analysis, delay test
14	James Chien-Mo Li	Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Fault diagnosis, ATPG, scan chain
14	Mukul R. Prasad, Armin Biere, Aarti Gupta	A survey of recent advances in SAT-based formal verification.	Int. J. Softw. Tools Technol. Transf.	2005	DBLP DOI BibTeX RDF	Model checking, Verification, ATPG, SAT, QBF
14	Amardeep Singh, Lalit M. Bharadwaj, Singh Harpreet	DNA and quantum based algorithms for VLSI circuits testing.	Nat. Comput.	2005	DBLP DOI BibTeX RDF	DNA algorithm, genetic algorithms, neural networks, ATPG, quantum computation, quantum algorithm
14	Ilia Polian, Thomas Fiehn, Bernd Becker 0001, John P. Hayes	A Family of Logical Fault Models for Reversible Circuits.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	ATPG, fault models, quantum circuits, reversible circuits
14	Shahin Nazarian, Massoud Pedram, Emre Tuncer	An empirical study of crosstalk in VDSM technologies.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	automatic test pattern generation (ATPG) tool, crosstalk induced slowdown and speedup, transition time, static timing analysis (STA), skew
14	Stelios Neophytou, Maria K. Michael, Spyros Tragoudas	Test set enhancement for quality transition faults using function-based methods.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	high quality test, ATPG, delay test, critical paths, transition fault, test compaction
14	Ronald D. Blanton, John P. Hayes	On the properties of the input pattern fault model.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	fault testing, testing digital circuits, ATPG, fault models, faults, defects
14	Vladimir Hahanov, Raimund Ubar, Stanley Hyduke	Back-Traced Deductive-Parallel Fault Simulation for Digital Systems.	DSD	2003	DBLP DOI BibTeX RDF	back traced simulation, re-convergent fan-outs, fault analysis model, ATPG, parallel simulation, deductive
14	Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak	Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models.	DAC	2003	DBLP DOI BibTeX RDF	delay ATPG, delay fault diagnosis, statistical timing models
14	Xijiang Lin, Rob Thompson	Test generation for designs with multiple clocks.	DAC	2003	DBLP DOI BibTeX RDF	clock domain, ATPG, scan design
14	Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto	Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Testing of embedded systems, VHDL, ATPG, fault modeling, testability analysis
14	Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal	State and Fault Information for Compaction-Based Test Generation.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	sequential circuits, ATPG, test compaction
14	Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	TA-PSV - Timing Analysis for Partially Specified Vectors.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	timing analysis for partially specified vectors (TA-PSV), crosstalk test generation (ATPG), static timing analysis (STA), delay model
14	Amy Streich, Alex Kondratyev, Lief Sorensen	Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach.	ASYNC	2002	DBLP DOI BibTeX RDF	ATPG, asynchronous circuits, stuck-at faults, partial scan
14	Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy	A Method of Static Test Compaction Based on Don't Care Identification.	DELTA	2002	DBLP DOI BibTeX RDF	Coloring Problem, Don't Care Identification, ATPG, Static Test Compaction
14	Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian	A Discussion on Test Pattern Generation for FPGA - Implemented Circuits.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	FPGA, test, ATPG
14	Paulo F. Flores, Horácio C. Neto, João P. Marques Silva	An exact solution to the minimum size test pattern problem.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	propositional satisfiability (SAT), verification and test, built-in self-test (BIST), Automatic test pattern generation (ATPG), integer linear programming (ILP)
14	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	Testing the Local Interconnect Resources of SRAM-Based FPGA's.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	FPGA, VLSI, test, ATPG
14	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	FPGA, test, ATPG, iterative testing
14	Michael S. Hsiao, Srimat T. Chakradhar	Test Set Compaction Using Relaxed Subsequence Removal.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	static test set compaction, support sets, recurrence subsequence, ATPG
14	Michael S. Hsiao, Srimat T. Chakradhar	Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	static test set compaction, vector-reordering, fault coverage curve, partitioning, ATPG
14	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel	Dynamic state traversal for sequential circuit test generation.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	finite-state-machine traversal, simulation-based, genetic algorithms, testing, sequential circuits, automatic test pattern generation (ATPG)
14	Carsten Wegener, Michael Peter Kennedy	Incorporation of Hard-Fault-Coverage in Model-Based Testing of Mixed-Signal ICs.	DATE	2000	DBLP DOI BibTeX RDF	Defect and Tolerance-Oriented Test, ATPG and Fault Modeling, Analog and Mixed-Signal Test
14	Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken	DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits.	ASYNC	2000	DBLP DOI BibTeX RDF	DUDES, testing, ATPG, fault model, asynchronous circuit, stuck-at fault, fault collapsing
14	Yiorgos Makris, Jamison Collins, Alex Orailoglu	Fast hierarchical test path construction for DFT-free controller-datapath circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	fast hierarchical test path construction, DFT-free controller-datapath circuits, transparency based scheme, locally generated vectors, global design test, influence tables, valid control state sequences, module testing, fault coverage levels, vector counts, logic testing, test generation, automatic test pattern generation, ATPG, computational cost reduction
14	Shiyi Xu, Wei Cen	Forecasting the efficiency of test generation algorithms for digital circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms
14	Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian	TOF: a tool for test pattern generation optimization of an FPGA application oriented test.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	TOF tool, test pattern generation optimization, FPGA application oriented test, application-oriented test procedure, RAM-based FPGAs, AC nonredundant fault coverage, circuit netlist, TPG optimisation tool, field programmable gate arrays, logic testing, optimisation, integrated circuit testing, automatic test pattern generation, ATPG
14	Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara	Single-control testability of RTL data paths for BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
14	Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer	On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	DO-RE-ME technique, MPG-D model, defective part level prediction, benchmark circuit simulations, stuck-at fault detection tests, bridging surrogate detection, stuck-at fault coverage, predictor accuracy, industrial circuit, test pattern sequences, integrated circuit testing, automatic test pattern generation, ATPG, fault simulation, logic circuit, circuit simulation, integrated logic circuits, correlation coefficient
14	Patrick Girard 0001	Low Power Testing of VLSI Circuits: Problems and Solutions.	ISQED	2000	DBLP DOI BibTeX RDF	Test, Low Power, ATPG, BIST, Low Energy
14	Fabrizio Ferrandi, G. Fornara, Donatella Sciuto, G. Ferrara, Franco Fummi	Testability Alternatives Exploration through Functional Testing.	VTS	2000	DBLP DOI BibTeX RDF	High-level Testability Analysis, Behavioral Test Generation, VHDL, ATPG
14	Frank Poehl, Walter Anheier	Quality Determination for Gate Delay Fault Tests Considering Three-State Elements.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	ATPG, fault modelling, fault simulation
14	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	SRAM-Based FPGAs: Testing the Embedded RAM Modules.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	FPGA, test, ATPG, RAM, iterative testing
14	Chris Feige, Jan Ten Pierick, Clemens Wouters, Ronald J. W. T. Tangelder, Hans G. Kerkhoff	Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	bus-transfer, core reuse, test protocol, TIC, TTM, vector transfer, design-for-testability, ATPG, scan-test, AMBA
14	Xinghao Chen 0004, Thomas J. Snethen, Joe Swenton, Ron Walther	A Simplified Method for Testing the IBM Pipeline Partial-Scan Microprocessor.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	ATPG, DFT
14	M. H. Konijnenburg, Hans van der Linden, Ad J. van de Goor	Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	sequential circuit TPG, back-jumping, conflict-directed backtrack, three-state (tri-state) circuit TPG, ATPG, cost estimates
14	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	Minimizing the Number of Test Configurations for Different FPGA Families.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	FPGA, ATPG
14	Sam D. Huynh, Jinyan Zhang, Seongwon Kim, Giri Devarayanadurg, Mani Soma	Efficient Test Set Design for Analog and Mixed-Signal Circuits and Systems.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Efficient, ATPG, Digital, Analog, Mixed-Signal
14	Tsung-Chu Huang, Kuen-Jong Lee	An Input Control Technique for Power Reduction in Scan Circuits During Test Application.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	ATPG, VLSI testing, Power Minimization, Low-power Test, Full-scan
14	Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone	Charge Sharing Fault Detection for CMOS Domino Logic Circuits.	DFT	1999	DBLP DOI BibTeX RDF	charge sharing, cs-vulnerability, pseudo gate, ATPG, domino circuit
14	Zohair Sahraoui, Francky Catthoor, Paul Six, Hugo De Man	Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	supergate, prime-and-irredundant, ATPG, BDD
14	Li-C. Wang, Magdy S. Abadir, Jing Zeng	On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	assertion test generation, design error model, validation, ATPG, logic verification, symbolic trajectory evaluation
14	Xiao Sun 0002, Carmie Hull	Functional Verification Coverage vs. Physical Stuck-at Fault Coverage.	DFT	1998	DBLP DOI BibTeX RDF	functional property, stuck-at fault coverage, verification coverage, UIO, verification, validation, ATPG, FSM, signature analysis, test application time
14	V. Rajesh, Ajai Jain	Automatic Test Pattern Generation for Sequential Circuits Using Genetic Algorithms.	VLSI Design	1998	DBLP DOI BibTeX RDF	Genetic Algorithm, ATPG, Stuck-at-fault, Mutation, Crossover, Fitness Function, Objective Function
14	Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda	Guaranteeing Testability in Re-encoding for Low Power.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Initialization sequence, Genetic Algorithm, ATPG
14	Wim Verhaegen, Geert Van der Plas, Georges G. E. Gielen	Automated test pattern generation for analog integrated circuits.	VTS	1997	DBLP DOI BibTeX RDF	automated test pattern generation, generated fault list, optimal test signals, statistical fluctuations, statistical test criterion, ATPG algorithm, analogue integrated circuits, analog integrated circuits
14	Richard M. Chou, Kewal K. Saluja	Sequential Circuit Testing: From DFT to SFT.	VLSI Design	1997	DBLP DOI BibTeX RDF	design-for-testability methods, SFT techniques, large sequential circuits, logic testing, automatic test pattern generation, ATPG, synthesis-for-testability, sequential circuit testing, DFT techniques
14	Hisashi Kondo, Kwang-Ting Cheng	An Efficient Compact Test Generator for IDDQ Testing.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	Selective IDDQ, Pattern Compaction, Pseudo Stuck-at Fault, Essential Fault, Test, ATPG, Fault Model, Testability, IDDQ, Leakage Fault
14	Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao	Easily Testable Data Path Allocation Using Input/Output Registers.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	testable data path allocation, behavioral synthesis systems, input/output registers, interconnection allocation, module allocation, higher fault coverage, lower hardware overhead, improved testability, VLSI synthesis, optimization, algorithms, benchmarks, ATPG, DFT, register allocation, circuit optimisation, RTL design
14	Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel	Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.	VTS	1996	DBLP DOI BibTeX RDF	GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm
14	Claudio Costi, Micaela Serra, Donatella Sciuto	A new DFT methodology for sequential circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	design for testability, ATPG, fault coverage, scan design, test application time
14	Dimitrios Kagaris, Spyros Tragoudas	Avoiding linear dependencies in LFSR test pattern generators.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	ATPG, BIST, LFSR, characteristic polynomials, pseudo-random testing
14	Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck	Deterministic test generation for non-classical faults on the gate level.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST