|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 1073 occurrences of 407 keywords
|
|
|
Results
Found 939 publication records. Showing 939 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Sanjay Srinivasan, Gnanasekaran Swaminathan, James H. Aylor, M. Ray Mercer |
Combinational circuit ATPG using binary decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 11th IEEE VLSI Test Symposium (VTS'93), 6 Apr 1993-8 Apr 1993, Atlantic City, NJ, USA, pp. 251-258, 1993, IEEE Computer Society, 0-8186-3830-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Haluk Konuk, Tracy Larrabee |
Explorations of sequential ATPG using Boolean satisfiability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 11th IEEE VLSI Test Symposium (VTS'93), 6 Apr 1993-8 Apr 1993, Atlantic City, NJ, USA, pp. 85-90, 1993, IEEE Computer Society, 0-8186-3830-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Maria José Aguado, Eduardo de la Torre, Miguel Miranda, Carlos A. López-Barrio |
Distributed Implementation of an ATPG System Using Dynamic Fault Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics - Join Them, Baltimore, Maryland, USA, October 17-21, 1993, pp. 409-418, 1993, IEEE Computer Society, 0-7803-1430-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Eun Sei Park, M. Ray Mercer |
Switch-Level ATPG Using Constraint-Guided Line Justification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics - Join Them, Baltimore, Maryland, USA, October 17-21, 1993, pp. 616-625, 1993, IEEE Computer Society, 0-7803-1430-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Yves Bertrand, Frédéric Bancel, Michel Renovell |
A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 51-54, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Gopi Ganapathy, Jacob A. Abraham |
Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 30th Design Automation Conference. Dallas, Texas, USA, June 14-18, 1993., pp. 550-555, 1993, ACM Press, 0-89791-577-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Enrico Macii, Angelo Raffaele Meo |
Techniques to increase sequential ATPG performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 10th IEEE VLSI Test Symposium (VTS'92), 7-9 Apr 1992, Atlantic City, NJ, USA, pp. 257-262, 1992, IEEE Computer Society, 0-7803-0623-6. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
17 | Weiwei Mao, Michael D. Ciletti |
Robustness Enhancement and Detection Threshold Reduction in ATPG for Gate Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992, pp. 588-597, 1992, IEEE Computer Society, 0-7803-0760-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
17 | Wei-Cheng Her, Lin-Ming Jin, Yacoub M. El-Ziq |
An ATPG Driver Selection Algorithm for Interconnect Test with Boundary Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992, pp. 382-388, 1992, IEEE Computer Society, 0-7803-0760-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
17 | Kwang-Ting Cheng, Hi-Keung Tony Ma |
On the Over-Specification Problem in Sequential ATPG Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 29th Design Automation Conference, Anaheim, California, USA, June 8-12, 1992., pp. 16-21, 1992, IEEE Computer Society Press, 0-8186-2822-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
|
17 | Kwang-Ting Cheng |
An ATPG-Based Approach to Sequential Logic Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1991 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of Technical Papers, pp. 372-375, 1991, IEEE Computer Society, 0-8186-2157-5. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
17 | Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi |
Fast Sequential ATPG Based on Implicit State Enumeration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1991, Test: Faster, Better, Sooner, Nashville, TN, USA, October 26-30, 1991, pp. 67-74, 1991, IEEE Computer Society, 0-8186-9156-5. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
17 | Susheel J. Chandra, Tom Ferry, Tushar Gheewala, Kerry Pierce |
ATPG Based on a Novel Grid-Addressable Latch Element. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 28th Design Automation Conference, San Francisco, California, USA, June 17-21, 1991., pp. 282-286, 1991, ACM, 0-89791395-7. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
17 | Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda |
Model Checking and Graph Theory in Sequential ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV (DIMACS/AMS volume) ![In: Computer-Aided Verification, Proceedings of a DIMACS Workshop 1990, New Brunswick, New Jersey, USA, June 18-21, 1990, pp. 505-518, 1990, DIMACS/AMS, 978-0-8218-6594-1. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Hyunwoo Cho, Gary D. Hachtel, Seh-Woong Jeong, Bernard Plessier, Eric M. Schwarz, Fabio Somenzi |
Results on the Interface between Formal Verification and ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV (DIMACS/AMS volume) ![In: Computer-Aided Verification, Proceedings of a DIMACS Workshop 1990, New Brunswick, New Jersey, USA, June 18-21, 1990, pp. 615-628, 1990, DIMACS/AMS, 978-0-8218-6594-1. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Hyunwoo Cho, Gary D. Hachtel, Seh-Woong Jeong, Bernard Plessier, Eric M. Schwarz, Fabio Somenzi |
ATPG Aspects of FSM Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical Papers, pp. 134-137, 1990, IEEE Computer Society, 0-8186-2055-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Udo Mahlstedt, Torsten Grüning, Cengiz Özcan, Wilfried Daehn |
Contest: A Fast ATPG Tool for Very Large Combinatorial Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical Papers, pp. 222-225, 1990, IEEE Computer Society, 0-8186-2055-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Don Sterba, Andy Halliday, Don McClean |
ATPG issues for board designs implementing boundary scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1990, Washington, D.C., USA, September 10-14, 1990, pp. 243-251, 1990, IEEE Computer Society, 0-8186-9064-X. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | C. Thomas Glover |
Mixed-mode ATPG under input constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1990, Washington, D.C., USA, September 10-14, 1990, pp. 142-151, 1990, IEEE Computer Society, 0-8186-9064-X. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | John A. Waicukauski, Paul A. Shupe, David Giramma, Arshad Matin |
ATPG for ultra-large structured designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1990, Washington, D.C., USA, September 10-14, 1990, pp. 44-51, 1990, IEEE Computer Society, 0-8186-9064-X. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Reily M. Jacoby, P. Moceyunas, Hyunwoo Cho, Gary D. Hachtel |
New ATPG techniques for logic optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989, Santa Clara, CA, USA, November 5-9, 1989. Digest of Technical Papers, pp. 548-551, 1989, IEEE Computer Society, 0-8186-1986-4. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
17 | Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh |
Compaction of ATPG-generated test sequences for sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1988 IEEE International Conference on Computer-Aided Design, ICCAD 1988, Santa Clara, CA, USA, November 7-10, 1988. Digest of Technical Papers, pp. 382-385, 1988, IEEE Computer Society, 0-8186-0869-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
17 | Antonio Lioy |
Adaptative backtrace and dynamic partitioning enhance ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 62-65, 1988, IEEE, 0-8186-0872-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
17 | Tom E. Kirkland, M. Ray Mercer |
A Topological Search Algorithm for ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 502-508, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
17 | André Ivanov, Vinod K. Agarwal |
Testability Measures : What Do They Do for ATPG ? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1986, Washington, D.C., USA, September 1986, pp. 129-139, 1986, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP BibTeX RDF |
|
17 | Tom E. Kirkland, M. Ray Mercer |
A Two-Level Guidance Heuristic for ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FJCC ![In: Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, pp. 841-846, 1986, IEEE Computer Society, 0-8186-0743-2. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP BibTeX RDF |
|
17 | Franc Brglez, Philip Pownall, Robert Hum |
Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1984, Philadelphia, PA, USA, October 1984, pp. 705-712, 1984, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP BibTeX RDF |
|
17 | Alexander Miczo |
The Sequential ATPG: A Theoretical Limit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1983, Philadelphia, PA, USA, October 1983, pp. 143-149, 1983, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP BibTeX RDF |
|
17 | Mats Johansson |
The GENESYS-Algorithm for ATPG without Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1983, Philadelphia, PA, USA, October 1983, pp. 333-337, 1983, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP BibTeX RDF |
|
17 | Glenn A. Kramer |
Employing Massive Parallelism in Digital ATPG Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1983, Philadelphia, PA, USA, October 1983, pp. 108-114, 1983, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP BibTeX RDF |
|
17 | Harold Levin |
ATPG and Simulation Systems : The State of the Art. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1982, Philadelphia, PA, USA, November 1982, pp. 146, 1982, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP BibTeX RDF |
|
17 | Samiha Mourad |
An optimized ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 17th Design Automation Conference, DAC '80, Minneapolis, Minnesota, USA, June 23-25, 1980, pp. 381-385, 1980, ACM/IEEE, 0-89791-020-6. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
|
14 | Hratch Mangassarian, Andreas G. Veneris, Marco Benedetti |
Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 59(7), pp. 981-994, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
k-induction, sequential ATPG, SAT, QBF, design debugging, BMC |
14 | Stephan Eggersglüß, Rolf Drechsler |
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 14th IEEE European Test Symposium, ETS 2009, Sevilla, Spain, May 25-29, 2009, pp. 81-86, 2009, IEEE Computer Society, 978-0-7695-3703-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
ATPG, SAT, Delay Test, Boolean Satisfiability, Dynamic Learning |
14 | Lei Fang 0002, Michael S. Hsiao |
Bilateral Testing of Nano-scale Fault-Tolerant Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 285-296, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Bilateral fault model, Fault-tolerant, ATPG, Nanoelectronics |
14 | Sverre Wichlund, Frank Berntsen, Einar J. Aas |
Scan Test Response Compaction Combined with Diagnosis Capabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 235-246, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Scan compression, Diagnosis, ATPG, Yield, Design for test, ATE |
14 | Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski |
Timing-Aware Multiple-Delay-Fault Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 246-253, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
defect-diagnosis, diagnosis, ATPG, DFT, delay-testing |
14 | Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi 0001, Rubin A. Parekhji |
A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 53-58, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Tester, ATPG, Estimation, ATE, Test Time, Test Data Volume |
14 | Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal |
Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 329-335, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Diagnosis, ATPG, Fault Model, Fault Collapsing, Implication Graph |
14 | Hans G. Kerkhoff, Jarkko J. M. Huijts |
Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 38-44, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
reconfigurable multi-processor-cores SoC, embedded system test, dependable SoCs, ATPG, Design-for-Test, self-repair |
14 | Donghwi Lee, Erik H. Volkerink, Intaik Park, Jeff Rearick |
Empirical Validation of Yield Recovery Using Idle-Cycle Insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(4), pp. 362-372, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
false failure, ATPG, delay testing, functional test, structural test, IR drop, yield loss |
14 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001 |
Variation-Tolerant, Power-Safe Pattern Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(4), pp. 374-384, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
low-power ATPG, process variation, IR drop, peak power, power profiling |
14 | Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu |
Accelerating Soft Error Rate Testing Through Pattern Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 191-193, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
soft error rate (SER), simulation, automatic test pattern generation (ATPG), Soft error |
14 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001 |
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 167-172, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Low Power ATPG, Glitch Power, IR Drop, Peak Power, Power-profiling |
14 | Qingwei Wu, Michael S. Hsiao |
A New Simulation-Based Property Checking Algorithm Based on Partitioned Alternative Search Space Traversal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(11), pp. 1325-1334, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
verification, Automatic test pattern generation (ATPG), satisfiability, logic-simulation |
14 | Zhong-Zhen Wu, Shih-Chieh Chang |
Multiple wire reconnections based on implication flow graph. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(4), pp. 939-952, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
global flow optimization (GFO), implication flow graph (IFG), mandatory assignment, multiple wire reconnection, redundant wire, Automatic test pattern generation (ATPG) |
14 | Amitava Majumdar 0002, Wei-Yu Chen, Jun Guo |
Hold time validation on silicon and the relevance of hazards in timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 326-331, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
hold time validation, ATPG, timing analysis, delay test |
14 | James Chien-Mo Li |
Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(11), pp. 1467-1472, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Fault diagnosis, ATPG, scan chain |
14 | Mukul R. Prasad, Armin Biere, Aarti Gupta |
A survey of recent advances in SAT-based formal verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 7(2), pp. 156-173, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Model checking, Verification, ATPG, SAT, QBF |
14 | Amardeep Singh, Lalit M. Bharadwaj, Singh Harpreet |
DNA and quantum based algorithms for VLSI circuits testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Nat. Comput. ![In: Nat. Comput. 4(1), pp. 53-72, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
DNA algorithm, genetic algorithms, neural networks, ATPG, quantum computation, quantum algorithm |
14 | Ilia Polian, Thomas Fiehn, Bernd Becker 0001, John P. Hayes |
A Family of Logical Fault Models for Reversible Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 422-427, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ATPG, fault models, quantum circuits, reversible circuits |
14 | Shahin Nazarian, Massoud Pedram, Emre Tuncer |
An empirical study of crosstalk in VDSM technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 317-322, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
automatic test pattern generation (ATPG) tool, crosstalk induced slowdown and speedup, transition time, static timing analysis (STA), skew |
14 | Stelios Neophytou, Maria K. Michael, Spyros Tragoudas |
Test set enhancement for quality transition faults using function-based methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 182-187, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
high quality test, ATPG, delay test, critical paths, transition fault, test compaction |
14 | Ronald D. Blanton, John P. Hayes |
On the properties of the input pattern fault model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(1), pp. 108-124, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
fault testing, testing digital circuits, ATPG, fault models, faults, defects |
14 | Vladimir Hahanov, Raimund Ubar, Stanley Hyduke |
Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey, pp. 370-377, 2003, IEEE Computer Society, 0-7695-2003-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
back traced simulation, re-convergent fan-outs, fault analysis model, ATPG, parallel simulation, deductive |
14 | Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak |
Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 668-673, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
delay ATPG, delay fault diagnosis, statistical timing models |
14 | Xijiang Lin, Rob Thompson |
Test generation for designs with multiple clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 662-667, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
clock domain, ATPG, scan design |
14 | Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto |
Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(2), pp. 200-215, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Testing of embedded systems, VHDL, ATPG, fault modeling, testability analysis |
14 | Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal |
State and Fault Information for Compaction-Based Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(1), pp. 63-72, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
sequential circuits, ATPG, test compaction |
14 | Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer |
TA-PSV - Timing Analysis for Partially Specified Vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(1), pp. 73-88, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
timing analysis for partially specified vectors (TA-PSV), crosstalk test generation (ATPG), static timing analysis (STA), delay model |
14 | Amy Streich, Alex Kondratyev, Lief Sorensen |
Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, pp. 171-180, 2002, IEEE Computer Society, 0-7695-1540-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
ATPG, asynchronous circuits, stuck-at faults, partial scan |
14 | Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy |
A Method of Static Test Compaction Based on Don't Care Identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 392-395, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Coloring Problem, Don't Care Identification, ATPG, Static Test Compaction |
14 | Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian |
A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(3-4), pp. 283-290, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
FPGA, test, ATPG |
14 | Paulo F. Flores, Horácio C. Neto, João P. Marques Silva |
An exact solution to the minimum size test pattern problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(4), pp. 629-644, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
propositional satisfiability (SAT), verification and test, built-in self-test (BIST), Automatic test pattern generation (ATPG), integer linear programming (ILP) |
14 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
Testing the Local Interconnect Resources of SRAM-Based FPGA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 513-520, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA, VLSI, test, ATPG |
14 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(3), pp. 289-299, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA, test, ATPG, iterative testing |
14 | Michael S. Hsiao, Srimat T. Chakradhar |
Test Set Compaction Using Relaxed Subsequence Removal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(4), pp. 319-327, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
static test set compaction, support sets, recurrence subsequence, ATPG |
14 | Michael S. Hsiao, Srimat T. Chakradhar |
Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(4), pp. 329-338, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
static test set compaction, vector-reordering, fault coverage curve, partitioning, ATPG |
14 | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel |
Dynamic state traversal for sequential circuit test generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(3), pp. 548-565, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
finite-state-machine traversal, simulation-based, genetic algorithms, testing, sequential circuits, automatic test pattern generation (ATPG) |
14 | Carsten Wegener, Michael Peter Kennedy |
Incorporation of Hard-Fault-Coverage in Model-Based Testing of Mixed-Signal ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 765, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Defect and Tolerance-Oriented Test, ATPG and Fault Modeling, Analog and Mixed-Signal Test |
14 | Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken |
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 73-, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
DUDES, testing, ATPG, fault model, asynchronous circuit, stuck-at fault, fault collapsing |
14 | Yiorgos Makris, Jamison Collins, Alex Orailoglu |
Fast hierarchical test path construction for DFT-free controller-datapath circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 185-190, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fast hierarchical test path construction, DFT-free controller-datapath circuits, transparency based scheme, locally generated vectors, global design test, influence tables, valid control state sequences, module testing, fault coverage levels, vector counts, logic testing, test generation, automatic test pattern generation, ATPG, computational cost reduction |
14 | Shiyi Xu, Wei Cen |
Forecasting the efficiency of test generation algorithms for digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 179-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms |
14 | Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian |
TOF: a tool for test pattern generation optimization of an FPGA application oriented test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 323-328, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
TOF tool, test pattern generation optimization, FPGA application oriented test, application-oriented test procedure, RAM-based FPGAs, AC nonredundant fault coverage, circuit netlist, TPG optimisation tool, field programmable gate arrays, logic testing, optimisation, integrated circuit testing, automatic test pattern generation, ATPG |
14 | Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara |
Single-control testability of RTL data paths for BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 210-215, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test |
14 | Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer |
On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 151-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
DO-RE-ME technique, MPG-D model, defective part level prediction, benchmark circuit simulations, stuck-at fault detection tests, bridging surrogate detection, stuck-at fault coverage, predictor accuracy, industrial circuit, test pattern sequences, integrated circuit testing, automatic test pattern generation, ATPG, fault simulation, logic circuit, circuit simulation, integrated logic circuits, correlation coefficient |
14 | Patrick Girard 0001 |
Low Power Testing of VLSI Circuits: Problems and Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 173-180, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Test, Low Power, ATPG, BIST, Low Energy |
14 | Fabrizio Ferrandi, G. Fornara, Donatella Sciuto, G. Ferrara, Franco Fummi |
Testability Alternatives Exploration through Functional Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 423-430, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
High-level Testability Analysis, Behavioral Test Generation, VHDL, ATPG |
14 | Frank Poehl, Walter Anheier |
Quality Determination for Gate Delay Fault Tests Considering Three-State Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 49-55, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
ATPG, fault modelling, fault simulation |
14 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
SRAM-Based FPGAs: Testing the Embedded RAM Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 159-167, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
FPGA, test, ATPG, RAM, iterative testing |
14 | Chris Feige, Jan Ten Pierick, Clemens Wouters, Ronald J. W. T. Tangelder, Hans G. Kerkhoff |
Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 125-131, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
bus-transfer, core reuse, test protocol, TIC, TTM, vector transfer, design-for-testability, ATPG, scan-test, AMBA |
14 | Xinghao Chen 0004, Thomas J. Snethen, Joe Swenton, Ron Walther |
A Simplified Method for Testing the IBM Pipeline Partial-Scan Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 321-326, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
ATPG, DFT |
14 | M. H. Konijnenburg, Hans van der Linden, Ad J. van de Goor |
Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 185-191, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
sequential circuit TPG, back-jumping, conflict-directed backtrack, three-state (tri-state) circuit TPG, ATPG, cost estimates |
14 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
Minimizing the Number of Test Configurations for Different FPGA Families. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 363-368, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
FPGA, ATPG |
14 | Sam D. Huynh, Jinyan Zhang, Seongwon Kim, Giri Devarayanadurg, Mani Soma |
Efficient Test Set Design for Analog and Mixed-Signal Circuits and Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 239-, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Efficient, ATPG, Digital, Analog, Mixed-Signal |
14 | Tsung-Chu Huang, Kuen-Jong Lee |
An Input Control Technique for Power Reduction in Scan Circuits During Test Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 315-320, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
ATPG, VLSI testing, Power Minimization, Low-power Test, Full-scan |
14 | Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone |
Charge Sharing Fault Detection for CMOS Domino Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 77-85, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
charge sharing, cs-vulnerability, pseudo gate, ATPG, domino circuit |
14 | Zohair Sahraoui, Francky Catthoor, Paul Six, Hugo De Man |
Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(3), pp. 217-238, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
supergate, prime-and-irredundant, ATPG, BDD |
14 | Li-C. Wang, Magdy S. Abadir, Jing Zeng |
On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(4), pp. 524-532, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
assertion test generation, design error model, validation, ATPG, logic verification, symbolic trajectory evaluation |
14 | Xiao Sun 0002, Carmie Hull |
Functional Verification Coverage vs. Physical Stuck-at Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 108-116, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
functional property, stuck-at fault coverage, verification coverage, UIO, verification, validation, ATPG, FSM, signature analysis, test application time |
14 | V. Rajesh, Ajai Jain |
Automatic Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 270-273, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Genetic Algorithm, ATPG, Stuck-at-fault, Mutation, Crossover, Fitness Function, Objective Function |
14 | Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda |
Guaranteeing Testability in Re-encoding for Low Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 30-35, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Initialization sequence, Genetic Algorithm, ATPG |
14 | Wim Verhaegen, Geert Van der Plas, Georges G. E. Gielen |
Automated test pattern generation for analog integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 296-301, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
automated test pattern generation, generated fault list, optimal test signals, statistical fluctuations, statistical test criterion, ATPG algorithm, analogue integrated circuits, analog integrated circuits |
14 | Richard M. Chou, Kewal K. Saluja |
Sequential Circuit Testing: From DFT to SFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 274-278, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
design-for-testability methods, SFT techniques, large sequential circuits, logic testing, automatic test pattern generation, ATPG, synthesis-for-testability, sequential circuit testing, DFT techniques |
14 | Hisashi Kondo, Kwang-Ting Cheng |
An Efficient Compact Test Generator for IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 177-182, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Selective IDDQ, Pattern Compaction, Pseudo Stuck-at Fault, Essential Fault, Test, ATPG, Fault Model, Testability, IDDQ, Leakage Fault |
14 | Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao |
Easily Testable Data Path Allocation Using Input/Output Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 142-, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
testable data path allocation, behavioral synthesis systems, input/output registers, interconnection allocation, module allocation, higher fault coverage, lower hardware overhead, improved testability, VLSI synthesis, optimization, algorithms, benchmarks, ATPG, DFT, register allocation, circuit optimisation, RTL design |
14 | Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel |
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 456-462, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm |
14 | Claudio Costi, Micaela Serra, Donatella Sciuto |
A new DFT methodology for sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(3), pp. 223-240, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
design for testability, ATPG, fault coverage, scan design, test application time |
14 | Dimitrios Kagaris, Spyros Tragoudas |
Avoiding linear dependencies in LFSR test pattern generators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(2), pp. 229-241, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
ATPG, BIST, LFSR, characteristic polynomials, pseudo-random testing |
14 | Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck |
Deterministic test generation for non-classical faults on the gate level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 244-251, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST |
Displaying result #601 - #700 of 939 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ 10][ >>] |
|