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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2784 occurrences of 1319 keywords
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Results
Found 4097 publication records. Showing 4097 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
88 | Carlos Montemayor, Marie Sullivan, Jen-Tien Yen, Pete Wilson, Richard Evers, K. R. Kishore |
The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 196-203, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
PowerPC 603e microprocessor, low-power superscalar microprocessor, portable products, on-chip instruction, cache associativity, bus modes, 120 SPECint92, 105 SPECfp92, die size, software controllable power-down modes, power saving capability, 16 Kbyte, performance evaluation, performance, computer architecture, system design, power consumption, data cache, cache storage, microprocessor chips, frequency, system buses, portable computers, portable computers, transistors, 100 MHz |
76 | William Lloyd Bircher, Lizy K. John |
Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 158-168, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power sensing hardware, complete system power estimation, microprocessor performance event, microprocessor performance counter, online measurement, complete system power consumption, microprocessor power, on-chip performance event counter, system power consumption estimation, power model |
62 | Shlomi Dolev, Yinnon A. Haviv |
Self-Stabilizing Microprocessor: Analyzing and Overcoming Soft Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(4), pp. 385-399, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Self-stabilization, microprocessor, soft errors, single event upset |
57 | Junichi Hirase, Shinichi Yoshimura |
Faster processing for microprocessor functional ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 191-197, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
microprocessor functional ATPG, fault coverage improvement, short test pattern, processing speed increase, logic testing, integrated circuit testing, automatic test pattern generation, identification, test pattern generation, functional testing, microprocessor chips, instruction sets, instruction sets, microprocessor tests |
57 | Matthew Wilding, David A. Greve, Raymond J. Richards, David S. Hardin |
Formal Verification of Partition Management for the AAMP7G Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design and Verification of Microprocessor Systems for High-Assurance Applications ![In: Design and Verification of Microprocessor Systems for High-Assurance Applications., pp. 175-191, 2010, Springer, 978-1-4419-1538-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
56 | Hyun-Gyu Kim, Hyeong-Cheol Oh |
A DSP-Enhanced 32-Bit Embedded Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings, pp. 17-26, 2005, Springer, 3-540-30807-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
DSP-enhanced microprocessor, hardware address generator, register extension, embedded microprocessor, SIMD |
50 | Thomas D. Burd, Robert W. Brodersen |
Energy efficient CMOS microprocessor design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 288-297, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
energy efficient CMOS microprocessor design, portable electronics, battery weight, battery size, heat dissipation, computation modes, power analysis methodology, energy efficiency quantification, computer architecture, computer architectures, throughput, parallel machines, energy consumption, energy conservation, microprocessor chips, design principles, power dissipation, CMOS digital integrated circuits, integrated circuit modelling, cooling, figures of merit, desktop computers |
50 | Jaime H. Moreno |
Chip-level integration: the new frontier for microprocessor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30 - August 2, 2006, pp. 328, 2006, ACM, 1-59593-452-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
chip-level integration, microprocessor architecture |
50 | Ioannis Panagopoulos, Christos Pavlatos, George K. Papakonstantinou |
An Embedded Microprocessor for Intelligent Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 42(2), pp. 179-211, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
embedded systems, logic programming, microprocessor, intelligent control, RISC, declarative programs |
50 | Seokkee Kim, Soo-Ik Chae |
Implementation of a simple 8-bit microprocessor with reversible energy recovery logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005, pp. 421-426, 2005, ACM, 1-59593-019-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
clocked power generator (CPG), nMOS reversible energy recovery logic (nRERL), phase scheduling, reversibility breaking, microprocessor |
50 | Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng |
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 15-22, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing |
50 | S. M. Yuen, K. P. Lam |
A Knowledge-based Approach for Worst-case Timing Analysis of Microprocessor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPSAC ![In: 19th International Computer Software and Applications Conference (COMPSAC'95), August 9-11, 1995, Dallas, Texas, USA, pp. 32-39, 1995, IEEE Computer Society, 0-8186-7119-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Microprocessor Systems Diagnosis, Time Range Reasoning, Knowledge-based Systems |
49 | Oleg Maslennikow, Juri Shevtshenko, Anatoli Sergyienko |
Configurable Microprocessor Array for DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPAM ![In: Parallel Processing and Applied Mathematics, 5th International Conference, PPAM 2003, Czestochowa, Poland, September 7-10, 2003. Revised Papers, pp. 36-41, 2003, Springer, 3-540-21946-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
45 | David M. Russinoff |
A Mechanically Verified Commercial SRT Divider. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design and Verification of Microprocessor Systems for High-Assurance Applications ![In: Design and Verification of Microprocessor Systems for High-Assurance Applications., pp. 23-63, 2010, Springer, 978-1-4419-1538-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
45 | Anthony C. J. Fox, Michael J. C. Gordon, Magnus O. Myreen |
Specification and Verification of ARM Hardware and Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design and Verification of Microprocessor Systems for High-Assurance Applications ![In: Design and Verification of Microprocessor Systems for High-Assurance Applications., pp. 221-247, 2010, Springer, 978-1-4419-1538-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
45 | Konrad Slind, Guodong Li, Scott Owens |
Compiling Higher Order Logic by Proof. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design and Verification of Microprocessor Systems for High-Assurance Applications ![In: Design and Verification of Microprocessor Systems for High-Assurance Applications., pp. 193-220, 2010, Springer, 978-1-4419-1538-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
45 | Michael W. Whalen, David A. Greve, Lucas G. Wagner |
Model Checking Information Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design and Verification of Microprocessor Systems for High-Assurance Applications ![In: Design and Verification of Microprocessor Systems for High-Assurance Applications., pp. 381-428, 2010, Springer, 978-1-4419-1538-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
45 | Warren A. Hunt Jr., Sol Swords, Jared Davis, Anna Slobodová |
Use of Formal Verification at Centaur Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design and Verification of Microprocessor Systems for High-Assurance Applications ![In: Design and Verification of Microprocessor Systems for High-Assurance Applications., pp. 65-88, 2010, Springer, 978-1-4419-1538-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
45 | Raymond J. Richards |
Modeling and Security Analysis of a Commercial Real-Time Operating System Kernel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design and Verification of Microprocessor Systems for High-Assurance Applications ![In: Design and Verification of Microprocessor Systems for High-Assurance Applications., pp. 301-322, 2010, Springer, 978-1-4419-1538-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
45 | Torben Amtoft, John Hatcliff, Edwin Rodríguez, Robby, Jonathan Hoag, David A. Greve |
Specification and Checking of Software Contracts for Conditional Information Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design and Verification of Microprocessor Systems for High-Assurance Applications ![In: Design and Verification of Microprocessor Systems for High-Assurance Applications., pp. 341-379, 2010, Springer, 978-1-4419-1538-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
45 | Sally Browning, Philip Weaver |
Designing Tunable, Verifiable Cryptographic Hardware Using Cryptol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design and Verification of Microprocessor Systems for High-Assurance Applications ![In: Design and Verification of Microprocessor Systems for High-Assurance Applications., pp. 89-143, 2010, Springer, 978-1-4419-1538-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
45 | David A. Greve |
Information Security Modeling and Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design and Verification of Microprocessor Systems for High-Assurance Applications ![In: Design and Verification of Microprocessor Systems for High-Assurance Applications., pp. 249-299, 2010, Springer, 978-1-4419-1538-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
45 | Gerwin Klein, Thomas Sewell, Simon Winwood |
Refinement in the Formal Verification of the seL4 Microkernel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design and Verification of Microprocessor Systems for High-Assurance Applications ![In: Design and Verification of Microprocessor Systems for High-Assurance Applications., pp. 323-339, 2010, Springer, 978-1-4419-1538-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
45 | Panagiotis Manolios, Sudarshan K. Srinivasan |
Verifying Pipelines with BAT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design and Verification of Microprocessor Systems for High-Assurance Applications ![In: Design and Verification of Microprocessor Systems for High-Assurance Applications., pp. 145-174, 2010, Springer, 978-1-4419-1538-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
45 | Matt Kaufmann, J Strother Moore |
ACL2 and Its Applications to Digital System Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design and Verification of Microprocessor Systems for High-Assurance Applications ![In: Design and Verification of Microprocessor Systems for High-Assurance Applications., pp. 1-21, 2010, Springer, 978-1-4419-1538-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
44 | Murat Aydos, Tugrul Yanik, Çetin Kaya Koç |
An High-Speed ECC-based Wireless Authentication Protocol on an ARM Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSAC ![In: 16th Annual Computer Security Applications Conference (ACSAC 2000), 11-15 December 2000, New Orleans, Louisiana, USA, pp. 401-410, 2000, IEEE Computer Society, 0-7695-0859-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
high-speed ECC-based wireless authentication, ARM microprocessor, elliptic curve digital signature algorithm, ARM7TDMI processor, core processor, 80 MHz, 160 bit, mobile computing, elliptic curve cryptography, public key cryptography, software libraries, software library, authorisation, microprocessor chips, message authentication, portable computers, ECDSA, 32 bit, wireless applications |
44 | Shannon V. Morton, Sam S. Appleton, Michael J. Liebelt |
ECSTAC: a fast asynchronous microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 180-189, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous microprocessor, ECSTAC, two-phase communication, processor pipeline, register tagging, branch techniques, block simulation, caches, logic design, asynchronous circuits, microprocessor chips |
44 | Noriyuki Ito, Hideaki Katagiri, Ryoichi Yamashita, Hiroshi Ikeda, Hiroyuki Sugiyama, Hiroaki Komatsu, Yoshiyasu Tanamura, Akihiro Yoshitake, Kazuhiro Nonomura, Kinya Ishizaka, Hiroaki Adachi, Yutaka Mori, Yutaka Isoda, Yaroku Sugiyama |
Diagonal routing in high performance microprocessor design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 624-629, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
diagonal routing, manhattan routing, microprocessor |
44 | Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis 0001 |
Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 196-201, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
fault-tolerant microprocessor, soft errors, single event upsets, single event transients |
44 | Seokkee Kim, Soo-Ik Chae |
Complexity reduction in an nRERL microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 180-185, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
buffer skipping, clocked power generator (CPG), nMOS reversible energy recovery logic (nRERL), reversibility breaking, microprocessor, complexity reduction |
44 | Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem |
Coordinated transformations for high-level synthesis of high performance microprocessor blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 898-903, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
high-level synthesis, microprocessor design |
43 | Fu-Ching Yang, Wen-Kai Huang, Jing-Kun Zhong, Ing-Jer Huang |
Automatic Verification of External Interrupt Behaviors for Microprocessor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9), pp. 1670-1683, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Jesse Zhixi Fang |
A Generation Ahead of Microprocessor: Where Software Can Drive uArchitecture To? ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings, pp. 270, 2004, Springer, 3-540-23003-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Mehdi M. Mechaik |
Effects of Package Stackups on Microprocessor Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 475-, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | Philip Heng Wai Leong, P. K. Tsang, T. K. Lee |
A FPGA Based Forth Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 254-255, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
43 | Pramod V. Argade, David K. Charles, Craig Taylor |
A Technique for Monitoring Run-Time Dynamics of an Operating System and a Microprocessor Executing User Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VI Proceedings - Sixth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 4-7, 1994., pp. 122-131, 1994, ACM Press, 0-89791-660-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
43 | Tony Zingale |
Distributed processing with iAPX 186 microprocessor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS National Computer Conference ![In: American Federation of Information Processing Societies: 1982 National Computer Conference, 7-10 June, 1982, Houston, Texas, USA, pp. 59-65, 1982, AFIPS Press, 0-88283-035-X. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
38 | S. Srivastava, S. C. Bose, B. P. Mathur, Arti Noor, Raj Singh, A. S. Mandal, K. Prabhakaran, Arindam Karmakar, Chandra Shekhar 0001, Sudhir Kumar, Amit K. Agarwal |
Evolution of Architectural Concepts and Design Methods of Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 312-317, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Microprocessor Evolution, Synthesis, VHDL, Microprocessor Design |
38 | Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante |
A genetic algorithm-based system for generating test programs for microprocessor IP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTAI ![In: 12th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2000), 13-15 November 2000, Vancouver, BC, Canada, pp. 195-198, 2000, IEEE Computer Society, 0-7695-0909-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
industrial property, genetic algorithm based system, test program generation, microprocessor IP cores, digital systems design trend, design-and-reuse paradigm, intellectual property cores, encrypted gate-level netlist, testability problems, automatic approach, processor cores, fault coverage figures, random approach, genetic algorithms, genetic algorithms, microprocessor chips, automatic test software, test program, electronic engineering computing |
38 | Christian Piguet, Thierry Schneider, Jean-Marc Masgonty, Claude Arm, Serge Durand, M. Stegers |
Low-Power Embedded Microprocessor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 600-605, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
low-power embedded microprocessor design, low-power RISC-like architectures, gated clock techniques, power savings, microprocessor chips, CMOS technology, hierarchical memories, clock cycles |
38 | Hong Hao, Kanti Bhabuthmal |
Clock controller design in SuperSPARC II microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 124-129, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
SuperSPARC II, internal clock pulses, internal clock, free running mode, IEEE 1149.1 interface, microprocessor, clocks, microprocessor chips, clock controller |
38 | Charles P. Roth, Frank E. Levine, Edward H. Welbon |
Performance monitoring on the PowerPC 604 microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 212-215, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
PowerPC 604 microprocessor, multichip processors, Groupe Bull, performance evaluation, integrated circuit testing, workstations, performance monitoring, microprocessor chips, PCs, Microsoft, IBM, computer testing, Apple, Motorola |
38 | Steven Wallace, Nirav Dagli, Nader Bagherzadeh |
Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 96-101, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
centralized instruction window, four instructions per cycle, compact layout, full-custom design, computer architecture, microprocessor chips, superscalar architecture, superscalar microprocessor, out-of-order issue, 100 MHz |
38 | Veljko M. Milutinovic, David A. Fura, Walter A. Helbig |
Pipeline Design Tradeoffs in a 32-bit Gallium Arsenide Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 40(11), pp. 1214-1224, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
instruction pipeline design, single-chip GaAs microprocessor, application-related parameters, pipelined memory pipeline, III-V semiconductors, performance evaluation, microprocessor chips, instruction sets, 32 bit, GaAs, gallium arsenide |
38 | Veljko M. Milutinovic, Mark Bettinger, Walter A. Helbig |
Multiplier/Shifter Design Tradeoffs in a 32-bit Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(6), pp. 874-881, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
full barrel shifter, large register file, GaAs microprocessor, logic design, microprocessors, microprocessor chips, design tradeoffs, 32 bits, single chip, bit-serial multiplier |
38 | Robert P. Roesser |
Two-Dimensional Microprocessor Pipelines for Image Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 27(2), pp. 144-156, 1978. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
two-dimensional pipeline, Digital image processor, microprocessor array, microprocessor pipeline, space-domain processing, state-space processing, parallel processors, microcomputers |
38 | Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak |
Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 357-365, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
clock faults, testing, microprocessor, Clock distribution network |
37 | Rupesh S. Shelar, Marek Patyra |
Impact of local interconnects on timing and power in a high performance microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 145-152, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
CAD, delay, interconnects, power, microprocessor |
37 | Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi |
Delay defect screening for a 2.16GHz SPARC64 microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 342-347, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
delay defect, microprocessor, screening, at-speed |
37 | Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante |
Automatic generation of test sets for SBST of microprocessor IP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 74-79, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FPGA, hardware accelerator, automatic test generation, pipelined architectures, microprocessor test, test programs |
37 | Mohammad H. Tehranipour, Mehrdad Nourani |
Signal Integrity Loss in SoC's Interconnects: A Diagnosis Approach Using Embedded Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 1093-1102, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Embedded Microprocessor, Integrity Loss, System-on-Chip, Diagnosis, Test Pattern Generation, Signal Integrity, Interconnect Testing, Noise Detection |
37 | Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia |
"Timing closure by design, " a high frequency microprocessor design methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 712-717, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
chip integration, dynamic circuits0, CAD, methodology, microprocessor, timing analysis, PLA, timing closure |
37 | John Matthews, Byron Cook, John Launchbury |
Microprocessor Specification in Hawk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCL ![In: Proceedings of the 1998 International Conference on Computer Languages, ICCL 1998, Chicago, IL, USA, May 14-16, 1998, pp. 90-101, 1998, IEEE Computer Society, 0-8186-8454-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Microprocessor Verification, Domain-Specific Language, Functional Language, Hardware Verification |
37 | Michael Nicolaidis |
Efficient UBIST implementation for microprocessor sequencing parts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(3), pp. 295-312, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
strongly code disjoint checkers, signature analyser, UBIST, microprocessor sequencing part, BIST, LFSR, self-checking circuits, totally self-checking circuits |
37 | Fu-Ching Yang, Jing-Kun Zhong, Ing-Jer Huang |
Verifying external interrupts of embedded microprocessor in SoC with on-chip bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 372-377, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Masatoshi Shima 0001 |
The Birth, Evolution and Future of the Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Fifth International Conference on Computer and Information Technology (CIT 2005), 21-23 September 2005, Shanghai, China, pp. 2, 2005, IEEE Computer Society, 0-7695-2432-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Seokkee Kim, Jun-Ho Kwon, Soo-Ik Chae |
An 8-b nRERL microprocessor for ultra-low-energy applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 27-28, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
37 | Bartomeu Alorda, Ivan de Paúl, Jaume Segura 0001, T. Miller |
On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 87-91, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Bill Huston |
Practical CMOS microprocessor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS National Computer Conference ![In: American Federation of Information Processing Societies: 1982 National Computer Conference, 7-10 June, 1982, Houston, Texas, USA, pp. 19-28, 1982, AFIPS Press, 0-88283-035-X. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
32 | Tom Thomas, Brian W. Anthony |
Area, Performance, and Yield Implications of Redundancy in On-Chip Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 291-292, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
cache, redundancy, microprocessor, yield, SRAM, yield enhancement, microprocessor design, embedded SRAM |
32 | Sam S. Appleton, Shannon V. Morton, Michael J. Liebelt |
Two-Phase Asynchronous Pipeline Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 12-23, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
two-phase asynchronous pipeline control, bounded-delay model, prototype microprocessor, microprocessor chips |
32 | James O. Bondi, Ashwini K. Nanda, Simonjit Dutta |
Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 14-23, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
branch target buffer technology, deep pipelines, misprediction recovery cache integration, performance loss, residual misprediction penalty, superscalar pipeline, microprocessor chips, microprocessor designs, CISC, multiple instructions |
32 | Thomas W. Lynch, Ashraf Ahmed, Michael J. Schulte, Thomas K. Callaway, Robert Tisdale |
The K5 transcendental functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 163-, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
K5 transcendental functions, AMD x86 compatible superscalar microprocessor, multi-level development cycle, design schedule, table-driven reductions, multiprecision arithmetic operations, encoding, polynomials, floating point arithmetic, microprocessor chips, approximation theory, polynomial approximations |
32 | Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington |
A high performance bus and cache controller for PowerPC multiprocessing systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 204-211, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor |
32 | Louis Monier, Ramsey W. Haddad, Jeremy Dion |
Recursive layout generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 172-184, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
BiCMOS digital integrated circuits, recursive layout generation, layout directives, netlist description, hand-drawn layout, synthesized layout, overall layout, dense VLSI, VLSI, logic CAD, circuit layout CAD, microprocessor chips, microprocessor chips, VLSI chips, seamless integration |
32 | Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell |
Automated verification of temporal properties specified as state machines in VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 100-105, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
automated verification methodology, correctness specifications, Viper microprocessor, Mealy FSM, compatible states, formal specification, formal verification, high level synthesis, finite state machines, VHDL, sequential circuits, state machines, hardware description languages, microprocessor chips, synchronous sequential circuit, temporal properties, liveness properties |
32 | O. A. Petlin, Stephen B. Furber |
Scan testing of micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 296-303, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines |
31 | Pinkesh J. Shah, Yoni Aizik, Muhammad K. Mhameed, Gila Kamhi |
Challenges and methodologies for efficient power budgeting across the die. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 317-322, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
simulation, performance, energy-efficient, management, power, microprocessor, budget |
31 | Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero |
Efficient Techniques for Automatic Verification-Oriented Test Set Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 34(1), pp. 93-109, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
test-set optimization, evolutionary algorithm, Validation, microprocessor |
31 | Ed Grochowski, David Ayers, Vivek Tiwari |
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), Boston, Massachusettes, USA, February 2-6, 2002, pp. 7-16, 2002, IEEE Computer Society, 0-7695-1525-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Power delivery, supply voltage drop, simulation, microprocessor, inductive noise, di/dt |
31 | Victor S. Foster |
MIDAS: A MID-level language for microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Annual Conference (2) ![In: Proceedings 1978 ACM Annual Conference, Washington, DC, USA, December 4-6, 1978, Volume II, pp. 526-529, 1978, ACM, 978-0-89791-000-2. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
Microprocessor languages, Mid-level languages, Languages, Microprocessors, MIDAS |
31 | Charles F. Webb |
IBM z10: The Next-Generation Mainframe Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 28(2), pp. 19-29, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
high-frequency design, decimal floating-point, reliability, pipeline, microprocessor, branch prediction, accelerators, symmetric multiprocessor (SMP), mainframe, Hot Chips 19 |
31 | Da Wang, Yu Hu 0001, Huawei Li 0001, Xiaowei Li 0001 |
Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 23(6), pp. 1037-1046, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
microprocessor design-for-testability, built-in self-test, test generation, at-speed testing |
31 | Desta Tadesse, R. Iris Bahar, Joel Grodstein |
Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 339-344, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Microprocessor Diagnosis, Pass/Fail Region, Maximum Likelihood Estimation, Silicon Debug |
31 | Fu-Ching Yang, Ing-Jer Huang |
An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 902-907, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
16 bit, ARM7 software tools, THUMB instruction set microprocessor, short-precision computing |
31 | Wei Li, Daniel Blakely, Scott Van Sooy, Keven Dunn, David Kidd, Robert Rogenmoser, Dian Zhou |
LVS verification across multiple power domains for a quad-core microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(2), pp. 490-500, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
LVS, multi-core microprocessor, physical verification |
31 | Koichi Sato, Brian L. Evans, J. K. Aggarwal |
Designing an Embedded Video Processing Camera Using a 16-bit Microprocessor for a Surveillance System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 42(1), pp. 57-68, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
temporal spatio-velocity transform, embedded system, interaction, tracking, video, recognition, microprocessor, surveillance, DRAM, velocity, Ptolemy |
31 | Eric S. Fetzer |
Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(6), pp. 476-483, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
dual core, Itanium microprocessor, Montecito, adaptive circuits, cache safe technology, active clock deskew, process variation, power measurement |
31 | Yue Luo, Lizy Kurian John, Lieven Eeckhout |
SMA: A Self-Monitored Adaptive Cache Warm-Up Scheme for Microprocessor Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 33(5), pp. 561-581, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Microprocessor simulation, cache warm-up, simulation time reduction, sampling |
31 | Luca Benini, Francesco Menichelli, Mauro Olivieri |
A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(4), pp. 467-482, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Microprocessor/microcomputer applications, low-power design, code compression |
31 | Fadi Busaba, Timothy J. Slegel, Steven R. Carlough, Christopher A. Krygowski, John G. Rell |
The design of the fixed point unit for the z990 microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 364-367, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
superscalar FXU, microprocessor |
31 | Mark D. Aagaard, Byron Cook, Nancy A. Day, Robert B. Jones |
A framework for superscalar microprocessor correctness statements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 4(3), pp. 298-312, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Microprocessor correctness, Commuting diagrams, Formal verification, Pipelines |
31 | Nguyen Quang Trung, Artur Kokoszka, Krystyna Siekierska, Adam Pawlak, Dariusz Obrebski, Norbert Lugowski |
Organization of a Microprocessor Design Process Using Internet-Based Interoperable Workflows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 405-410, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Virtual Component, Interoperability, Workflow, VHDL, IP, Microprocessor, Microcontroller, Collaborative Engineering |
31 | Yuichiro Takamizawa, Kouhei Nadehara, Max Boegli, Masao Ikekawa, Ichiro Kuroda |
MPEG-2 AAC 5.1-Channel Decoder Software for a Low-Power Embedded RISC Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 29(3), pp. 247-254, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
microprocessor, decoder, MPEG, AAC |
31 | Stanislav Polonsky, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Pia N. Sanda |
Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 125-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
imaging circuit analysis, IBM G6 microprocessor, non-invasive backside timing, Picosecond Imaging Circuit Analysis, waveform extraction, integrated circuit testing, timing analysis, race condition, circuit switching, integrated memory circuits, hazards and race conditions, L1 cache |
31 | Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina |
At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 3-8, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
delay testing, at-speed testing, microprocessor testing |
31 | Erik A. McShane, Krishna Shenai, Leon Alkalai, E. Kolawa, Victor Boyadzhyan, Brent R. Blaes, Wai-Chi Fang |
Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 332-333, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Mixed-signal VLSI, VLSI circuits process for mixed-signal VLSI in a die size measuring 2.2 mm x 2.2 mm, low-power, microprocessor, RF |
31 | Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda |
EXFI: a low-cost fault injection system for embedded microprocessor-based boards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(4), pp. 626-634, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
microprocessor systems, software-implemented fault injection, trace exception mode, fault injection, fault coverage |
31 | Marc Renaudin, Pascal Vivet, Frédéric Robin |
ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 22-31, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design |
31 | Kåre Tais Christensen, Peter Jensen, Peter Korger, Jens Sparsø |
The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 108-, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Asynchronous circuits and systems, low-power, microprocessor design |
31 | Daniel Audet, Steve Masson, Yvon Savaria |
Reducing Fault Sensitivity of Microprocessor-Based Systems by Modifying Workload Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 241-, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
bit flip, fault-tolerance, memory, microprocessor, fault injection, software fault-tolerance, transient faults |
31 | Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura |
Design Methodology of a 200MHz Superscalar Microprocessor: SH-4. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 246-249, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
verification, timing, design methodology, microprocessor |
31 | Bogdan Kasztenny, Eugeniusz Rosolowski |
A digital protective relay as a real-time microprocessor system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 1997 Workshop on Engineering of Computer-Based Systems (ECBS '97), March 24-28, 1997, Monterey, CA, USA, pp. 460-466, 1997, IEEE Computer Society, 0-8186-7889-5. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
power system protection, digital protective relay, real-time microprocessor system, protection system, hardware, power system, software structures |
31 | D. L. Grundy, M. Bozic, John V. Hatfield |
Development of an Analogue Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 420-424, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Analogue array, Analogue microprocessor, Analogue signal processing, Programmable Logarithmic, Instruction set |
31 | Po-Ching Hsu, Sying-Jyan Wang |
Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 56-61, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multiple-board system, bus emulator, wiring interconnect, testing, fault detection, diagnosis, microprocessor, printed circuit board, printed circuit testing, hierarchical testing |
31 | Suresh Rajgopal |
Challenges in Low Power Microprocessor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 329-330, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
power benchmarks, latch power, idle power, active power, clock enabling, max power, thermal power, transient power, low-power, clock gating, microprocessor design, di/dt |
31 | Alexander Dalal, Lavi Lev, Sundari Mitra |
Design of an efficient power distribution network for the UltraSPARC-I microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 118-123, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
computer power supplies, UltraSPARC-I, simulation method, exact layout locations, excessive voltage drop, floorplanning constraints, power interconnections, reduced time-to-market, circuit analysis computing, circuit layout CAD, microprocessor chips, electromigration, CAD tools, power distribution network |
31 | Francis Y. L. Chin, Francis Wu |
A microprocessor-based optical character recognition check reader. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: Third International Conference on Document Analysis and Recognition, ICDAR 1995, August 14 - 15, 1995, Montreal, Canada. Volume II, pp. 982-985, 1995, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
microprocessor-based optical character recognition check reader, Magnetic Ink Character Recognition, check reader, lens system, colour image, hardware limitations, optical character recognition, floating point arithmetics, recognition algorithm, software solution |
31 | Lei Wang 0011, Hongyi Lu, Kui Dai, Zhiying Wang 0003 |
TengYue-1TengYue: In Chinese means jump over.: A High Performance Embedded SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings, pp. 126-136, 2004, Springer, 3-540-23003-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Julio Faura, C. Horton, B. Krah, Joan Cabestany, M. A. Aguirre, Josep Maria Insenser |
A new field programmable system-on-a-chip for mixed signal integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 610, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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