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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 18369 occurrences of 5291 keywords
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Results
Found 50014 publication records. Showing 49999 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
78 | Ananta K. Majhi, Vishwani D. Agrawal |
Tutorial: Delay Fault Models and Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 364-369, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
delay fault models, gate delay model, line delay model, path delay model, segment delay model, transition model, Delay test |
60 | W. Melody Moh, Yu-Jen Chien, Irene Zhang, Teng-Sheng Moh |
Delay performance evaluation of high speed protocols for multimedia communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the 4th International Conference on Computer Communications and Networks (ICCCN '95), September 20-23, 1995, Las Vegas, Nevada, USA, pp. 352, 1995, IEEE Computer Society, 0-8186-7180-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
delay performance evaluation, high speed protocols, delay fairness, worst-case delay performance, distributed queue dual bus, CRMA, cyclic reservation multiple access, DQMA, distributed queue multiple access, FDQ, fair distributed queue, heavy network load, reservation-based protocols, throughput, multimedia communication, multimedia communication, multimedia traffic, quality of service requirements, DQDB, access delay, message delay, heterogeneous traffic |
55 | Subhrajit Bhattacharya, Sujit Dey, Franc Brglez |
Fast true delay estimation during high level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9), pp. 1088-1105, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
52 | Mukund Sivaraman, Andrzej J. Strojwas |
Diagnosis of parametric path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 412-417, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
parametric path delay faults, chip failure, fabrication process parameter values, path sensitization mechanism, path delay conditions, ISCAS'89 benchmark circuits, path segment, circuit failure, fault diagnosis, logic testing, logic testing, delays, probability, probability, statistical analysis, statistical analysis, integrated circuit testing, failure analysis, diagnosability, delay fault testing, IC testing, production testing |
49 | Ioannis Papapanagiotou, John S. Vardakas, Georgios S. Paschos, Michael D. Logothetis, Stavros A. Kotsopoulos |
Performance evaluation of IEEE 802.11e based on ON-OFF traffic model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MobiMedia ![In: Proceedings of the 3rd International Conference on Mobile Multimedia Communications, MobiMedia 2007, Nafpaktos, Greece, August 27-29, 2007, pp. 17, 2007, ICST, 978-963-06-2670-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
MAC delay, QoS, IEEE 802.11e, end-to-end delay, queuing delay |
49 | Eun Sei Park, M. Ray Mercer, Thomas W. Williams |
The Total Delay Fault Model and Statistical Delay Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(6), pp. 688-698, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
delay fault model, delay fault coverage, statistical delay fault coverage, defect level model, logic testing, delay testing, delay faults |
46 | Youxin Gao, D. F. Wong 0001 |
Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 512-516, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | Branka Medved Rogina, Bozidar Vojnovic |
Metastability evaluation method by propagation delay distribution measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 40-44, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
propagation delay distribution measurement, edge-triggered flip-flops, input signals time relationship, output signal timing characteristics, analytical representation, propagation delay density distribution function, fault events, integrated propagation delay density distribution function, flip-flop normal propagation delay, resolution time constant, automatic data acquisition, complex architecture microsystems, MTBF, latch devices, custom CMOS, VLSI, VLSI, fault diagnosis, logic testing, delays, logic design, asynchronous circuits, flip-flops, data acquisition, failure analysis, reliability analysis, graphical representation, metastability, PLD, asynchronous logic, integrated circuit reliability, statistical measurement |
43 | Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges |
Statistical estimation of delay fault detectabilities and fault grading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(1), pp. 47-60, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
transition delay and path delay faults, statistical delay fault analysis, fault detectabilities, fault coverage, random patterns |
43 | Andrew B. Kahng, Kei Masuko, Sudhakar Muddu |
Analytical delay models for VLSI interconnects under ramp input. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 30-36, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
SPICE-computed delay, VLSI routing topologies layout, analytical delay models, arbitrary interconnect trees, interconnect transfer function, performance-driven synthesis, ramp input, source-sink delays, VLSI, Elmore delay, interconnect delays, VLSI interconnects, RLC interconnections |
42 | Huawei Li 0001, Zhongcheng Li, Yinghua Min |
Reduction of Number of Paths to be Tested in Delay Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 477-485, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
linearly independent, analytical delay model, delay testing, path sensitization |
42 | Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu |
Generation of tenacious tests for small gate delay faults in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 332-338, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
tenacious tests, small gate delay faults, single gate delay fault, ISCAS'85 benchmark circuits, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuits, fault coverage |
42 | Rodica Branzei, Giulio Ferrari, Vito Fragnelli, Stef Tijs |
Two Approaches to the Problem of Sharing Delay Costs in Joint Projects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 109(1-4), pp. 359-374, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
activity graph, delay cost, taxation, serial cost sharing, bankruptcy |
41 | William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
Delay fault coverage, test set size, and performance trade-offs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1), pp. 32-44, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
40 | Mukund Sivaraman, Andrzej J. Strojwas |
Timing analysis based on primitive path delay fault identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 182-189, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
primitive path delay faults, correlated delay, floating mode, timing analysis, timing verification, false path, path delay fault testing |
40 | Sudhakar M. Reddy, Peter Maxwell |
Fundamentals of Small-Delay Defect Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ![In: Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., pp. 1-22, 2014, CRC Press, 978-1-439-82941-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
40 | Sandeep Kumar Goel, Krishnendu Chakrabarty |
Circuit Topology-Based Test Pattern Generation for Small-Delay Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ![In: Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., pp. 161-184, 2014, CRC Press, 978-1-439-82941-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
40 | Sandeep Kumar Goel, Narendra Devta-Prasanna |
Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ![In: Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., pp. 147-160, 2014, CRC Press, 978-1-439-82941-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
40 | Narendra Devta-Prasanna, Sandeep Kumar Goel |
Small-Delay Defect Coverage Metrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ![In: Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., pp. 185-210, 2014, CRC Press, 978-1-439-82941-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
40 | Nisar Ahmed, Mohammad Tehranipoor |
Faster-than-at-Speed Test for Screening Small-Delay Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ![In: Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., pp. 73-94, 2014, CRC Press, 978-1-439-82941-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
40 | Abdelmajid Khelil, Faisal Karim Shaikh, Azad Ali, Neeraj Suri, Christian Reinl |
Delay Tolerant Monitoring of Mobility-Assisted WSN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Delay Tolerant Networks ![In: Delay Tolerant Networks - Protocols and Applications., pp. 189-222, 2011, CRC Press, 978-1-4398-1108-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
40 | Angela Sara Cacciapuoti, Marcello Caleffi, Luigi Paura |
Mobile Peer-to-Peer Systems over Delay Tolerant Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Delay Tolerant Networks ![In: Delay Tolerant Networks - Protocols and Applications., pp. 159-188, 2011, CRC Press, 978-1-4398-1108-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
40 | Corrado Moiso, Antonio Manzalini, Francesco De Pellegrini, Iacopo Carreras, Daniele Miorandi, Athanasios V. Vasilakos |
R-P2P: a Data-Centric Middleware for Delay Tolerant Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Delay Tolerant Networks ![In: Delay Tolerant Networks - Protocols and Applications., pp. 127-158, 2011, CRC Press, 978-1-4398-1108-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
40 | Maode Ma, Chao Lu, Hui Li 0006 |
Delay Tolerant Networking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Delay Tolerant Networks ![In: Delay Tolerant Networks - Protocols and Applications., pp. 1-30, 2011, CRC Press, 978-1-4398-1108-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
40 | Ruhai Wang, Xuan Wu, Tiaotiao Wang, Tarik Taleb |
Delay Tolerant Networking (DTN) Protocols for Space Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Delay Tolerant Networks ![In: Delay Tolerant Networks - Protocols and Applications., pp. 261-282, 2011, CRC Press, 978-1-4398-1108-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
40 | Seung Keun Yoon, Zygmunt J. Raas |
Energy-Aware Routing Protocol for Delay Tolerant Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Delay Tolerant Networks ![In: Delay Tolerant Networks - Protocols and Applications., pp. 69-100, 2011, CRC Press, 978-1-4398-1108-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
40 | Kevin R. Fall, Cecilia Mascolo, Jörg Ott, Lars C. Wolf |
09071 Executive Summary - Delay and Disruption-Tolerant Networking (DTN) II. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Delay and Disruption-Tolerant Networking (DTN) II ![In: Delay and Disruption-Tolerant Networking (DTN) II, 08.02. - 11.02.2009, 2009, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, Germany. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
40 | Kevin R. Fall, Cecilia Mascolo, Jörg Ott, Lars C. Wolf |
09071 Abstracts Collection - Delay and Disruption-Tolerant Networking (DTN) II. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Delay and Disruption-Tolerant Networking (DTN) II ![In: Delay and Disruption-Tolerant Networking (DTN) II, 08.02. - 11.02.2009, 2009, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, Germany. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
40 | Baris Bozkurt, Thierry Dutoit, Laurent Couvreur |
Spectral Analysis of Speech Signals Using Chirp Group Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WNSP ![In: Progress in Nonlinear Speech Processing, Workshop on Nonlinear Speech Processing, WNSP 2005, Heraklion, Crete, Greece, September 20-23, 2005, pp. 41-57, 2005, Springer, 978-3-540-71503-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Phase processing, chirp group delay, group delay, zzt, ASR feature extraction |
40 | Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng |
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 15-22, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing |
40 | Shibin Song, Joseph Kee-Yin Ng, Bihai Tang |
Statistical Delay Analysis with Self-Similar Input Traffic in ATM Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 6th International Workshop on Real-Time Computing and Applications Symposium (RTCSA '99), 13-16 December 1999, Hong Kong, China, pp. 133-140, 1999, IEEE Computer Society, 0-7695-0306-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Real-Time ATM Networks, Statistical Delay Analysis, Efficient Delay Computation, Performance Evaluation, Self-similar Traffic |
40 | Mukund Sivaraman, Andrzej J. Strojwas |
A diagnosability metric for parametric path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 316-323, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
diagnosability metric, parametric path delay faults, test vector pairs, chip failure, fabrication process parameter variations, diagnosis framework, ISCAS'89 benchmark circuits, VLSI, fault diagnosis, logic testing, delays, timing, integrated circuit testing, failure analysis, diagnosability, delay fault testing, test set |
40 | Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal |
On test coverage of path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 418-421, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
two-pass test generation method, falling transition, line delay test, longest sensitizable path, decreasing length, redundant stuck-at fault, computational complexity, fault diagnosis, logic testing, delays, redundancy, combinational circuits, fault simulation, circuit analysis computing, test coverage, path delay faults, benchmark circuits, coverage metric, combinational logic circuits, longest paths |
39 | Abbas El Gamal, James P. Mammen, Balaji Prabhakar, Devavrat Shah |
Optimal throughput-delay scaling in wireless networks: part I: the fluid model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 52(6), pp. 2568-2592, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
throughput scaling, throughput-delay tradeoff, wireless networks, queueing theory, random walks, scaling laws |
39 | Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu |
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 422-427, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
39 | Masoud Sharif, Babak Hassibi |
A delay analysis for opportunistic transmission in fading broadcast channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOCOM ![In: INFOCOM 2005. 24th Annual Joint Conference of the IEEE Computer and Communications Societies, 13-17 March 2005, Miami, FL, USA, pp. 2720-2730, 2005, IEEE, 0-7803-8968-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Matthew K. H. Leung, John C. S. Lui, David K. Y. Yau |
Characterization and Performance Evaluation for Proportional Delay Differentiated Services. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNP ![In: Eighth Annual International Conference on Network Protocols, ICNP 2000, 14-17 November, 2000, Osaka, Japan, pp. 295-304, 2000, IEEE Computer Society, 0-7695-0921-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
proportional delay differentiated services, Internet differentiated services, traffic classes, tariff rate, time-dependent priority scheduling, proportional delay model, delay ratios, scheduling parameters, efficient control algorithm, relative waiting time, performance evaluation, performance evaluation, Internet, delays, telecommunication traffic, waiting times, telecommunication services, ISP, feasible regions, average waiting time, service classes |
38 | Seiichiro Tani, Mitsuo Teramoto, Tomoo Fukazawa, Kazuyoshi Matsuhiro |
Efficient Path Selection for Delay Testing Based on Path Clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(1-2), pp. 75-85, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
clustering, delay testing, delay fault, path delay |
38 | Irith Pomeranz, Sudhakar M. Reddy |
Functional test generation for delay faults in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(2), pp. 231-248, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
function-robust tests, functional delay fault model, delay faults, path delay faults, robust tests |
38 | Matthew Andrews, Antonio Fernández 0001, Mor Harchol-Balter, Frank Thomson Leighton, Lisa Zhang |
General Dynamic Routing with Per-Packet Delay Guarantees of O(distance + 1 / session rate). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 38th Annual Symposium on Foundations of Computer Science, FOCS '97, Miami Beach, Florida, USA, October 19-22, 1997, pp. 294-302, 1997, IEEE Computer Society, 0-8186-8197-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
per-packet delay, queue buildup, scheduling, packet-switching, communication networks, dynamic routing, telecommunication networks, performance guarantees, delay bounds, bursty traffic, packet delay, arbitrary topology |
38 | Aiguo Lu, Erik L. Dagless, Jonathan M. Saul |
DART: delay and routability driven technology mapping for LUT based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 409-414, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
DART, delay driven technology mapping, LUT based FPGAs, two-phased approach, routability directed delay-optimal mapping, stochastic routability analysis, delay-optimal mapping, field programmable gate arrays, delays, logic design, programmable logic arrays, table lookup, minimisation of switching nets |
38 | Wuudiann Ke, Premachandran R. Menon |
Multifault testability of delay-testable circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 400-409, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
delay-testable circuits, multifault testability, path-delay-fault testability, multiple stuck-at-fault testability, multilevel combinational circuits, robust path-delay-fault test set, logic testing, delays, combinational circuits, multivalued logic circuits |
38 | Mukund Sivaraman, Andrzej J. Strojwas |
Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 494-501, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
fabrication process, coverage, delay testing, delay fault, path sensitization |
38 | Syed Sohel Hussain, Yih-Chyun Jenq |
Analysis and Optimization of a Banyan-Based ATM Switch by Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: Proceedings 21st Conference on Local Computer Networks, Minneapolis, Minnesota, USA, October 13-16, 1996, pp. 268-277, 1996, IEEE Computer Society, 0-8186-7617-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Banyan based ATM switch, switch optimization, switch analysis, delay variance, performanc analysis, uniform traffic, three-state model, nonblocking first stage, packet blocking, enhanced priority scheme, single buffer Banyan network, double buffer switching element, delay sensitive voice packet, asynchronous transfer mode, asynchronous transfer mode, delay, throughput, bandwidth, simulation results, voice traffic, data traffic |
37 | Yu-Sheng Huang, Chih-wen Hsueh |
Minimizing the maximum end-to-end delay on tree structure using the distributed pinwheel model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 7th International Workshop on Real-Time Computing and Applications Symposium (RTCSA 2000), 12-14 December 2000, Cheju Island, South Korea, pp. 127-134, 2000, IEEE Computer Society, 0-7695-0930-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
maximum end-to-end delay minimisation, distributed pinwheel model, end-to-end timing requirements, tight maximum delay bound, quality of service, Internet, computational complexity, timing, computer networks, heuristic algorithm, processor scheduling, timing constraints, simulation result, distributed real-time systems, tree structure, heuristic programming, NP-hard problems, linear-time algorithm, pipeline structure |
37 | S. Cremoux, Christophe Fagot, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch |
A new test pattern generation method for delay fault testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 296-301, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
test pattern generation method, directed random generation technique, random test vectors, test sequence length, delay fault coverage, learning (artificial intelligence), VLSI, logic testing, delays, built-in self test, integrated circuit testing, BIST, automatic testing, delay fault testing, digital integrated circuits, learning tool, high speed circuits |
37 | Yinghua Min, Zhuxing Zhao, Zhongcheng Li |
An Analytical Delay Model Based on Boolean Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 162-165, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
waveform polynomial, transition delay, floating delay, sensitization, Boolean process |
37 | Colin J. Ihrig, Gerold Joseph Dhanabalan, Alex K. Jones |
A low-power CMOS thyristor based delay element with programmability extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 297-302, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
delay element, thyristor, low power |
36 | Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001 |
A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2934-2943, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal |
Test Generation for Path Delay Faults Using Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(3), pp. 434-447, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Boolean algebraic test generation, redundant delay faults, robust delay tests, scan testing of delay faults, binary decision diagrams, delay faults |
36 | Daniel C. McCrackin |
Eliminating Interlocks in Deeply Pipelined Processors by Delay Enforced Multistreaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 40(10), pp. 1125-1132, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
deeply pipelined processors, delay enforced multistreaming, data dependency problem, jump problem, interdispatch delay, stream dispatching algorithms, modified fixed delay, encoded delay with fixed minimum, pipeline processing, processor architecture, interleaving, interlocks |
35 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Safe Delay Optimization for Physical Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 628-633, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
safe delay optimization, SafeResynth, safe resynthesis technique, immediately-measurable delay improvement, circuit timing, route length, physical synthesis, electronic design automation, route congestion, circuit delay |
35 | Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu |
An Application-Independent Delay Testing Methodology for Island-Style FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 478-486, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
segment delay fault, FPGA, delay testing, path delay fault |
35 | Maria K. Michael, Spyros Tragoudas |
ATPG tools for delay faults at the functional level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(1), pp. 33-57, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
functional-level testing, path delay fault simulation (coverage), testing digital circuits, Automatic test pattern generation, Binary Decision Diagrams, delay testing, Boolean Satisfiability, path delay fault testing |
35 | Wen Ching Wu, Chung-Len Lee 0001, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir |
Oscillation Ring Delay Test for High Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 147-155, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
oscillation ring testing, sensitized path, robust path dealy fault, hazard-free path delay fault, multiple reconvergent fanout, flunk lines, stuck at fault, delay fault testing, gate delay fault |
35 | Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukherjee |
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 97-104, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
delay defects, delay fault modeling, delay testing, critical paths, statistical timing analysis |
35 | Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das |
Delay Fault Coverage Enhancement Using Variable Observation Times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(2), pp. 131-146, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
statistical delay fault coverage, delay test observation times, delay fault testing |
35 | Joseph Kee-Yin Ng, Shibin Song, Wei Zhao 0001 |
Integrated delay analysis of regulated ATM switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 18th IEEE Real-Time Systems Symposium (RTSS '97), December 3-5, 1997, San Francisco, CA, USA, pp. 285-296, 1997, IEEE Computer Society, 0-8186-8268-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
integrated delay analysis, regulated ATM switch, worst case delay, hard real-time connection, real-time connection traffic, arrival functions, priority driven scheduling, FIFO scheduling, admission probability, cell delay estimation, performance, asynchronous transfer mode, deadline, simulation experiments, service functions, piecewise linear functions |
35 | Chung-Ping Chen, Hai Zhou 0001, D. F. Wong 0001 |
Optimal non-uniform wire-sizing under the Elmore delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 38-43, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Elmore delay model, IBM RS/6000 workstation, NWSA-db, NWSA-md, NWSA-wd algorithm, general routing trees, maximum sink delay, minimization objectives, optimal nonuniform wire sizing, routing-tree problem, sink-delay bounds, total area, total weighted sink-delays, wire-sizing formula, circuit analysis computing, Lagrangian relaxation |
35 | Jacob Savir |
Generator choices for delay test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 214-221, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
BIST based delay test, generator choices, delay test vector generator, nonscan designs, transition test, skewed-load delay test, shift dependency, digital logic circuits, performance, VLSI, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, automatic testing, flexibility, linear feedback shift register, cost, shift registers, scan designs, boundary scan testing, test vectors, timing requirement, pseudo-random test |
35 | Hagit Attiya, David Hay |
The inherent queuing delay of parallel packet switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2004: Proceedings of the Sixteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, June 27-30, 2004, Barcelona, Spain, pp. 269-270, 2004, ACM, 1-58113-840-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
leaky-bucket traffic, load balancing, packet switching, clos networks, queuing delay, delay jitter, inverse multiplexing |
35 | Moonsoo Kang, Chansu Yu |
Job-Based Queue Delay Modeling in a Space-Shared Hypercube. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: Proceedings of the 1999 International Conference on Parallel Processing Workshops, ICPPW 1999, Wakamatsu, Japan, September 21-24, 1999, pp. 313-318, 1999, IEEE Computer Society, 0-7695-0353-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
topological delay, processor allocation, space sharing, queue delay, Hypercube computer |
35 | Angela Krstic, Kwang-Ting Cheng |
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(1), pp. 43-54, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
resynthesis for testability, timing defects, delay testing, path delay faults, VLSI testing |
35 | Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga |
A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 320-325, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
marginal delay, test generation, combinational circuit, gate delay faults |
35 | Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram |
Timing-based delay test for screening small delay defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 320-325, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
test generation, delay testing |
35 | Taieb Znati, Rami G. Melhem |
Node delay assignment strategies to support end-to-end delay requirements in heterogeneous networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 12(5), pp. 879-892, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
quality of service (QoS), packet scheduling, end-to-end delay |
35 | Duncan M. Hank Walker |
K Longest Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ![In: Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., pp. 23-48, 2014, CRC Press, 978-1-439-82941-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
35 | Mahmut Yilmaz |
Output Deviations-Based SDD Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ![In: Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., pp. 119-146, 2014, CRC Press, 978-1-439-82941-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
35 | Ke Peng, Mahmut Yilmaz, Mohammad Tehranipoor |
Circuit Path Grading Considering Layout, Process Variations, and Cross Talk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ![In: Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., pp. 95-118, 2014, CRC Press, 978-1-439-82941-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
35 | Mark Kassab, Benoit Nadeau-Dostie, Xijiang Lin |
Timing-Aware ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ![In: Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., pp. 49-72, 2014, CRC Press, 978-1-439-82941-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
35 | Haojin Zhu, Xiaodong Lin 0001, Rongxing Lu, Yanfei Fan, Xuemin Shen |
A Routing-Compatible Credit-Based Incentive Scheme for DTNs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Delay Tolerant Networks ![In: Delay Tolerant Networks - Protocols and Applications., pp. 101-126, 2011, CRC Press, 978-1-4398-1108-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
35 | Thrasyvoulos Spyropoulos, Rao Naveed Bin Rais, Thierry Turletti, Katia Obraczka, Athanasios V. Vasilakos |
DTN Routing: Taxonomy and Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Delay Tolerant Networks ![In: Delay Tolerant Networks - Protocols and Applications., pp. 31-68, 2011, CRC Press, 978-1-4398-1108-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
35 | Carlo Caini, Rosario Firrincieli |
DTN and Satellite Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Delay Tolerant Networks ![In: Delay Tolerant Networks - Protocols and Applications., pp. 283-318, 2011, CRC Press, 978-1-4398-1108-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
35 | Shabbir Ahmed 0002, Salil S. Kanhere |
Message Dissemination in Vehicular Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Delay Tolerant Networks ![In: Delay Tolerant Networks - Protocols and Applications., pp. 223-260, 2011, CRC Press, 978-1-4398-1108-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
35 | Kevin R. Fall, Cecilia Mascolo, Jörg Ott, Lars C. Wolf (eds.) |
Delay and Disruption-Tolerant Networking (DTN) II, 08.02. - 11.02.2009 ![Search on Bibsonomy](Pics/bibsonomy.png) |
Delay and Disruption-Tolerant Networking (DTN) II ![Schloss Dagstuhl - Leibniz-Zentrum für Informatik, Germany The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
35 | Gunnar Karlsson, Ólafur Ragnar Helgason, Vladimir Vukadinovic |
On the Performance of Pedestrian Content Distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Delay and Disruption-Tolerant Networking (DTN) II ![In: Delay and Disruption-Tolerant Networking (DTN) II, 08.02. - 11.02.2009, 2009, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, Germany. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
35 | Eiko Yoneki, Pan Hui 0001, Jon Crowcroft |
Wireless Epidemic Spread in Dynamic Human Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Delay and Disruption-Tolerant Networking (DTN) II ![In: Delay and Disruption-Tolerant Networking (DTN) II, 08.02. - 11.02.2009, 2009, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, Germany. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
34 | Josef Schmid, Timo Schüring, Christoph Smalla |
Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 337-342, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
34 | Petar Djukic, Shahrokh Valaee |
Delay aware link scheduling for multi-hop TDMA wireless networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 17(3), pp. 870-883, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
TDMA scheduling algorithms, scheduling delay, stop-and-go queueing |
34 | I-De Huang, Yi-Shing Chang, Sandeep K. Gupta 0001, Sreejit Chakravarty |
An Industrial Case Study of Sticky Path-Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 395-402, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
sticky paths, timing false paths, path reprioritization, delay testing, test quality |
34 | Hechmi Khlifi, Jean-Charles Grégoire |
Estimation and Removal of Clock Skew From Delay Measures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: 29th Annual IEEE Conference on Local Computer Networks (LCN 2004), 16-18 November 2004, Tampa, FL, USA, Proceedings, pp. 144-151, 2004, IEEE Computer Society, 0-7695-2260-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
clock skew, delay measurement |
34 | Jun (Jim) Xu, Richard J. Lipton |
On fundamental tradeoffs between delay bounds and computational complexity in packet scheduling algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCOMM ![In: Proceedings of the ACM SIGCOMM 2002 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication, August 19-23, 2002, Pittsburgh, PA, USA, pp. 279-292, 2002, ACM, 1-58113-570-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
quality of service, computational complexity, decision tree, packet scheduling, delay bound |
34 | Tatsuhiro Tsuchiya, Masatoshi Yamaguchi, Tohru Kikuno |
Minimizing the Maximum Delay for Reaching Consensus in Quorum-Based Mutual Exclusion Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 10(4), pp. 337-345, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
distributed systems, mutual exclusion, communication delay, Quorums, coteries |
34 | Kartik Gopalan, Tzi-cker Chiueh, Yow-Jian Lin |
Probabilistic delay guarantees using delay distribution measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Multimedia ![In: Proceedings of the 12th ACM International Conference on Multimedia, New York, NY, USA, October 10-16, 2004, pp. 900-907, 2004, ACM, 1-58113-893-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
measurement-based, admission control, statistical multiplexing |
34 | Masoud Sharif, Babak Hassibi |
Delay Considerations for Opportunistic Scheduling in Broadcast Fading Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 6(9), pp. 3353-3363, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi 0001, Majid Sarrafzadeh |
Optimal integer delay-budget assignment on directed acyclic graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(8), pp. 1184-1199, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Yoon G. Kim, Afshin Shiravi, Paul S. Min |
Prediction-Based Routing through Least Cost Delay Constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Eun Sei Park, M. Ray Mercer |
An efficient delay test generation system for combinational logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(7), pp. 926-938, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
34 | Eun Sei Park, M. Ray Mercer |
An Efficient Delay Test Generation System for Combinational Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 522-528, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
33 | Youxin Gao, Martin D. F. Wong |
Wire-sizing optimization with inductance consideration using transmission-line model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(12), pp. 1759-1767, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
33 | Libin Dong, Rami G. Melhem, Daniel Mossé |
Effect of scheduling jitter on end-to-end delay in TDMA protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 7th International Workshop on Real-Time Computing and Applications Symposium (RTCSA 2000), 12-14 December 2000, Cheju Island, South Korea, pp. 223-230, 2000, IEEE Computer Society, 0-7695-0930-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
scheduling jitter, TDMA protocols, time slot allocation algorithm, transmission rate, ETE delay bound, simulations, scheduling, distributed system, real-time systems, delays, time division multiple access, time division multiple access, jitter, real time communication, end-to-end delay, packet delay, destination node |
33 | Ping Zhou, Charles Thompson |
Available Bit Rate (ABR) Source Control and Delay Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: Proceedings 27th Conference on Local Computer Networks, Tampa, Florida, USA, 8-10 November, 2000, pp. 598-603, 2000, IEEE Computer Society, 0-7695-0912-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
nonlinear estimation, ABR source control, transmission rate regulation, ABR traffic source, linear quadratic rate regulation, round-trip propagation delay estimation, nonlinear least mean square, NLMS algorithm, ATM standard, asynchronous transfer mode, ATM network, simulation results, telecommunication traffic, least squares approximations, telecommunication control, delay estimation, delay estimation, available bit rate |
33 | Priyadarsan Patra, Donald S. Fussell |
Power-efficient delay-insensitive codes for data transmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 316-323, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
telecommunication switching, power-efficient delay-insensitive codes, dynamic delay-insensitive codes, switching energy optimization, data pins, protocols, delays, power consumption, codes, asynchronous systems, data communication, data communication, data transmission, energy reduction, delay-insensitive circuits |
33 | Erik Burman, Guillaume Delay, Alexandre Ern |
The Unique Continuation Problem for the Heat Equation Discretized with a High-Order Space-Time Nonconforming Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIAM J. Numer. Anal. ![In: SIAM J. Numer. Anal. 61(5), pp. 2534-2557, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
33 | Pranoy Roy, Reza Ilka, Jiangbiao He, Yuan Liao, Aaron M. Cramer, Justin Mccann, Samuel Delay, Steven Coley, Melissa Geraghty, Sachindra Dahal |
Impact of Electric Vehicle Charging on Power Distribution Systems: A Case Study of the Grid in Western Kentucky. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 49002-49023, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
33 | Sahan Wijethunga, Shehan Kaushalya Senavirathna, Kavishka Dissanayake, Janith Bandara Senanayaka, Eranda Somathilake, Upekha Hansanie Delay, Roshan Indika Godaliyadda, Mervyn Parakrama B. Ekanayake, Janaka V. Wijayakulasooriya |
IMU-based Modularized Wearable Device for Human Motion Classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2303.16468, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
33 | Oleksandr Zaitsev, François Vendel, Etienne Delay |
Cormas: The Software for Participatory Modelling and its Application for Managing Natural Resources in Senegal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2310.12534, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
33 | Oleksandr Zaitsev, François Vendel, Etienne Delay |
Cormas: The Software for Participatory Modelling and Its Application for Managing Natural Resources in Senegal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par Workshops ![In: Euro-Par 2023: Parallel Processing Workshops - Euro-Par 2023 International Workshops, Limassol, Cyprus, August 28 - September 1, 2023, Revised Selected Papers, Part II, pp. 76-84, 2023, Springer, 978-3-031-48802-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
33 | Eranda Somathilake, Upekha Hansanie Delay, Janith Bandara Senanayaka, Samitha Gunarathne, Roshan Indika Godaliyadda, Mervyn Parakrama B. Ekanayake, Janaka V. Wijayakulasooriya, Chathura Rathnayake |
Assessment of Fetal and Maternal Well-Being During Pregnancy Using Passive Wearable Inertial Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 71, pp. 1-11, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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33 | Angelos K. Sikalidis, Aleksandra S. Kristo, Scott K. Reaves, Franz J. Kurfess, Ann M. DeLay, Kathryn Vasilaky, Lorraine Donegan |
Capacity Strengthening Undertaking - Farm Organized Response of Workers against Risk for Diabetes: (C.S.U. - F.O.R.W.A.R.D. with Cal Poly) - A Concept Approach to Tackling Diabetes in Vulnerable and Underserved Farmworkers in California. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 22(21), pp. 8299, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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