|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 438 occurrences of 169 keywords
|
|
|
Results
Found 386 publication records. Showing 386 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
157 | Srdjan Dragic, Martin Margala |
A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 25-26 April 2002, Pittsburgh, PA, USA, pp. 165-170, 2002, IEEE Computer Society, 0-7695-1486-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Current Amplifier, On-Line Testing, Iddq, delta Iddq, Current Monitoring |
143 | Chih-Wen Lu, Chauchin Su, Chung-Len Lee 0001, Jwu E. Chen |
Is IDDQ testing not applicable for deep submicron VLSI in year 2011? ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 338-343, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
deep submicron VLSI, IDDQ current estimation, random process deviations, IDDQ distributions, VLSI, statistical analysis, integrated circuit testing, CMOS integrated circuits, leakage currents, IDDQ testing, statistical approach, standard deviation, input vectors, circuit size |
133 | Arabi Keshk, Kozo Kinoshita, Yukiya Miura |
IDDQ Current Dependency on Test Vectors and Bridging Resistance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 158-163, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Bridging fault, IDDQ Testing |
128 | Jan Schat |
Evaluation of the Iddq Signature in devices with Gauss-distributed background current. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 241-246, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
128 | Yukio Okuda |
Eigen-Signatures for Regularity-based IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 289-294, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
126 | Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita |
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 443-451, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
IDDQ measurement vector, sequential circuit, bridging fault, IDDQ testing |
116 | Ashutosh Sharma, Anura P. Jayasumana, Yashwant K. Malaiya |
X-IDDQ: A Novel Defect Detection Technique Using IDDQ Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 180-185, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Defect Correlation, Principal Component Analysis, IDDQ, Binning, Test Optimization |
114 | Masaru Sanada |
A CAD-based approach to failure diagnosis of CMOS LSI's using abnormal Iddq. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 186-191, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
CAD-based failure diagnosis technology, CMOS LSI, abnormal Iddq phenomenon, physical damage detection, faulty blocks, failure point localization, Iddq test patterns, fault diagnosis, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, circuit CAD, large scale integration |
109 | Chih-Wen Lu, Chung-Len Lee 0001, Chauchin Su, Jwu-E Chen |
Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(1), pp. 89-97, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
VLSI, IDDQ testing, deep sub-micron |
102 | Paul Lee, Alfred Chen, Dilip Mathew |
A Speed-Dependent Approach for Delta IDDQ Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 280-286, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Self-scaling IDDQ, Speed Performance Index, characterization, Delta IDDQ |
102 | Yann Antonioli, Tsuneo Inufushi, Shigeki Nishikawa, Kozo Kinoshita |
A high-speed IDDQ sensor implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 356-361, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
circuit feedback, high-speed IDDQ sensor implementation, submicron CMOS process, feedback scheme, floppy-disk controller IDDQ test, current sensor, built-in sensor, 0.35 micron, 50 MHz, integrated circuit testing, CMOS digital integrated circuits, BICS, electric current measurement, electric sensing devices |
102 | B. Straka, Hans A. R. Manhaeve, Jozef Vanneuville, M. Svajda |
A Fully Digital Controlled Off-Chip IDDQ Measurement Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 495-500, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
IDDQ monitors, test hardware, CMOS, testability, integrated circuits, IDDQ |
98 | Claude Thibeault |
On the Comparison of IDDQ and IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 143-151, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
92 | Chintan Patel, Abhishek Singh 0001, Jim Plusquellic |
Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 319-328, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
92 | Yukio Okuda, Nobuyuki Furukawa |
Hysteresis of Intrinsic IDDQ Currents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 555-564, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
92 | C. P. Ravikumar, Rahul Kumar |
Divide-and-Conquer IDDQ Testing for Core-Based System Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 761-766, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
92 | Lan Zhao, D. M. H. Walker, Fabrizio Lombardi |
IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 47(10), pp. 1136-1152, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
92 | Jerry M. Soden, Charles F. Hawkins |
IDDQ Testing: Issues Present and Future. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 13(4), pp. 61-65, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
90 | Chintan Patel, Abhishek Singh 0001, Jim Plusquellic |
Defect Detection Using Quiescent Signal Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(5), pp. 463-483, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multiple current measurements, Quiescent Signal Analysis, IDDQ, current testing, defect-based testing, parametric testing |
90 | Lan Zhao, D. M. H. Walker, Fabrizio Lombardi |
Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 1037-1046, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
IDDQ Tes t, Configurable Logic Blocks, FPGA, Testing, Bridging Fault, Programming Phase |
86 | Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita |
IDDQ Sensing Technique for High Speed IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 111-116, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
85 | Alan W. Righter, Charles F. Hawkins, Jerry M. Soden, Peter C. Maxwell |
CMOS IC reliability indicators and burn-in economics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 194-203, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
85 | Toshiyuki Maeda, Kozo Kinoshita |
Compaction of IDDQ Test Sequence Using Reassignment Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(3), pp. 243-249, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
reassignment method, weighted random vector, sequential circuit, IDDQ testing, test compaction |
85 | Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara |
On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 147-152, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
IDDQ testing, test compaction |
85 | Rosa Rodríguez-Montañés, Joan Figueras |
Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 490-494, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
IDDQ testability, CMOS, deep-submicron |
85 | Peter C. Maxwell |
The use of IDDQ testing in low stuck-at coverage situations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 84-88, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
stuck-at coverage situations, quality goal, graded coverage, composite metric, fault diagnosis, logic testing, logic tests, integrated circuit testing, automatic testing, application specific integrated circuits, ASIC, CMOS logic circuits, IDDQ testing, IC testing |
80 | Kunhyuk Kang, Keejong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy 0001 |
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 358-363, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
80 | Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal |
New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 353-360, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
80 | Shengli Li, Kai Zhang, Jien-Chung Lo |
The 2nd Order Analysis of IDDQ Test Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 376-, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
80 | R. D. (Shawn) Blanton |
IDDQ-Testability of Tree Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 78-86, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
77 | Sagar S. Sabade, D. M. H. Walker |
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 361-, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
spatial correlation, IDDQ testing, delta IDDQ |
77 | Hisashi Kondo, Kwang-Ting Cheng |
Driving toward higher IDDQ test quality for sequential circuits: a generalized fault model and its ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 228-232, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Selective IDDQ, Pseudo Stuck-at Fault, Sequential ATPG, Vector compaction, Test, Fault model, IDDQ, Leakage Fault |
67 | B. Straka, Hans A. R. Manhaeve, J. Brenkus, Stefaan Kerckenaere |
Theoretical and Practical Aspects of IDDQ Settling-Impact on Measurement Timing and Quality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1310-1315, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
67 | Chuen-Song Chen, Jien-Chung Lo, Tian Xia |
Equivalent IDDQ Tests for Systems with Regulated Power Supply. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 291-299, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
67 | Abhijit Prasad, D. M. H. Walker |
Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 140-, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
67 | Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota |
Test Vector Generation Based on Correlation Model for Ratio-Iddq. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 545-554, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
67 | Swarup Bhunia, Hai Li, Kaushik Roy 0001 |
A High Performance IDDQ Testable Cache for Scaled CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 157-, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
67 | Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni |
Extending the Viability of IDDQ Testing in the Deep Submicron Era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 100-105, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
67 | Sagar S. Sabade, D. M. H. Walker |
Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 81-86, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
67 | Bram Kruseman, Stefan van den Oetelaar, Josep Rius 0001 |
Comparison of IDDQ Testing and Very-Low Voltage Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 964-973, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
67 | Zhanping Chen, Liqiong Wei, Kaushik Roy 0001 |
On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(5), pp. 718-725, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
67 | Chintan Patel, Jim Plusquellic |
A Process and Technology-Tolerant IDDQ Method for IC Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 145-152, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
67 | Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Masashi Takeda |
Testability Analysis of IDDQ Testing with Large Threshold Value. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 367-375, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
67 | Zhanping Chen, Liqiong Wei, Kaushik Roy 0001 |
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 181-188, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
65 | Hisashi Kondo, Kwang-Ting Cheng |
An Efficient Compact Test Generator for IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 177-182, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Selective IDDQ, Pattern Compaction, Pseudo Stuck-at Fault, Essential Fault, Test, ATPG, Fault Model, Testability, IDDQ, Leakage Fault |
60 | Jim Plusquellic, Dhruva Acharyya, Abhishek Singh 0001, Mohammad Tehranipoor, Chintan Patel |
Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(4), pp. 278-293, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Quiescent Signal Analysis, defect detection, IDDQ |
60 | Chuen-Song Chen, Jien-Chung Lo, Tian Xia |
An indirect current sensing technique for IDDQ and IDDT tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 235-240, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
IDDT, IDDQ, current testing, BICS |
60 | Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni |
An Embedded IDDQ Testing Architecture and Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 442-445, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
IEEE 1149.1, Design for Testability (DFT), Boundary Scan, IDDQ Testing |
60 | Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos |
A Compact Built-In Current Sensor for IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 95-99, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Bridging and Stuck-on fault testability, Design for testability, DFT, IDDQ testing, Built in current sensors, BICS, Current monitoring |
60 | Hugo Cheung, Sandeep K. Gupta 0001 |
A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 89-96, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
critical severity, test escape, fault modeling, IDDQ, yield loss |
60 | Theo J. Powell, James R. Pair, Melissa St. John, Doug Counce |
Delta Iddq for Testing Reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 439-443, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
reliability, Iddq |
60 | Víctor H. Champac, José Castillejos, Joan Figueras |
IDDQ Testing of Opens in CMOS SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(1-2), pp. 53-62, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
data retention faults, memory testing, opens, IDDQ |
60 | Yinghua Min, Zhongcheng Li |
IDDT Testing versus IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(1), pp. 51-55, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
IDDT test, IDDQ test, stuck-open fault, Boolean process |
55 | Bin Xue, D. M. H. Walker |
Is IDDQ Test of Microprocessors Feasible? ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA, pp. 63-69, 2005, IEEE Computer Society, 0-7695-2627-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
55 | Sagar S. Sabade, D. M. H. Walker |
Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 889-894, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
55 | Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita |
A BIST Circuit for IDDQ Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 390-395, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
55 | Chris Schuermyer, Brady Benware, Kevin Cota, Robert Madge, W. Robert Daasch, L. Ning |
Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 565-573, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
55 | Sagar S. Sabade, D. M. H. Walker |
IDDQ Test: Will It Survive the DSM Challenge? ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 19(5), pp. 8-16, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
55 | Sagar S. Sabade, D. M. H. Walker |
Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 381-389, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
55 | Claude Thibeault |
Speeding-Up IDDQ Measurements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 295-301, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
55 | W. Robert Daasch, Kevin Cota, James McNames, Robert Madge |
Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 1240, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
55 | David I. Bergman, Hans Engler |
Improved IDDQ Testing with Empirical Linear Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 954-963, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
55 | Sagar S. Sabade, D. M. H. Walker |
Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 755-760, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
55 | Juan M. Díez, Juan Carlos López 0001 |
Influence of Manufacturing Variations in IDDQ Measurements: A New Test Criterion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 645-649, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
55 | Sri Jandhyala, Hari Balachandran, Manidip Sengupta, Anura P. Jayasumana |
Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 444-452, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
55 | Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita |
Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 312-317, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
55 | Manoj Sachdev |
Deep sub-micron IDDQ testing: issues and solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 271-278, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
49 | Robert Madge, Manu Rehani, Kevin Cota, W. Robert Daasch |
Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 69-74, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
48 | Sagar S. Sabade, D. M. H. Walker |
Use of Multiple IDDQ Test Metrics for Outlier Identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 31-38, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Current ratio, neighbor current ratio, outlier identification, spatial correlation, IDDQ testing |
48 | Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda |
High speed IDDQ test and its testability for process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 344-349, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
high speed IDDQ test, charge current, gate load capacitances, test input vector application, CMOS IC production, logic testing, integrated circuit testing, process variation, testability, CMOS logic circuits, production testing |
48 | Tsuyoshi Shinogi, Masahiro Ushio, Terumine Hayashi |
Cyclic greedy generation method for limited number of IDDQ tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 362-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
cyclic greedy generation method, undetected faults, ISCAS85Y circuits, short circuit faults, fault diagnosis, integrated circuit testing, iterative methods, iterative method, CMOS integrated circuits, IDDQ tests, test patterns, CMOS IC, electric current measurement, cyclic, random patterns |
48 | Claude Thibeault |
Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 431-438, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
probabilistic signatures, double faults, Diagnosis, Viterbi algorithm, Delta Iddq |
48 | Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita |
Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 141-146, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
sequential circuit, fault simulation, bridging fault, IDDQ testing |
48 | Tsuyoshi Shinogi, Terumine Hayashi |
A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 164-, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
compact test generation, parallel processing, ATPG, IDDQ testing |
48 | Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken |
An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 459, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
semiconductor testing, stuck-fault testing, ASIC device, application specific integrated circuits, functional testing, IDDQ testing, delay-fault testing, scan testing |
48 | Hari Balachandran, D. M. H. Walker |
Improvement of SRAM-based failure analysis using calibrated Iddq testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 130-137, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
defect-bitmap dictionary, voltage testing, microprocessor cache memory, integrated circuit testing, calibration, calibration, SRAM, cache storage, failure analysis, failure analysis, IDDQ testing, current testing, defect classification, SRAM chips, integrated circuit yield, integrated circuit yield |
48 | Jason P. Hurst, Adit D. Singh |
A differential built-in current sensor design for high speed IDDQ testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 419-423, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
built-in current sensor design, high speed IDDQ testing, differential architecture, quiescent current detection, BIST environment, n-well technology, MOSIS, 31.25 MHz, VLSI, built-in self test, built-in self-test, integrated circuit testing, design for testability, integrated circuit design, CMOS digital integrated circuits, electric current measurement, 2 micron, electric sensing devices |
43 | Junichi Hirase, Yoshiyuki Goi, Yoshiyuki Tanaka |
IDDQ Testing Method using a Scan Pattern for Production Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 18-21, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Thomas J. Vogels |
Effectiveness of I-V Testing in Comparison to IDDq Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 47-56, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Nobuhiro Sato, Yoshihiro Hashimoto |
A High Precision IDDQ Measurement System With Improved Dynamic Load Regulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 410-414, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Sreejit Chakravarty, Sujit T. Zachariah |
STBM: a fast algorithm to simulate IDDQ tests forleakage faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5), pp. 568-576, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | Lan Zhao, D. M. H. Walker, Fabrizio Lombardi |
Bridging Fault Detection in FPGA Interconnects Using IDDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998, pp. 95-104, 1998, ACM, 0-89791-978-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
43 | M. Svajda, B. Straka, Hans A. R. Manhaeve |
IOCIMU - An Integrated Off-Chip IDDQ Measurement Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 959-960, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
43 | Md. Altaf-Ul-Amin, Zahari Mohamed Darus |
An Off-Chip Current Sensor for IDDQ Testing of CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 318-322, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
43 | B. Laquai, H. Richter, H. Werkmann |
A production-oriented measurement method for fast and exhaustive Iddq tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 279-286, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
43 | Don Douglas Josephson, Mark Storey, Daniel D. Dixon |
Microprocessor IDDQ Testing: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 12(2), pp. 42-52, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
43 | S. Wayne Bollinger, Scott F. Midkiff |
Test generation for IDDQ testing of bridging faults in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(11), pp. 1413-1418, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
41 | Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001 |
Low-Power and testable circuit synthesis using Shannon decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(4), pp. 47, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Shannon expansion, dynamic supply gating, test coverage, Design-for-test, IDDQ, noise immunity, test power |
41 | Anton Chichkov, Dirk Merlier, Peter Cox |
Current Testing Procedure for Deep Submicron Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(3-4), pp. 219-224, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
ASIC testing, IDDQ, deep submicron |
41 | Antonio Zenteno, Víctor H. Champac, Joan Figueras |
Detectability Conditions of Full Opens in the Interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(2), pp. 85-95, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
logic testing, IDDQ testing, opens, defect modeling |
41 | Yukiya Miura, Hiroshi Yamazaki |
A Low-Loss Built-In Current Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 39-48, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
low-voltage LSIs, multiple power supplies, IDDQ testing, Built-in current sensor |
41 | Claude Thibeault |
Increasing Current Testing Resolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 126-134, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
current signatures, test, Integrated circuits, Iddq testing |
41 | Yinghua Min, Zhuxing Zhao, Zhongcheng Li |
IDDT Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 378-383, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
IDDT test, IDDQ test, stuck-open fault, Boolean process |
38 | Alexei Kaltchenko, Oleg Semenov |
Temperature dependence of IDDQ distribution: application for thermal delta IDDQ testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 1(6), pp. 509-516, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Carlo Dallavalle |
Adaptive IDDQ: How to Set an IDDQ Limit for any Device Under Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, pp. 177, 2002, IEEE Computer Society, 0-7695-1641-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
36 | Ritesh P. Turakhia, Brady Benware, Robert Madge, Thaddeus T. Shannon, W. Robert Daasch |
Defect Screening Using Independent Component Analysis on I_DDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 427-432, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Ali Keshavarzi, Kaushik Roy 0001, Charles F. Hawkins |
Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(6), pp. 717-723, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Wanli Jiang, Bapiraju Vinnakota |
IC test using the energy consumption ratio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1), pp. 129-141, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Josep Rius 0001, Luis Elvira Villagra, Maurice Meijer |
A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 14th IEEE European Test Symposium, ETS 2009, Sevilla, Spain, May 25-29, 2009, pp. 135-140, 2009, IEEE Computer Society, 978-0-7695-3703-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
IDDQ testing |
36 | Toshiyuki Maeda, Kozo Kinoshita |
Memory reduction of IDDQ test compaction for internal and external bridging faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 350-355, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction |
Displaying result #1 - #100 of 386 (100 per page; Change: ) Pages: [ 1][ 2][ 3][ 4][ >>] |
|