|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 37 occurrences of 34 keywords
|
|
|
Results
Found 294 publication records. Showing 294 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
74 | Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang |
Simultaneous block and I/O buffer floorplanning for flip-chip design. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
67 | Xiaodong Liu 0018, Yifan Zhang, Gary K. Yeap, Chunlei Chu, Jian Sun 0005, Xuan Zeng 0001 |
Global routing and track assignment for flip-chip designs. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
flip-chip, track assignment, voronoi diagram, global routing |
62 | Cheng-Yu Wang, Wai-Kei Mak |
Signal skew aware floorplanning and bumper signal assignment technique for flip-chip. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
58 | Chia-Yi Chang, Hung-Ming Chen |
Design Migration From Peripheral ASIC Design to Area-I/O Flip-Chip Design by Chip I/O Planning and Legalization. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
56 | Jia-Wei Fang, Yao-Wen Chang |
Area-I/O flip-chip routing for chip-package co-design. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
53 | Jin-Tai Yan, Zhi-Wei Chen |
RDL pre-assignment routing for flip-chip designs. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
RDL routing, flip-chip design, routability, wirelength |
44 | Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang |
An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
44 | Jia-Wei Fang, I-Jye Lin, Yao-Wen Chang, Jyh-Herng Wang |
A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang |
An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
41 | XiaoLi Da, Guangdi Shen, Chen Xu, DeShu Zou, YanXu Zhu, Jia Zhang |
Investigation of high extraction efficiency flip-chip GaN-based light-emitting diodes. |
Sci. China Ser. F Inf. Sci. |
2009 |
DBLP DOI BibTeX RDF |
GaN, light emitting diodes, SiO2/SiN x dielectric film reflectors, plasma enhanced chemical vapor deposition |
41 | Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen |
Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Woo Hyung Lee, Sanjay Pant, David T. Blaauw |
Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Y. P. Wu, M. O. Alam, Yan Cheong Chan, B. Y. Wu |
Dynamic strength of anisotropic conductive joints in flip chip on glass and flip chip on flex packages. |
Microelectron. Reliab. |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Hung-Ming Chen, I-Min Liu, Martin D. F. Wong |
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang |
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Janet Meiling Wang, Kishore Kumar Muchherla, Jai Ganesh Kumar |
A Clustering Based Area I/O Planning for Flip-Chip Technology. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Kari Stadius, Kari Halonen |
Development of 4-GHz flip-chip VCO module. |
ISCAS (3) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Eli Chiprout |
Fast flip-chip power grid analysis via locality and grid shells. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Mario Paniccia, Travis M. Eiles, V. R. M. Rao, Wai Mun Yee |
Novel optical probing technique for flip chip packaged microprocessors. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
32 | Tymon Barwicz, Swetha Kamlapurkar, Yves Martin, Robert L. Bruce, Sebastian Engelmann |
A silicon metamaterial chip-to-chip coupler for photonic flip-chip applications. |
OFC |
2017 |
DBLP BibTeX RDF |
|
32 | Theresa Sze, Darko Popovic, Jing Shi, Yi-Shao Lai, James G. Mitchell, Bruce Guenin, Tsung-Yueh Tsai, Chin-Li Kao, Matthew Giere |
Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip package. |
Microelectron. Reliab. |
2010 |
DBLP DOI BibTeX RDF |
|
31 | Ming-Fang Lai, Hung-Ming Chen |
An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Chip-Package Codesign, I/O Placement, Power Integrity |
30 | Jin-Tai Yan, Zhi-Wei Chen |
IO connection assignment and RDL routing for flip-chip designs. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Jia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang |
Flip-chip routing with unified area-I/O pad assignments for package-board co-design. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
physical design, global routing, detailed routing |
30 | Hao-Yueh Hsieh, Ting-Chi Wang |
Simple yet effective algorithms for block and I/O buffer placement in flip-chip design. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Roderick P. Cruz |
Flip Chip Advanced Package Solder Joint Embrittlement Fault Isolation Using TDR. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Rishi Bhooshan |
Novel and Efficient IR-Drop Models for Designing Power Distribution Network for Sub-100nm Integrated Circuits. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Andrey V. Mezhiba, Eby G. Friedman |
Scaling trends of on-chip Power distribution noise. |
SLIP |
2002 |
DBLP DOI BibTeX RDF |
technology scaling, power supply noise, power distribution |
25 | Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Kikuo Muramatsu, Hiromu Hasegawa, Takuya Sawada, Takahito Fukushima, Hisashi Kondo, Takuji Miki, Makoto Nagata |
Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging. |
IEICE Trans. Electron. |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Takuji Miki, Makoto Nagata, Kikuo Muramatsu, Hiromu Hasegawa, Takuya Sawada, Takahito Fukushima, Hisashi Kondo |
Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging. |
IRPS |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Lev Kirischian, Valeri Kirischian, Dimple Sharma |
Mitigation of Thermo-cycling effects in Flip-chip FPGA-based Space-borne Systems by Cyclic On-chip Task Relocation. |
AHS |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Lin Lin, Jun Wang, Lei Wang, Wenqi Zhang |
The stress analysis and parametric studies for the low-k layers of a chip in the flip-chip process. |
Microelectron. Reliab. |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Kyung-Woon Jang, Jin-Hyoung Park, Soon-Bok Lee, Kyung-Wook Paik |
A study on thermal cycling (T/C) reliability of anisotropic conductive film (ACF) flip chip assembly for thin chip-on-board (COB) packages. |
Microelectron. Reliab. |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Sheldon Logan, Matthew R. Guthaus |
Package-chip co-design to increase flip-chip C4 reliability. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Jia-Wei Fang, Yao-Wen Chang |
Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
25 | Changsoo Jang, Seongyoung Han, Hangyu Kim, Sayoon Kang |
A numerical failure analysis on lead breakage issues of ultra fine pitch flip chip-on-flex and tape carrier packages during chip/film assembly process. |
Microelectron. Reliab. |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Takashi Tokuda, Masayuki Kawada, Sachie Sugitani, Mari Taniyama, Akihiro Uehara, Keiichiro Kagawa, Masahiro Nunoshita, Jun Ohta |
A multi-chip-architecture based flexible stimulation device for retinal prosthesis with a flip-chip packaging technique. |
EMBC |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Ovidiu Vermesan, Knut H. Riisnæs, Laurent Le Pailleur, Jon B. Nysæther, Mark Bauge, Helge Rustad, Sigmund Clausen, Lars-Cyril Julin Blystad, Hanne Grindvoll, Rune Pedersen, Robert Pezzani, David Kaire |
A 500-dpi AC capacitive hybrid flip-chip CMOS ASIC/sensor module for fingerprint, navigation, and pointer detection with on-chip data processing. |
IEEE J. Solid State Circuits |
2003 |
DBLP DOI BibTeX RDF |
|
25 | C. F. Luk, Y. C. Chan, K. C. Hung |
Development of gold to gold interconnection flip chip bonding for chip on suspension assemblies. |
Microelectron. Reliab. |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Giulio Di Giacomo, Stefano Oggioni |
Reliability of Flip Chip Applications with Ceramic and Organic Chip Carriers. |
Microelectron. Reliab. |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Greg Hotchkiss, Gonzalo Amador, Darvin Edwards, Paul Hundt, Les Stark, Roger Stierman, Gail Heinen |
Wafer level packaging of a tape flip-chip chip scale packages. |
Microelectron. Reliab. |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Yutaka Kumano, Yoshihiro Tomura, Minehiro Itagaki, Yoshihiro Bessho |
Development of chip-on-flex using SBB flip-chip technology. |
Microelectron. Reliab. |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Rishi Bhooshan, Bindu P. Rao |
Optimum IR drop models for estimation of metal resource requirements for power distribution network. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Kaushik Sheth, Egino Sarto, Joel McGrath |
The importance of adopting a package-aware chip design flow. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
RDL, flip chip, routing, concurrent, prototyping, synthesis, exploration, co-design, I/O, package, chip, substrate |
23 | Rui Shi 0003, Chung-Kuan Cheng |
Efficient escape routing for hexagonal array of high density I/Os. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
BGA, flip chip, hexagonal array, escape routing |
23 | Chandra Tan, Donald W. Bouldin, Peyman H. Dehkordi |
Design Implementation of Intrinsic Area Array ICs. |
ARVLSI |
1997 |
DBLP DOI BibTeX RDF |
Area-array pad, flip-chip, physical design, VLSI design, placement and routing |
23 | Peter Sandborn, Rajarshi Ghosh, Ken Drake, Magdy S. Abadir, Linda Bal, Ashish Parikh |
Multichip systems trade-off analysis tool. |
J. Electron. Test. |
1994 |
DBLP DOI BibTeX RDF |
flip chip bonding, multichip module (MCM), packaging and interconnect, Conceptual design, trade-off analysis |
23 | Meigen Shen, Li-Rong Zheng 0001, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen |
Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Jun Ohta, Takahashi Tokuda, Keiichiro Kagawa, Akihiro Uehara, Yasuo Terasawa, Kazuaki Nakauchi, Takashi Fujikado, Yasuo Tano |
A multi-microchip retinal stimulator for in vitro / in vivo experiments. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Aishwarya Dubey |
P/G Pad Placement Optimization: Problem Forumulation for Best IR Drop. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
P/G (Power/Ground) pad placement, current sink, package resistance, package inductance, IR drop |
20 | Qing Zhu, Wayne Wei-Ming Dai |
Planar clock routing for high performance chip and package co-design. |
IEEE Trans. Very Large Scale Integr. Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Yaofeng Yi, Toshimasa Umezawa, Kouichi Akahane, Tetsuya Kawanishi |
Thermal Study for High-Photocurrent Photodetector in Non-Saturation Region Using Thin Substrate, Thin Absorber, and Flip- Chip Bonding Process. |
IEEE Access |
2024 |
DBLP DOI BibTeX RDF |
|
19 | Yu Sun, Lei Su 0002, Jiefei Gu, Ke Li, Michael G. Pecht |
A Novel Three-Probability Spaces Logic Decoupling Distillation for Flip-Chip Defect Detection. |
IEEE Trans. Instrum. Meas. |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Lanxiang Xiao, Lei Chen 0001, Fengwei An |
An 11.6aF/kPa Mechanical Stress Sensor With 0.808% Temperature-Drift Oscillator for Flip-Chip Packaging. |
IEEE Trans. Circuits Syst. II Express Briefs |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Toshiki Kishi, Munehiko Nagatani, Shigeru Kanazawa, Kota Shikama, Takuro Fujii, Hidetaka Nishi, Tadashi Minotani, Norio Sato, Toru Segawa, Shinji Matsuo |
30-Gbps/ch x 4 ch Simultaneous Error-Free Transmission with A Low-Power Transmitter Flip-Chip-Bonded 1.3-μm LD-Array-on-Si. |
OFC |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Naseem, Nan-Wei Chen, Syed Hasan Parvez, Zohauddin Ahmad, Sean Yang, H.-S. Chen, Hsiang-Szu Chang, Jack Jia-Sheng Huang, Jin-Wei Shi |
Enhancement of Bandwidth-Responsivity Product in High-Speed Avalanche Photodiodes with Optimized Flip-Chip Bonding Package for Coherent Detection. |
OFC |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Jiedong Li, Hui Tang 0003, Zhongyuan Zhu, Sifeng He, Jian Gao 0002, Yunbo He, Xin Chen 0005 |
Hybrid Position/Force Fully Closed-Loop Control of a Flip-Chip Soft-Landing Bonding System. |
IEEE Trans. Ind. Electron. |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Pragya Laad |
"High Five": Arm's first 5nm Silicon in flip-chip! |
SOCC |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Szu-Ru Nie, Yen-Ting Chen, Yao-Wen Chang |
Y-architecture-based flip-chip routing with dynamic programming-based bend minimization. |
DAC |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Sifeng He, Hui Tang 0003, Kaifu Zhang, Chuangbin Chen, Jianglin Wang, Zhongyuan Zhu, Jian Gao 0002, Chengqiang Cui, Xin Chen 0005 |
A Flip-Chip Alignment System With the Property of Deviation Self-Correction at the Nanoscale. |
IEEE Trans. Ind. Electron. |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Chunkyun Seok, Oluwafemi Joel Adelegan, Ali Önder Biliroglu, Feysel Yalcin Yamaner, Ömer Oralkan |
A Wearable Ultrasonic Neurostimulator - Part II: A 2D CMUT Phased Array System With a Flip-Chip Bonded ASIC. |
IEEE Trans. Biomed. Circuits Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor |
An End-to-End Bitstream Tamper Attack Against Flip-Chip FPGAs. |
IACR Cryptol. ePrint Arch. |
2021 |
DBLP BibTeX RDF |
|
19 | Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi |
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. |
IEEE J. Solid State Circuits |
2020 |
DBLP DOI BibTeX RDF |
|
19 | Haiyang Xia, Tao Zhang 0086, Lianming Li, Fu-Chun Zheng |
A 1 × 2 Taper Slot Antenna Array With Flip-Chip Interconnect via Glass-IPD Technology for 60 GHz Radar Sensors. |
IEEE Access |
2020 |
DBLP DOI BibTeX RDF |
|
19 | Zelong Wu, Hui Tang 0003, Zhaoyang Feng, Weimin Wang, Sifeng He, Jian Gao 0002, Xin Chen 0005, Yunbo He, Xun Chen 0002 |
A Novel Self-Feedback Intelligent Vision Measure for Fast and Accurate Alignment in Flip-Chip Packaging. |
IEEE Trans. Ind. Informatics |
2020 |
DBLP DOI BibTeX RDF |
|
19 | Taiki Uemura, Byungjin Chung, Jeongmin Jo, Hai Jiang 0005, Yongsung Ji, Tae-Young Jeong, Rakesh Ranjan, Seungbae Lee, Hwasung Rhee, Sangwoo Pae, Euncheol Lee, Jaehee Choi, Shota Ohnishi, Ken Machida |
Backside Alpha-Irradiation Test in Flip-Chip Package in EUV 7 nm FinFET SRAM. |
IRPS |
2020 |
DBLP DOI BibTeX RDF |
|
19 | Serguei Stoukatch, Nicolas André, Thibault P. Delhaye, François Dupont, Jean-Michel Redouté, Denis Flandre |
Anisotropic conductive film & flip-chip bonding for low-cost sensor prototyping on rigid & flex PCB. |
IEEE SENSORS |
2020 |
DBLP DOI BibTeX RDF |
|
19 | Andrew Townley, Nima Baniasadi, Sashank Krishnamurthy, Constantine Sideris, Ali Hajimiri, Elad Alon, Ali M. Niknejad |
A Fully Integrated, Dual Channel, Flip Chip Packaged 113 GHz Transceiver in 28nm CMOS supporting an 80 Gb/s Wireless Link. |
CICC |
2020 |
DBLP DOI BibTeX RDF |
|
19 | Toshiki Kishi, Munehiko Nagatani, Shigeru Kanazawa, Kota Shikama, Takuro Fujii, Hidetaka Nishi, Hiroshi Yamazaki, Norio Sato, Hideyuki Nosaka, Shinji Matsuo |
A 0.57-mW/Gbps, 2ch × 53-Gbps Low-Power PAM4 Transmitter Front-End Flip-Chip-Bonded 1.3-µm LD-Array-on-Si. |
OFC |
2020 |
DBLP BibTeX RDF |
|
19 | Sensen Li, Taiyun Chi, Jong Seok Park, Huy Thong Nguyen, Hua Wang 0006 |
A 28-GHz Flip-Chip Packaged Chireix Transmitter With On-Antenna Outphasing Active Load Modulation. |
IEEE J. Solid State Circuits |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Guanghua Wu, Meixian Jiang |
Study on the Interfacial Residual Stress of Flip-Chip Joints Based on Anisotropic Conductive Adhesive. |
IEEE Access |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Chun-Hsing Li, Te-Yen Chiu |
Single Flip-Chip Packaged Dielectric Resonator Antenna for CMOS Terahertz Antenna Array Gain Enhancement. |
IEEE Access |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Tao-Chun Yu, An-Jie Shih, Shao-Yun Fang |
Flip-Chip Routing With I/O Planning Considering Practical Pad Assignment Constraints. |
IEEE Trans. Very Large Scale Integr. Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Shigeru Kanazawa, Hiroshi Yamazaki, Yuta Ueda, Wataru Kobayashi, Yoshihiro Ogiso, Johsuke Ozaki, Takahiko Shindo, Satoshi Tsunashima, Hiromasa Tanobe, Atsushi Araratake |
High-Frequency and Integrated Design Based on Flip-Chip Interconnection Technique (Hi-FIT) for High-Speed (>100 Gbaud) Optical Devices. |
IEICE Trans. Electron. |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Shunli Ma, Hao Yu 0001, Qun Jane Gu, Junyan Ren |
A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Zhuo-Jie Wu, Manish Nayini, Charles Carey, Samantha Donovan, David Questad, Edmund D. Blackshear |
CPI Reliability Challenges of Large Flip Chip Packages and Effects of Kerf Size and Substrate. |
IRPS |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Yu-Hsuan Chang, Hsiang-Ting Wen, Yao-Wen Chang |
Obstacle-Aware Group-Based Length-Matching Routing for Pre-Assignment Area-I/O Flip-Chip Designs. |
ICCAD |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi |
A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. |
A-SSCC |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Kerim Kibaroglu, Mustafa Sayginer, Gabriel M. Rebeiz |
A Low-Cost Scalable 32-Element 28-GHz Phased Array Transceiver for 5G Communication Links Based on a 2×2 Beamformer Flip-Chip Unit Cell. |
IEEE J. Solid State Circuits |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Junhui Li, Qing Tian, Haoliang Zhang, Xinxin Chen, Xiaohe Liu, Wenhui Zhu |
Study on Dipping Mathematical Models for the Solder Flip-Chip Bonding in Microelectronics Packaging. |
IEEE Trans. Ind. Informatics |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Lisa Mitterhuber, Stefan Defregger, Julien Magnien, Jördis Rosc, René Hammer, Lena Goullon, Matthias Hutter, Franz Schrank, Stefan Hörth, Elke Kraker |
Thermal transient measurement and modelling of a power cycled flip-chip LED module. |
Microelectron. Reliab. |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Melina Lofrano, Vladimir Cherman, Mario Gonzalez, Eric Beyne |
Enhanced Cu pillar design to reduce thermomechanical stress induced during flip chip assembly. |
Microelectron. Reliab. |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Jiajie Fan, Jianwu Cao, Chaohua Yu, Cheng Qian 0003, Xuejun Fan, Guoqi Zhang |
A design and qualification of LED flip Chip-on-Board module with tunable color temperatures. |
Microelectron. Reliab. |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Fei Chong Ng, Aizat Abas, Mohd Zulkifly Abdullah |
Effect of solder bump shapes on underfill flow in flip-chip encapsulation using analytical, numerical and PIV experimental approaches. |
Microelectron. Reliab. |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Julien Magnien, Lisa Mitterhuber, Jördis Rosc, Franz Schrank, Stefan Hörth, Matthias Hutter, Stefan Defregger, Elke Kraker |
Parameter driven monitoring for a flip-chip LED module under power cycling condition. |
Microelectron. Reliab. |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Tao-Chun Yu, Shao-Yun Fang |
Flip-chip routing with IO planning considering practical pad assignment constraints. |
ASP-DAC |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Takeshi Matsumoto, Teruo Kurahashi, Ryotaro Konoike, Ken Tanizawa, Keijiro Suzuki, Ayahito Uetake, Kazumasa Takabayashi, Kazuhiro Ikeda, Hitoshi Kawashima, Suguru Akiyama, Shigeaki Sekiguchi |
In-line Optical Amplification for Silicon Photonics Platform by Flip-Chip Bonded InP-SOAs. |
OFC |
2018 |
DBLP BibTeX RDF |
|
19 | Toshiki Kishi, Munehiko Nagatani, Shigeru Kanazawa, Shinsuke Nakano, Hiroaki Katsurai, Takuro Fujii, Hidetaka Nishi, Takaaki Kakitsuka, Koichi Hasebe, Kota Shikama, Yuko Kawajiri, Atsushi Aratake, Hideyuki Nosaka, Hiroshi Fukuda, Shinji Matsuo |
A 137-mW, 4 ch × 25-Gbps Low-Power Compact Transmitter Flip-Chip-Bonded 1.3-μm LD-Array-on-Si. |
OFC |
2018 |
DBLP BibTeX RDF |
|
19 | Saqib A. Khan, Chul Seung Lim, GeunYong Bak, Sanghyeon Baeg, Soonyoung Lee |
An alternative approach to measure alpha-particle-induced SEU cross-section for flip-chip packaged SRAM devices: High energy alpha backside irradiation. |
Microelectron. Reliab. |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Vincenzo d'Alessandro, Antonio Pio Catalano, Alessandro Magnani, Lorenzo Codecasa, Niccolò Rinaldi, Brian Moser, Peter J. Zampardi |
Simulation comparison of InGaP/GaAs HBT thermal performance in wire-bonding and flip-chip technologies. |
Microelectron. Reliab. |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Julien Magnien, Lisa Mitterhuber, Jördis Rosc, Franz Schrank, Stefan Hörth, Lena Goullon, Matthias Hutter, Stefan Defregger, Elke Kraker |
Reliability and failure analysis of solder joints in flip chip LEDs via thermal impedance characterisation. |
Microelectron. Reliab. |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Ari Laor, Depayne Athia, Alireza Rezvani, Horst Clauberg, Michael Mayer |
Monitoring of thermo-mechanical stress via CMOS sensor array: Effects of warpage and tilt in flip chip thermo-compression bonding. |
Microelectron. Reliab. |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Jin-Tai Yan |
Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip Designs. |
ACM Trans. Design Autom. Electr. Syst. |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Shrikant Swaminathan, Kamal K. Sikka, Richard F. Indyk, Tuhin Sinha |
Measurement of underfill interfacial and bulk fracture toughness in flip-chip packages. |
Microelectron. Reliab. |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Hongjun Ji, Jiao Wang, Mingyu Li |
Microstructure and reliability of hybrid interconnects by Au stud bump with Sn-0.7Cu solder for flip chip power device packaging. |
Microelectron. Reliab. |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Brett Fennell, Sangil Lee, Daniel F. Baldwin |
Rotational solder self-alignment mechanics modeling for a flip chip in the presence of a viscous fluid. |
Microelectron. Reliab. |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Saqib A. Khan, Shi-Jie Wen, Sanghyeon Baeg |
Assessing alpha-particle-induced SEU sensitivity of flip-chip bonded SRAM using high energy irradiation. |
IEICE Electron. Express |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Saqib A. Khan, Shi-Jie Wen, Sanghyeon Baeg |
Erratum: Assessing alpha-particle-induced SEU sensitivity of flip-chip bonded SRAM using high energy irradiation [IEICE Electronics Express Vol. 13 (2016) No. 17 pp. 20160627]. |
IEICE Electron. Express |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Nathaniel Ross Pinckney, Dennis Sylvester, David T. Blaauw |
Supply boosting for high-performance processors in flip-chip packages. |
ESSCIRC |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Takeshi Matsumoto, Teruo Kurahashi, Ken Tanizawa, Keijiro Suzuki, Ayahito Uetake, Kazumasa Takabayashi, Kazuhiro Ikeda, Hitoshi Kawashima, Suguru Akiyama |
In-line optical amplification for Si waveguides on 1×8 splitter and selector by flip-chip bonded InP-SOAs. |
OFC |
2016 |
DBLP BibTeX RDF |
|
Displaying result #1 - #100 of 294 (100 per page; Change: ) Pages: [ 1][ 2][ 3][ >>] |
|