Search results for "technology-mapping"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
47	Hannah Honghua Yang, D. F. Wong 0001	Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs.	ICCAD	1994	DBLP DOI BibTeX RDF
46	Jason Cong, Yean-Yow Hwang	Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	computer-aided design of VSLI, FPGA, synthesis, system design, decomposition, technology mapping, simplification, programmable logic, logic optimization, delay minimization
46	Shashidhar Thakur, D. F. Wong 0001	Series-parallel functions and FPGA logic module design.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	series-parallel technology mapping, tree-based technology mapping algorithm, universal logic modules, field programmable gate arrays
45	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	multi-output logic module, cellular automata array, design turn-around time, field programmability, rapid circuit realization, logic blocks, AND-XOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture
44	Peichen Pan, C. L. Liu 0001	Optimal clock period FPGA technology mapping for sequential circuits.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, retiming, technology mapping, look-up tables, logic replication, clock period, sequential synthesis
42	Deming Chen, Jason Cong, Fei Li 0003, Lei He 0001	Low-power technology mapping for FPGA architectures with dual supply voltages.	FPGA	2004	DBLP DOI BibTeX RDF	low-power FPGA, technology mapping, dual supply voltage
42	Jason Cong, Kirill Minkovich	Optimality study of logic synthesis for LUT-based FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	optimization, logic synthesis, technology mapping, Boolean logic, FPGA lookup table
41	Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang	A predictive distributed congestion metric and its application to technology mapping.	ISPD	2004	DBLP DOI BibTeX RDF	congestion prediction, technology mapping
39	Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan	Efficient SAT-based Boolean matching for FPGA technology mapping.	DAC	2006	DBLP DOI BibTeX RDF	FPGA technology mapping, Boolean satisfiability, Boolean matching
39	Uwe Hinsberger, Reiner Kolla	Optimal technology mapping for single output cells.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	optimal technology mapping, single output cells, DAG-mapping, minimum delay mapping, duplication-free mapping, logic duplication, AT-tradeoffs, LUT-FPGAs, field programmable gate arrays, delays, Boolean functions, Boolean functions, logic CAD, table lookup, cost functions, circuit optimisation, lookup table
38	Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness	Logic decomposition during technology mapping.	ICCAD	1995	DBLP DOI BibTeX RDF	Logic Decomposition, Logic Factorization, Logic Synthesis, Technology Mapping
38	Chi-Shong Wang, Chingwei Yeh	Performance-driven technology mapping with MSG partition and selective gate duplication.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	gate duplication, maximal super-gate, super-gate, dynamic programming, partition, matching, logic synthesis, directed acyclic graph, Technology mapping, covering
36	Taiga Takata, Yusuke Matsunaga	A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, technology mapping
36	Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky	Gain-based technology mapping for minimum runtime leakage under input vector uncertainty.	DAC	2006	DBLP DOI BibTeX RDF	leakage, technology mapping, logical effort
36	Min Zhao 0001, Sachin S. Sapatnekar	Technology mapping algorithms for domino logic.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	XOR/XNOR logic, dual-monotonic gates, parameterized library, phase assignment, synthesis, technology mapping, Domino logic
35	Felipe S. Marques 0001, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis	DAG based library-free technology mapping.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	library free synthesis, logic synthesis, technology mapping, switching theory, virtual libraries
35	Jason Cong, Hui Huang 0001, Xin Yuan 0005	Technology mapping and architecture evalution for k/m-macrocell-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	FPGA, technology mapping, CPLD, PLD
35	Bo Hu 0006, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska	Gain-based technology mapping for discrete-size cell libraries.	DAC	2003	DBLP DOI BibTeX RDF	technology mapping, logic effort, gain
35	Aiguo Lu, Guenter Stenz, Frank M. Johannes	Technology Mapping for Minimizing Gate and Routing Area.	DATE	1998	DBLP DOI BibTeX RDF	Routing, Technology Mapping, Area Optimization
34	Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar	An efficient technology mapping algorithm targeting routing congestion under delay constraints.	ISPD	2005	DBLP DOI BibTeX RDF	logic synthesis, technology mapping, routing congestion
34	Cheoljoo Jeong, Steven M. Nowick	Technology Mapping and Cell Merger for Asynchronous Threshold Networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
34	Jason Cong, Songjie Xu	Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
34	Mahesh Mehendale, M. K. Ram Prasad	AATMA: an algorithm for technology mapping for antifuse-based FPGAs.	VLSI Design	1995	DBLP DOI BibTeX RDF	AATMA, antifuse-based FPGAs, logic module structure, complex functions, signature-matching based approach, mapping quality, logic module architectures, field programmable gate arrays, directed graphs, combinational circuits, logic CAD, technology mapping, execution times
32	Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko	WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	area flow, cut enumeration, edge flow, FPGA, technology mapping
32	Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko	WireMap: FPGA technology mapping for improved routability.	FPGA	2008	DBLP DOI BibTeX RDF	area flow, cut enumeration, edge flow, FPGA, technology mapping
32	Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton	Improvements to technology mapping for LUT-based FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	area recovery, cut enumeration, lossless synthesis, FPGA, technology mapping
32	Chi-Chou Kao, Yen-Tai Lai	An efficient algorithm for finding the minimal-area FPGA technology mapping.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	partition, Logic synthesis, technology mapping, greedy method
32	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev	Decomposition and technology mapping of speed-independent circuits using Boolean relations.	ICCAD	1997	DBLP DOI BibTeX RDF	Boolean decomposition, decomposed logic sharing, design library, library matching, logic decomposition, logic resynthesis, signal insertion, two-input combinational gate, two-input sequential gate, optimization, technology mapping, circuit CAD, speed-independent circuits, netlist, complex gates, Boolean relations
32	Jason Cong, Yuzheng Ding	On area/depth trade-off in LUT-based FPGA technology mapping.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
32	Jason Cong, Kirill Minkovich	Optimality Study of Logic Synthesis for LUT-Based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
31	Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox	FPGA technology mapping with encoded libraries andstaged priority cuts.	FPGA	2009	DBLP DOI BibTeX RDF	priority cuts, fpga, synthesis, technology mapping
31	Hao Li, Srinivas Katkoori, Wai-Kei Mak	Power minimization algorithms for LUT-based FPGA technology mapping.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	FPGA, technology mapping, power optimization, Delay minimization
31	Vinícius P. Correia, André Inácio Reis	Advanced technology mapping for standard-cell generators.	SBCCI	2004	DBLP DOI BibTeX RDF	cell library, library-free, logic synthesis, technology mapping, complex gates
31	Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen	An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping.	ICCAD	1996	DBLP DOI BibTeX RDF	LUT-Based FPGA Technology Mapping, Area/Performance Trade-Off and Timing Driven FPGA Synthesis
31	Amit Chowdhary, John P. Hayes	Technology mapping for field-programmable gate arrays using integer programming.	ICCAD	1995	DBLP DOI BibTeX RDF	Field-programmable gate arrays (FPGAs), technology mapping, mixed integer linear programming (MILP), lookup tables, circuit partitioning
31	Shrirang K. Karandikar, Sachin S. Sapatnekar	Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
30	Joey Y. Lin, Deming Chen, Jason Cong	Optimal simultaneous mapping and clustering for FPGA delay optimization.	DAC	2006	DBLP DOI BibTeX RDF	clustering, FPGA, dynamic programming, technology mapping
30	Shashidhar Thakur, D. F. Wong 0001	Simultaneous area and delay minimum K-LUT mapping for K-exact networks.	ICCD	1995	DBLP DOI BibTeX RDF	area/delay minimum K-LUT mapping, K-exact networks, technology mapping problem, lookup table FPGAs, area minimization problem, K-bounded networks, delay minimization problem, flow-map algorithm, field programmable gate arrays, computational complexity, complexity, NP-complete, logic design, polynomial time algorithm, programmable logic arrays, table lookup, minimisation of switching nets
29	Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang	A predictive distributed congestion metric with application to technology mapping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
29	Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness	Logic decomposition during technology mapping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
28	Jason Cong, Hui Huang 0001	Depth optimal incremental mapping for field programmable gate arrays.	DAC	2000	DBLP DOI BibTeX RDF
28	Kang Yi, Seong Yong Ohm	A Fast and Exact Cell Matching Method for MUX-Based FPGA Technology Mapping.	ICCD	1999	DBLP DOI BibTeX RDF	Cell Matching, FPGA Technology Mapping, FPGA Synthesis
28	Jason Helge Anderson, Stephen Dean Brown	Technology Mapping for Large Complex PLDs.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
28	Jinan Lou, Amir H. Salek, Massoud Pedram	An exact solution to simultaneous technology mapping and linear placement problem.	ICCAD	1997	DBLP DOI BibTeX RDF	Combinational Logic Optimization (area, timing), Technology Mapping
28	Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones	Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM).	FCCM	2006	DBLP DOI BibTeX RDF
28	Jason Cong, Yean-Yow Hwang	Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
28	Jason Cong, Songjie Xu	Performance-driven technology mapping for heterogeneous FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
28	Per Larsson-Edefors	Technology mapping onto very-high-speed standard CMOS hardware.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
28	R. Manimegalai, A. Manoj Kumar, B. Jayaram 0002, V. Kamakoti 0001	MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks.	FPL	2004	DBLP DOI BibTeX RDF
27	Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider	A comparative study of CMOS gates with minimum transistor stacks.	SBCCI	2007	DBLP DOI BibTeX RDF	PTL, unateness, BDDs, technology mapping, switch theory, logical effort, CMOS gates
26	Cheoljoo Jeong, Steven M. Nowick	Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks.	ASYNC	2006	DBLP DOI BibTeX RDF
26	Shrirang K. Karandikar, Sachin S. Sapatnekar	Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
26	Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton	Improvements to Technology Mapping for LUT-Based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
25	Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun	Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits.	ASYNC	1998	DBLP DOI BibTeX RDF
25	Yifang Liu, Rupesh S. Shelar, Jiang Hu	Delay-optimal simultaneous technology mapping and placement with applications to timing optimization.	ICCAD	2008	DBLP DOI BibTeX RDF
25	Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu	Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring.	ISCAS	2007	DBLP DOI BibTeX RDF
25	Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown	FPGA technology mapping: a study of optimality.	DAC	2005	DBLP DOI BibTeX RDF	resynthesis optimization, FPGA, boolean satisfiability, lookup table, cone
25	Gang Chen 0020, Jason Cong	Simultaneous logic decomposition with technology mapping in FPGA designs.	FPGA	2001	DBLP DOI BibTeX RDF
25	Jason Cong, Yuzheng Ding	FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
25	Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki	A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays.	ICCAD	1994	DBLP DOI BibTeX RDF
25	Reinaldo A. Bergamaschi	SKOL: a system for logic synthesis and technology mapping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
25	Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic	Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
25	Jason Cong, Yuzheng Ding	On Nominal Delay Minimization in LUT-based FPGA Technology Mapping.	FPGA	1995	DBLP DOI BibTeX RDF
24	Sree Ganesan, Ranga Vemuri	A Methodology for Rapid Prototyping of Analog Systems.	ICCD	1999	DBLP DOI BibTeX RDF	rapid prototyping, technology mapping, placement and routing, FPAA, field-programmable analog arrays
24	Fung Yu Young, Chris C. N. Chu, D. F. Wong 0001	Generation of Universal Series-Parallel Boolean Functions.	J. ACM	1999	DBLP DOI BibTeX RDF	series-parallel Boolean functions, universal functions, FPGA, technology mapping
24	Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton	Factor cuts.	ICCAD	2006	DBLP DOI BibTeX RDF
24	Jason Cong, Kirill Minkovich	LUT-based FPGA technology mapping for reliability (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	logic synthesis, error analysis, windowing, technology mapping, don't cares, fpga lookup table
24	Jason Cong, Kirill Minkovich	LUT-based FPGA technology mapping for reliability.	DAC	2010	DBLP DOI BibTeX RDF	logic synthesis, error analysis, windowing, technology mapping, don't cares, FPGA lookup table
24	Taiga Takata, Yusuke Matsunaga	An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	FPGA, logic synthesis, technology mapping
24	Sree Ganesan, Ranga Vemuri	Technology Mapping and Retargeting for Field-Programmable Analog Arrays.	DATE	2000	DBLP DOI BibTeX RDF	Rapid prototyping Field-programmable analog arrays, Technology Mapping, Retargeting, FPAA
24	Ahmad S. Al-Mulhem, Alaaeldin Amin, Habib Youssef	Stochastic Evolution Algorithm For Technology Mapping.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Stochastic Evolution, FPGA, Logic Synthesis, Technology mapping, Boolean Network
24	Hai Zhou 0001, D. F. Wong 0001	An exact gate decomposition algorithm for low-power technology mapping.	ICCAD	1997	DBLP DOI BibTeX RDF	Gate Decomposition, Low Power, Technology Mapping
24	Peichen Pan, C. L. Liu 0001	Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance.	FPGA	1996	DBLP DOI BibTeX RDF	FPGAs, sequential circuits, retiming, technology mapping, look-up table, logic replication, clock period
24	Xiaoqing Wen, Kewal K. Saluja	A new method towards achieving global optimality in technology mapping.	ICCAD	1996	DBLP DOI BibTeX RDF	Combinational Logic Synthesis, Optimality, Technology Mapping
24	Aiguo Lu, Erik L. Dagless, Jonathan M. Saul	DART: delay and routability driven technology mapping for LUT based FPGAs.	ICCD	1995	DBLP DOI BibTeX RDF	DART, delay driven technology mapping, LUT based FPGAs, two-phased approach, routability directed delay-optimal mapping, stochastic routability analysis, delay-optimal mapping, field programmable gate arrays, delays, logic design, programmable logic arrays, table lookup, minimisation of switching nets
24	Stanley Habib, Quan Xu	Technology mapping algorithms for sequential circuits using look-up table based FPGAS.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	technology mapping algorithms, FPGAS, routing results, adjacent combinational parts, field programmable gate arrays, delays, sequential circuits, sequential circuits, logic CAD, network routing, flip-flops, flip-flops, circuit layout CAD, table lookup, time delay, look-up table
23	Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton	DAG-aware AIG rewriting a fresh look at combinational logic synthesis.	DAC	2006	DBLP DOI BibTeX RDF	NPN equivalence, and-inverter graphs, technology-independent logic synthesis, technology mapping
23	Seok-Bum Ko, Jien-Chung Lo	Efficient Realization of Parity Prediction Functions in FPGAs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	parity prediciton functions, Davio''s expansion, AND/XOR expressions, FPGA, technology mapping
23	Jae-Jin Kim, Hi-Seok Kim, Chi-Ho Lin	A new techology mapping for CPLD under the time constraint.	ASP-DAC	2001	DBLP DOI BibTeX RDF	feasible cluster, number of multi-level, technology mapping for CPLD, time constraint
22	Shigenobu Suzuki, Tatsushige Bitoh, Masao Kakimoto, Kazutoshi Takahashi, Takao Sugimoto	TRIP: An Automated Technology Mapping System.	DAC	1987	DBLP DOI BibTeX RDF
22	Maitrali Marik, Ajit Pal	Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs.	VLSI Design	2004	DBLP DOI BibTeX RDF
22	Seok-Bum Ko, Jien-Chung Lo	A Novel Technology Mapping Method for AND/XOR Expressions.	ISMVL	2003	DBLP DOI BibTeX RDF
22	Alireza Kaviani, Stephen Dean Brown	Technology mapping issues for an FPGA with lookup tables and PLA-like blocks.	FPGA	2000	DBLP DOI BibTeX RDF
22	K. K. Lee, D. F. Wong 0001	An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs.	ICCD	1999	DBLP DOI BibTeX RDF
22	Madhukar R. Korupolu, K. K. Lee, D. F. Wong 0001	Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs.	DAC	1998	DBLP DOI BibTeX RDF
22	Kirill Minkovich, Jason Cong	Mapping for better than worst-case delays in LUT-based FPGA designs.	FPGA	2008	DBLP DOI BibTeX RDF	better than worst-case, razor, switching probabilities, simulation, logic synthesis, technology mapping, FPGA lookup table
21	Deming Chen, Jason Cong	DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs.	ICCAD	2004	DBLP DOI BibTeX RDF
21	Jae-sun Seo, Igor L. Markov, Dennis Sylvester, David T. Blaauw	On the decreasing significance of large standard cells in technology mapping.	ICCAD	2008	DBLP DOI BibTeX RDF
21	Xing Wei, Juanjuan Chen, Qiang Zhou 0001, Yici Cai, Jinian Bian, Xianlong Hong	MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation.	FPL	2008	DBLP DOI BibTeX RDF
21	Sz-Cheng Huang, Jie-Hong Roland Jiang	A dynamic accuracy-refinement approach to timing-driven technology mapping.	ICCD	2008	DBLP DOI BibTeX RDF
21	Srini Krishnamoorthy, Russell Tessier	Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
21	Amit Chowdhary, John P. Hayes	General technology mapping for field-programmable gate arrays based on lookup tables.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	lookup tables (LUTs), multiple-LUT blocks, nonrooted trees, field-programmable gate arrays, mapping, synthesis, circuit partitioning, rooted trees, Basis
21	Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji	Technology mapping for high-performance static CMOS and pass transistor logic designs.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
21	Wolfgang Günther 0001, Rolf Drechsler	ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs.	EUROMICRO	2000	DBLP DOI BibTeX RDF
21	Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
21	Jason Cong, Songjie Xu	Technology Mapping for FPGAs with Embedded Memory Blocks.	FPGA	1998	DBLP DOI BibTeX RDF
21	Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar	DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
20	Jason Cong, Yuzheng Ding	Combinational logic synthesis for LUT based field programmable gate arrays.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	FPGA, routing, synthesis, system design, decomposition, technology mapping, simplification, programmable logic, power minimization, logic optimization, delay modeling, delay minimization, computer-aided design of VLSI, area minimization
19	Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar	Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
19	Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas	Global and local congestion optimization in technology mapping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF