Search results for "circuit"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
24	Christopher P. Silva	The double-Hook Attractor in Chua's Circuit: some analytical Results.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Alexander P. Kuznetsov, Sergey P. Kuznetsov, Igor R. Sataev, Leon O. Chua	Two-parameter Study of Transition to Chaos in Chua's Circuit: Renormalization Group, Universality and Scaling.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Ljupco Kocarev, K. Sean Halle, Kevin Eckert, Leon O. Chua	Experimental Observation of Antimonotonicity in Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Alexander I. Khibnik, Dirk Roose, Leon O. Chua	On periodic orbits and homoclinic bifurcations in Chua's Circuit with a smooth nonlinearity.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	G. A. Johnson, E. R. Hunt	Maintaining stability in Chua's Circuit Driven into regions of oscillation and Chaos.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Frank Böhme, Wolfgang Schwarz	Transformations of Circuits belonging to Chua's Circuit family into nonlinear feedback Loops Made of passive RC-filter and Active memoryless nonlinearity.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Vadim S. Anishchenko, Alexander B. Neiman, Leon O. Chua	Chaos-Chaos intermittency and 1/F noise in Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Bruno Rossetto	Chua's Circuit as a Slow-Fast Autonomous dynamical System.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Nikolai F. Rulkov, Alexander Volkovskii	Experimental Analysis of 1-d Maps from Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	René Lozi, Shigehiro Ushiki	The Theory of Confinors in Chua's Circuit: accurate Analysis of bifurcations and attractors.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Michael Peter Kennedy, Chai Wah Wu, Stanley Pau, James Tow	Digital signal Processor-based Investigation of Chua's Circuit family.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Xavier Rodet	Sound and Music from Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Edward J. Altman	Bifurcation Analysis of Chua's Circuit with Applications for low-Level Visual Sensing.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	G. A. Johnson, T. E. Tigner, E. R. Hunt	Controlling Chaos in Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Ladislav Pivka, Viktor Spány	Boundary surfaces and Basin bifurcations in Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Vadim S. Anishchenko, M. A. Safonova, Leon O. Chua	Stochastic resonance in Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Ray Brown	From the Chua Circuit to the generalized Chua Map.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Fan Zou, Josef A. Nossek	An Autonomous Chaotic Cellular Neural Network and Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Marc Genot	Applications of 1-d Map from Chua's Circuit: a Pictorial Guide.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Tom T. Hartley, Faramarz Mossayebi	Control of Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Roberto Genesio, Alberto Tesi	Distortion control of Chaotic Systems: the Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Rabinder N. Madan, Chai Wah Wu	Introduction to Experimental Chaos using Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	K. A. Lukin	High-frequency oscillations from Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	James Glover, Alistair Mees	Reconstructing the dynamics of Chua's Circuit.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	C. M. Blázquez, E. Tuma	Dynamics of Chua's Circuit in a Banach Space.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Adelheid I. Mahla, Álvaro G. Badan Palhares	Chua's Circuit with a discontinuous nonlinearity.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Claus Kahlert	The effects of Symmetry Breaking in Chua's Circuit and Related piecewise-linear dynamical Systems.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
24	Lee A. Belfore II, Amy B. Adcock, Ginger S. Watson	Introducing digital logic and electronics concepts in a game-like environment.	SpringSim	2009	DBLP BibTeX RDF	game based learning, computer engineering, digital logic
24	Yu Wang 0002, Xiaoming Chen 0003, Wenping Wang, Varsha Balakrishnan, Yu Cao 0001, Yuan Xie 0001, Huazhong Yang	On the efficacy of input Vector Control to mitigate NBTI effects and leakage power.	ISQED	2009	DBLP DOI BibTeX RDF
24	Kei Uchizawa, Rodney J. Douglas, Wolfgang Maass 0001	Energy Complexity and Entropy of Threshold Circuits.	ICALP (1)	2006	DBLP DOI BibTeX RDF
24	Tathagato Rai Dastidar, P. P. Chakrabarti 0001, Partha Ray	A synthesis system for analog circuits based on evolutionary search and topological reuse.	IEEE Trans. Evol. Comput.	2005	DBLP DOI BibTeX RDF
24	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik	A BIST scheme for RTL circuits based on symbolic testabilityanalysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
24	Ivan S. Kourtev, Eby G. Friedman	Clock skew scheduling for improved reliability via quadratic programming.	ICCAD	1999	DBLP DOI BibTeX RDF
24	Rajagopalan Srinivasan, Sandeep K. Gupta 0001, Melvin A. Breuer	Bounds on pseudoexhaustive test lengths.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
24	José Duato, Pedro López 0001, Sudhakar Yalamanchili	Deadlock- and Livelock-Free Routing Protocols for Wave Switching.	IPPS	1997	DBLP DOI BibTeX RDF
24	Kaushik De, Chitra Natarajan, Devi Nair, Prithviraj Banerjee	RSYN: a system for automated synthesis of reliable multilevel circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
23	Cong-Kha Pham	CMOS Schmitt Trigger Circuit with Controllable Hysteresis Using Logical Threshold Voltage Control Circuit.	ACIS-ICIS	2007	DBLP DOI BibTeX RDF
23	Lyudmila Zinchenko, Heinz Mühlenbein, Victor Kureichik, Thilo Mahnig	A Comparison of Different Circuit Representations for Evolutionary Analog Circuit Design.	ICES	2003	DBLP DOI BibTeX RDF
23	Gensoh Matsubara, Nobuhiro Ide	A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit.	ASYNC	1997	DBLP DOI BibTeX RDF	floating point, division, square root, self-timed
23	William Adams, Warren A. Hunt Jr., Damir Jamsek	Verisym: Verifying Circuits by Symbolic Simulation.	Formal Methods Syst. Des.	2003	DBLP DOI BibTeX RDF	circuit extraction, formal property checking, memory verification, symbolic simulation
23	Qadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri	Low power startup circuits for voltage and current reference with zero steady state current.	ISLPED	2003	DBLP DOI BibTeX RDF	low power integrated circuits, startup circuit, voltage reference, current reference
23	Kazuo Iwama, Hiroki Morizumi, Jun Tarui	Negation-Limited Complexity of Parity and Inverters.	Algorithmica	2009	DBLP DOI BibTeX RDF	Negation-limited circuit, Parity function, Inversion complexity, Gate elimination, Circuit complexity, Inverter
23	Luís Mendes, Eduardo José Solteiro Pires, Paulo B. de Moura Oliveira, José António Tenreiro Machado, Nuno M. Fonseca Ferreira, João Caldinhas Vaz, Maria João Rosário	Design Optimization of Radio Frequency Discrete Tuning Varactors.	EvoWorkshops	2009	DBLP DOI BibTeX RDF	automated circuit synthesis, radio frequency integrated circuits, Evolutionary algorithms, analog circuit design
23	Fei Qiao, Huazhong Yang, Gang Huang, Hui Wang 0004	Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	low-swing interface, differential signaling, tapered-buffer, interconnect, asynchronous circuit, low power circuit
23	Yiming Li 0005, Chih-Hong Hwang, Ta-Ching Yeh, Tien-Yeh Li	Large-scale atomistic approach to random-dopant-induced characteristic variability in nanoscale CMOS digital and high-frequency integrated circuits.	ICCAD	2008	DBLP DOI BibTeX RDF	device variability, high frequency circuit, random dopant, timing, digital circuit, fluctuation
23	Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi	A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	Minimum area retiming, application of mincost network flow, longpath circuit constraints, minimum delay padding, shortpath circuit constraints
23	Eric W. MacDonald, Nur A. Touba	Testing domino circuits in SOI technology.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	silicon-on-insulator, SOI technology, dynamic circuit styles, fault modeling analysis, overall fault coverage, parasitic bipolar leakage, CMOS logic, logic testing, integrated circuit testing, automatic testing, fault simulation, CMOS logic circuits, leakage currents, domino circuits
23	Luís Guerra e Silva, Luís Miguel Silveira, João Marques-Silva 0001	Algorithms for Solving Boolean Satisfiability in Combinational Circuits.	DATE	1999	DBLP DOI BibTeX RDF	Circuit Delay Computation, Test Pattern Generation, Boolean Satisfiability, Circuit Satisfiability
23	Josef Eckmüller, Martin Groepl, Helmut E. Graeb	Hierarchical Characterization of Analog Integrated CMOS Circuits.	DATE	1998	DBLP DOI BibTeX RDF	hierarchical characterization, circuit class, topology independent, transistor pairs, circuit performances, functional constraints
23	Charles E. Molnar, Ian W. Jones, William S. Coates, Jon K. Lexau	A FIFO Ring Performance Experiment.	ASYNC	1997	DBLP DOI BibTeX RDF	FIFO ring performance experiment, high-speed FIFO circuit, asynchronous FIFO, clocked shift register, pulse-like protocol, two-phase clocked design, MOSIS, internal FIFO stages, 3.3 V, 1.67 to 4.8 V, 0.6 micron, pipeline, SPICE, data path, hSpice, circuit delays
23	Abby A. Ilumoka	Modular artificial neural network models for simulation and optimization of VLSI circuits.	Annual Simulation Symposium	1997	DBLP DOI BibTeX RDF	modular artificial neural network models, MANN, process level parameters, optimization, circuit analysis computing, VLSI circuits, modular neural network, circuit performance
23	Alvin Jee, F. Joel Ferguson	A methodolgy for characterizing cell testability.	VTS	1997	DBLP DOI BibTeX RDF	cell testability, stuck-at fault coverage, IC quality, physical design for testability, metric, integrated circuit design, integrated circuit design, DPM, manufacturing defects
23	Franco Fummi, Donatella Sciuto	Implicit test pattern generation constrained to cellular automata embedding.	VTS	1997	DBLP DOI BibTeX RDF	implicit test pattern generation, cellular automata embedding, test sequence identification, autonomous finite state machine, off-line self-testable circuit, BIST strategy, deterministic test sequences, MCNC benchmarks, controller, built-in self test, stuck-at faults, ASIC design, circuit under test
23	Jong Won Park, David T. Harper III	An Efficient Memory System for the SIMD Construction of a Gaussian Pyramid.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	SIMD memory architecture, address calculating circuit, data routing circuit, Gaussian pyramid algorithms, image processing, parallel memory systems
23	Zhuxing Zhao, Zhongcheng Li, Yinghua Min	Waveform Polynomial Manipulation Using Bdds.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	waveform polynomial manipulation, design verification and test, middle size circuits, complexity, data structure, high level synthesis, timing, logic design, combinational circuit, logic synthesis, binary decision diagram, directed acyclic graph, digital circuit, Boolean process
23	Rajesh Ramadoss, Michael L. Bushnell	Test generation for mixed-signal devices using signal flow graphs.	VLSI Design	1996	DBLP DOI BibTeX RDF	mixed-signal devices, reverse simulation approach, component tolerances, analog input sinusoids, test generation results, analog backtrace method, high-order analog circuits, fault diagnosis, test generation, integrated circuit testing, automatic testing, circuit analysis computing, mixed analogue-digital integrated circuits, signal flow graphs, signal flow graphs, nonlinear circuits
23	Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell	Functional test generation for path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults
23	Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama	Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic.	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued arithmetic integrated circuits, dual-rail source-coupled logic, multiple-valued current-mode MOS integrated circuit, high-speed arithmetic systems, multiple-valued source-coupled logic circuit, dual-rail complementary inputs, pipelined multiplier, 54 bit, 200 MHz, 0.8 mum, 1.5 V, CMOS logic circuits, multiplying circuits, multivalued logic circuits, current-mode logic, pipeline arithmetic
23	Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng	Automatic synthesis of gate-level timed circuits with choice.	ARVLSI	1995	DBLP DOI BibTeX RDF	gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates
23	Enrico Macii, Massimo Poncino	Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	worst-case power consumption, symbolic neural networks, gate level description, symbolic domain, algebraic decision diagrams, graph specification, delays, combinational circuits, combinational circuits, logic CAD, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, energy dissipation
23	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Resynthesis for sequential circuits designed with a specified initial state.	VTS	1995	DBLP DOI BibTeX RDF	specified initial state, retiming method, redundancy removal method, resynthesized circuit, input sequences, logic optimisation, timing, redundancy, sequential circuits, logic CAD, flip-flops, flip-flops, circuit optimisation, synchronous sequential circuits
23	Srimat T. Chakradhar	Optimum retiming of large sequential circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	optimum retiming, large sequential circuits, unit delay model, optimum clock period, path graph, VLSI, linear programming, delays, timing, integer programming, sequential circuits, logic CAD, integer linear program, flip-flops, circuit CAD, fast algorithm, integrated logic circuits, circuit optimisation, VLSI circuits, linear program relaxation
23	Imtiaz P. Shaik, Michael L. Bushnell	A graph approach to DFT hardware placement for robust delay fault BIST.	VLSI Design	1995	DBLP DOI BibTeX RDF	graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI
22	Stanislaw J. Piestrak	Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	embedded circuit, inverter-free circuit, totally self-testing circuit, concurrent error detection, Berger code, self-testing checker, two-rail code
22	Richard Cleve, John Watrous	Fast parallel circuits for the quantum Fourier transform.	FOCS	2000	DBLP DOI BibTeX RDF	fast parallel circuits, quantum Fourier transform, QFT, circuit depth, constant error, depth bound, polynomial size, classical polynomial-time processing, depth complexity, arbitrary modulus, lower bound, theorem proving, quantum computing, Fourier transforms, upper bound, circuit complexity, circuit complexity, quantum circuits, factoring algorithm
22	Wu-Tung Cheng	Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	test logic, deep Sub-Micron technologies, scan-based ATPG, test application cost, test development, VLSI, CAD, logic testing, built-in self test, system on chip, SoC, automatic test pattern generation, automatic test pattern generation, ATPG, BIST, VLSI design, integrated circuit design, circuit CAD, VLSI testing, embedded memories, test quality, integrated circuit economics
22	Chin-Te Kao, Sam Wu, Jwu E. Chen	A case study of failure analysis and guardband determination for a 64M-bit DRAM.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	guardband determination, prevention strategy, test derivation, test cost, 64 Mbit, integrated circuit testing, yield, DRAM, failure analysis, failure analysis, test selection, DRAM chips, product quality, integrated circuit yield, integrated circuit economics
22	M. Miegler, Werner Wolz	Development of test programs in a virtual test environment.	VTS	1996	DBLP DOI BibTeX RDF	test programs development, virtual test environment, quality-assured mixed-signal test programs, standard test description language, VTML, Virtual Test Modelling Language, standardized description models, test system resources, equivalent simulation models, VLSI, integrated circuit testing, design for testability, integrated circuit design, circuit CAD, automatic test software
22	Egor S. Sogomonyan, Michael Gössel	Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems.	VTS	1996	DBLP DOI BibTeX RDF	circuit feedback, concurrently self-testing embedded checker, ultra-reliable fault-tolerant system, parity codes, design, monitoring, built-in self test, integrated circuit testing, linear feedback shift register, error detection codes, error detection code, shift registers, arithmetic codes, Berger codes, duplication codes, integrated circuit reliability, corrector
22	Michel Renovell, P. Huc, Yves Bertrand	Serial transistor network modeling for bridging fault simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	serial transistor network modeling, voting model, biased voting model, relative transistor strength, SPICE pre-simulation, fault simulation procedure, CMOS logic, fault diagnosis, logic testing, integrated circuit testing, digital simulation, circuit analysis computing, CMOS logic circuits, SPICE, integrated circuit modelling, bridging fault simulation
22	Hassan Ihs, Christian Dufaza	Tolerance DC bands of CMOS operational amplifier.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	tolerance DC bands, CMOS operational amplifier, DC node voltages, data tolerance bands, foundry process fluctuations, DC branch current, OA, supply voltage, catastrophic defects, transistor connections, optimization, fault diagnosis, integrated circuit testing, fault detection, fault model, fault simulation, circuit optimisation, operational amplifiers, integrated circuit modelling, transistor size, CMOS analogue integrated circuits, design parameters
22	Hannah Honghua Yang, D. F. Wong 0001	New algorithms for min-cut replication in partitioned circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	Hyper-MAMC, VLSI circuit partitioning, k-way partition, k-way partitioned digraph, min-cut replication, partitioned circuits, VLSI, optimal algorithm, circuit layout CAD, hypergraphs, VLSI layout, digraphs, circuit layout
22	Sasan Iman, Massoud Pedram	Two-level logic minimization for low power.	ICCAD	1995	DBLP DOI BibTeX RDF	Power Prime Implicants, low power two-level logic minimization, minimum covering problem, minimum power solution, static CMOS circuits, logic design, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, circuit optimisation, minimisation of switching nets
22	X. Cai, Keith Nabors, Jacob K. White 0001	Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics.	ARVLSI	1995	DBLP DOI BibTeX RDF	piecewise constant techniques, permittivity, Galerkin techniques, multipole-accelerated capacitance extraction, multiple dielectrics, arbitrary piecewise-constant dielectric medium, IC interconnections, VLSI, VLSI, integrated circuit design, circuit CAD, boundary-elements methods, boundary element method, capacitance, integrated circuit interconnections, Galerkin method, capacitance extraction, 3D structures
22	Robert Pearson	Linking fabrication and parametric testing to VLSI design courses.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	VLSI design courses, simulation model parameters, VLSI, integrated circuit testing, integrated circuit design, integrated circuit modelling, educational courses, device models, parametric testing, electronic engineering education
22	Enric Pastor, Jordi Cortadella, Oriol Roig	A new look at the conditions for the synthesis of speed-independent circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	gate-level synthesis, gate library constraint, fan-in reduction, VLSI, logic design, logic CAD, integrated circuit design, circuit CAD, integrated logic circuits, circuit optimisation, optimization techniques, speed-independent circuits
22	James M. Varanelli, James P. Cohoon	A two-stage simulated annealing methodology.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	two-stage simulated annealing methodology, starting temperature determination, problem suite, VLSI, VLSI, formal method, simulated annealing, CAD, integrated circuit design, circuit CAD, optimization problems, circuit optimisation, running time, adaptive schedules, stop criterion
22	Nestoras Tzartzanis, William C. Athas	Design and analysis of a low-power energy-recovery adder.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	energy-recovery adder, frequency range, VLSI, VLSI, delays, logic CAD, circuit analysis computing, integrated circuit design, adders, CMOS logic circuits, CMOS logic circuits, circuit CAD, SPICE, SPICE simulation, delay time, energy dissipation
22	Nikolaos G. Bourbakis, Mohammad Mortazavi	An efficient building block layout methodology for compact placement.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	building block layout methodology, compact placement, synthesis placement, GEOMETRIA, geometric reshapings, VLSI regulation, functional performance, connection lines, occupied chip area, neighboring relations, dead space, open holes, channels merging process, legal overlapping, VLSI, formal languages, formal language, network routing, circuit layout CAD, compaction, global routing, integrated circuit layout, integrated circuit interconnections, local routing
22	Masahiro Nagamatu, Shakeel Ismail, Torao Yanaru	Lagrangian method for wire routing of layout design.	ANNES	1995	DBLP DOI BibTeX RDF	wire routing, layout design, LSI layout design, continuous valued constrained optimization problem, continuous valued wires, dynamic equations, small switchbox routing problems, rip-up reroute maze router, neural nets, network routing, circuit layout CAD, circuit optimisation, integrated circuit layout, large scale integration, neurocomputing, Lagrangian method
22	Peter Lidén, Peter Dahlgren	Switch-level modeling of transistor-level stuck-at faults.	VTS	1995	DBLP DOI BibTeX RDF	transistor-level stuck-at faults, switch-level algorithms, fault modeling capability, fault detection measures, confidence degradation, unknown output values, uncertainty quantification, node model, fault diagnosis, logic testing, integrated circuit testing, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, switch-level modeling
22	O. A. Petlin, Stephen B. Furber	Scan testing of micropipelines.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines
22	Alessandro Bogliolo, Maurizio Damiani	Synthesis of combinational circuits with special fault-handling capabilitie.	VTS	1995	DBLP DOI BibTeX RDF	combinational circuit synthesis, fault-handling capabilities, internal faults, multilevel logic optimization process, logic testing, redundancy, redundancy, design for testability, logic design, combinational circuits, logic CAD, multivalued logic, circuit optimisation, self-checking circuits, circuit reliability, fault-tolerant circuits
22	B. Hamdi, Hakim Bederr, Michael Nicolaidis	A tool for automatic generation of self-checking data paths.	VTS	1995	DBLP DOI BibTeX RDF	self-checking data paths, ALUs, shifters, double rail checkers, logic testing, built-in self test, microprocessors, adders, circuit CAD, multipliers, microcontrollers, register files, circuit design, CAD tools, automatic generation, automatic test software, dividers, circuit testing, parity checkers
22	Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani	Optimal algorithms for planar over-the-cell routing in the presence of obstacles.	VLSI Design	1995	DBLP DOI BibTeX RDF	planar over-the-cell routing, arbitrary shaped obstacles, two layer standard cell design methodology, ALGO-PROBES algorithm, VLSI, network routing, optimal algorithms, circuit layout CAD, circuit optimisation, integrated circuit layout
22	P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya	VLSI floorplan generation and area optimization using AND-OR graph search.	VLSI Design	1995	DBLP DOI BibTeX RDF	VLSI floorplan generation, AND-OR graph search, rectangular dualization, minimum-area floorplan, optimal sizing, heuristic search method, top-down first phase, search effort, bottom-up polynomial-time algorithm, nonslicible floorplans, VLSI, graph theory, circuit layout CAD, circuit optimisation, integrated circuit interconnections, aspect ratios, area optimization, adjacency graph
22	Keumog Ahn, Sartaj Sahni	NP-Hard Module Rotation Problems.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	NP-hard module rotation problems, circuit modules, performance, computational complexity, circuit layout CAD, circuit layout CAD, routability
22	Lindsay Kleeman	The Jitter Model for Metastability and Its Application to Redundant Synchronizers.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	jitter model, redundant synchronizers, circuit noise, CMOS D-type flip-flop, bistable device, simulation, circuit analysis computing, flip-flops, SPICE, CMOS integrated circuits, integrated logic circuits, reliability analysis, metastability, timing model, circuit analysis
22	Takeshi Yamakawa, Tsutomu Miki	The Current Mode Fuzzy Logic Integrated Circuits Fabricated by the Standard CMOS Process.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	semicustom IC, fuzzy computer, fuzzy integrated circuit, fuzzy logic array, fuzzy logic building block, MOS current mirror, ratioless circuit, Current mode circuit
22	Michal Servít	Hazard Correction in Synchronous Sequential Circuits.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	Double-rank circuit, flip-flop memory, hazard correction, single-rank circuit, synchronous sequential circuit
22	Satyendra R. Datla, Mitchell A. Thornton, David W. Matula	A Low Power High Performance Radix-4 Approximate Squaring Circuit.	ASAP	2009	DBLP DOI BibTeX RDF
22	David Grant, Guy G. Lemieux	Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	Automated development tools, hardware-supporting software, testing, graph algorithms, design automation, place and route
22	Tracey Y. Zhou, Dian Zhou, Hua Zhang 0019, Xinyue Niu	Foundational-circuit-based spice simulation.	ISCAS	2008	DBLP DOI BibTeX RDF
22	Matthew Webb, Hua Tang	Analog design retargeting by design knowledge reuse and circuit synthesis.	ISCAS	2008	DBLP DOI BibTeX RDF
22	B. P. Harish, Navakanta Bhat, Mahesh B. Patil	On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
22	Zhe Zhang, MaoLiu Lin, QingHua Xu, JiuBin Tan	Accurate and robust estimation of phase error and its uncertainty of 50 GHz bandwidth sampling circuit.	Sci. China Ser. F Inf. Sci.	2007	DBLP DOI BibTeX RDF	phase error, sampling oscilloscope, uncertainty
22	Seonyoung Lee, Kyeongsoon Cho	Design of Transform and Quantization Circuit for Multi-Standard Integrated Video Decoder.	SiPS	2007	DBLP DOI BibTeX RDF
22	Xuewen Xia, Yuanxiang Li 0001, Weiqin Ying, Lei Chen	Automated Design Approach for Analog Circuit Using Genetic Algorithm.	International Conference on Computational Science (4)	2007	DBLP DOI BibTeX RDF	Evolutionary algorithms, Evolving hardware, Electronic Design Automation
22	Hsiang-Hui Huang, Ching-Hwa Cheng	Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit.	VTS	2007	DBLP DOI BibTeX RDF
22	Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy 0001	Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design.	DATE	2006	DBLP DOI BibTeX RDF