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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 29152 publication records. Showing 29152 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
34 | Heonchul Park, Viktor K. Prasanna |
A Fast Algorithm for Performing Vector Quantization and its VLSI Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 91-94, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
34 | A. Bandyopadhyay, P. R. Verma, A. B. Bhattacharyya, M. J. Zarabi |
LATCHSIM - A Lath-Up Simulator in VLSI CAD Environment for CMOS and BiCMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 339-342, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
34 | M. K. Kidambi, Akhilesh Tyagi, Mohammed R. Madani, Magdy A. Bayoumi |
Parameterized Modeling of Open-Circuit Critical Volume for Three-Dimensional Defects in VLSI Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 333-338, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri |
Architecture for VLSI Design of CA Based Byte Error Correcting Code Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 283-286, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
34 | P. Pal Chowdhury, R. Barua |
Cellular Automata Based VLSI Architecture for Computing Multiplication and Inverses in GF (2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 279-282, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Dinesh Bhatia, Ramesh Rajagopalan, Srinivas Katkoori |
Hierarchical Reconfiguration of VLSI/WSI Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 349-352, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
34 | S. K. Lahiri 0001, M. K. Das, A. Das Gupta, I. Manna |
3D Effects in VLSI/ULSI MOSFETs: A Novel Analytical Approach to Model Threshold Voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 328-332, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Arup K. Bhattacharya, Syed S. Haider |
A VLSI Architecture of an Inverse Discrete Cosine Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 87-90, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Mourad B. Takla, Donald W. Bouldin, Daniel B. Koch |
Early Exploration of the Multi-Dimensional VLSI Design Space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 413-416, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Indradeep Ghosh, Bandana Majumdar |
Design of an Application Specific VLSI Chip for Image Rotation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 275-278, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Feng-Ming Yang, Stefan Wolter, Rainer Laur |
VLSI Architecture for HDTV Motion Estimation Based on Block-Matching Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 287-290, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Joseph B. Costello |
On the Brink of a New Era in VLSI Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 3, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
34 | Himanshu S. Mazumdar |
A Multilayered Feed Forward Neural Network Suitable for VLSI Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 108, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Sunil D. Sherlekar |
Export of VLSI Design and CAD: Present and Future. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 264, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
34 | G. Pannerselvam, A. Sarkar, Subir Bandyopadhyay, Graham A. Jullien |
Area Efficient VLSI Design with Cells of Controllable Complexity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 218-221, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
34 | S. Bapat, James P. Cohoon |
A Parallel VLSI Circuit Layout Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 236-241, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Mario Kovac, N. Ranganathan, M. Varanasi |
SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 25-30, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Osamu Karatsu |
On the History and Future Detecion of VLSI Design and CAD - Japanese Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 3-4, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin |
A Massively Parallel, Micro-Grained VLSI Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 250-255, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Krishnaiyan Thulasiraman, Prasad R. Chalasani, Parimala Thulasiraman, M. A. Comeau |
Parallel Network Primal-Dual Method on a Shared Memory Multiprocessor and a Unified Approach to VLSI Layout Compaction and Wire Balancing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 242-245, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Kanti Prasad, Aditya Goel |
Preparing Engineers to Meet the Challenges of the 21st Century Through VLSI Education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 114-117, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Biswadip Mitra, Parimal Pal Chaudhuri |
A Scheme for Synthesizing Testable VLSI Designs with Minimum Area Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 112, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Pradip Bose, John-David Wellman |
MIPS-Driven Early Design and Analysis of VLSI CPU Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 256-259, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
34 | V. Visvanathan, Nibedita Mohanty, S. Ramanathan |
An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 166-171, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Aditya Agrawal, P. V. Srinivas, Gade Sreenivas, Uttiya Dasgupta |
LATCHECK: A Latchup Checker for VLSI Layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 230-235, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
34 | N. Ranganathan, Rajiv Mehrotra, S. Kurji |
A CMOS VLSI Chip for Motion Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Fifth International Conference on VLSI Design, VLSI Design 1992, Bangalore, India, January 4-7, 1992, pp. 209-214, 1992, IEEE Computer Society, 0-8186-2465-5. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
34 | Jaisimha Bannur |
A Designer's Perspective on VLSI Tools and Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Fifth International Conference on VLSI Design, VLSI Design 1992, Bangalore, India, January 4-7, 1992, pp. 315-319, 1992, IEEE Computer Society, 0-8186-2465-5. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
34 | M. V. V. Satyanarayana |
Structured Construction of VLSI Circuits Using Adjacency Lists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Fifth International Conference on VLSI Design, VLSI Design 1992, Bangalore, India, January 4-7, 1992, pp. 374-375, 1992, IEEE Computer Society, 0-8186-2465-5. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
34 | Pei-Yung Hsiao, Lih-Der Jang |
Using a Balanced Quad List Quad Tree to Speed Up a Hierarchical VLSI Compaction Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Fifth International Conference on VLSI Design, VLSI Design 1992, Bangalore, India, January 4-7, 1992, pp. 370-371, 1992, IEEE Computer Society, 0-8186-2465-5. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
34 | Pei-Yung Hsiao, Chiao-Yi Lin, Chia-Chun Tsai |
Minimum Partition for the Space Region of VLSI Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Fifth International Conference on VLSI Design, VLSI Design 1992, Bangalore, India, January 4-7, 1992, pp. 273-276, 1992, IEEE Computer Society, 0-8186-2465-5. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
34 | Kanad Ghose, Arun Gupta |
Scalable, Pipelined, Cmos VLSI Content Addressable Memory Chips - Architecture And Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Fifth International Conference on VLSI Design, VLSI Design 1992, Bangalore, India, January 4-7, 1992, pp. 161-166, 1992, IEEE Computer Society, 0-8186-2465-5. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
34 | Mokhtar Aboelaze, De-Lei Lee, Benjamin W. Wah |
A programmable VLSI array with constant I/O pins. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 205-210, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
34 | D. K. Arvind 0001 |
Distributed simulation of parallel VLSI architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 285-298, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
34 | Patrice Quinton, Yves Robert |
Algorithms and Parallel VLSI Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms and Parallel VLSI Architectures ![In: Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991, pp. 1-10, 1991, Elsevier, 0-444-89153-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
34 | Hussein M. Alnuweiri |
A New Class of Optimal Bounded-Degree VLSI Sorting Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(6), pp. 746-752, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
VLSI sorting networks, optimal VLSI sorters, rotate-sort, enumeration-sort, reduced-area, K-shuffle layouts, VLSI, optimisation, logic design, sorting, time complexity, bounded-degree |
34 | Philip S. Liu, Tzay Y. Young |
VLSI Array Design Under Constraint of Limited I/O Bandwidth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(12), pp. 1160-1170, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
matrix inversion array, multiplication array, reconfigurable VLSI array, image processing, performance analysis, signal processing, VLSI architecture, VLSI implementation, Design constraints |
33 | Arijit Mondal, Partha Pratim Chakrabarti, Pallab Dasgupta |
Accelerating Synchronous Sequential Circuits Using an Adaptive Clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 176-181, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
VLSI, CAD, delays, Timing, sequential circuits, Timing optimization |
33 | Shailendra Jain, Vasantha Erraguntla, Sriram R. Vangal, Yatin Vasant Hoskote, Nitin Borkar, Tulasi Mandepudi, V. P. Karthik |
A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 252-257, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
multiply-accumulate, Fused and continuous MAC, VLSI, Floating-point |
33 | Xiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiaodong Yang, Sangwoo Kim, Stephan Mueller, Hendrik T. Mau, Lawrence T. Pileggi |
A fast simulation approach for inductive effects of VLSI interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 108-111, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
inductance, circuit simulation, VLSI interconnects |
33 | Tong Zhang 0002, Keshab K. Parhi |
On the high-speed VLSI implementation of errors-and-erasures correcting reed-solomon decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002, pp. 89-93, 2002, ACM, 1-58113-462-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
erasure, VLSI architectures, Reed-Solomon codes, Berlekamp-Massey algorithm |
33 | Kuo-Hsing Cheng, Shun-Wen Cheng |
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 155-159, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
full-swing logic, Low power design, VLSI design, hybrid logic, prime implicant |
33 | Santanu Dutta, Deepak Singh, Essam Abu-Ghoush, Vijay Mehra |
Architecture and Implementation of a High-Definition Video Co-Processor for Digital Television Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 350-359, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
ATSC standard, picture processing, VLSI design, video processing, Digital television, HDTV, media processor |
33 | Bedabrata Pain, Guang Yang 0003, Monico Ortiz, Kenneth McCarty, Julie Heynssens, Bruce Hancock, Thomas Cunningham, Chris Wrigley, Charlie Ho |
A Single-Chip Programmable Digital CMOS Imager with Enhanced Low-Light Detection Capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 342-349, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low-power VLSI, camera-on-a-chip, digital imager, CMOS imager, APS, active pixel sensor |
33 | Yehea I. Ismail, Eby G. Friedman, José Luis Neves |
Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 39-44, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Lossless Transmission Lines, VLSI, Dynamic, Power, CMOS, Inductance, Short-circuit |
33 | Jim E. Crenshaw, Majid Sarrafzadeh |
Low Power Driven Scheduling and Binding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 406-413, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
high level synthesis, low power design, design automation, VLSI CAD |
33 | Saeid Sadeghi-Emamchaie, Graham A. Jullien, Vassil S. Dimitrov, William C. Miller |
Digital Arithmetic Using Analog Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 202-207, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Cellular Neural Networks, Double-Base Number System, Analog VLSI |
33 | R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili |
A Low Power Floating Point Accumulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 330-, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
low power CMOS, Digital arithmetic, VLSI architecture, floating point |
33 | Tony Tsang |
A Compilable Read-Only-Memory Library for ASIC Deep Sub-micron Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 490-494, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
circuit technique, VLSI, compiler, ASIC, deep sub-micron, ROM |
33 | Giuseppe Ascia, Vincenzo Catania |
A Framework for a Parallel Architecture Dedicated to Soft Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 318-321, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
VLSI, Parallel Architecture, Soft Computing |
33 | Sandip Das 0001, Susmita Sur-Kolay, Bhargab B. Bhattacharya |
Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 65-, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
nonslicible floorplan, switchbox, Manhattan-diagonal model, channel, VLSI routing |
33 | Sam S. Appleton, Shannon V. Morton, Michael J. Liebelt |
A new method for asynchronous pipeline control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 13-15 March 1997, Urbana, IL, USA, pp. 100-104, 1997, IEEE Computer Society, 0-8186-7904-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
asynchronous pipeline control, static logic control, dynamic logic control, flow controlled asynchronous method, asynchronous circuits, VLSI architecture |
33 | Jianzhong Shi, Akash Randhar, Dinesh Bhatia |
Macro Block Based FPGA Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 21-26, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
macro block based FPGA floorplanning, FPGA based designs, very large designs, performance driven designs, constraint-based FPGA floorplanning, flexible macro blocks, fixed macro blocks, input constraint set, topological placement, FPGA architectural constraints, large benchmark examples, VLSI floorplanning, heuristic algorithm, integrated circuit layout, ASIC design |
33 | Masato Edahiro, Richard J. Lipton |
Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 143-147, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
VLSI, CAD, Placement, Layout, Buffer, Clock |
33 | S. Ramanathan, V. Visvanathan |
A systolic architecture for LMS adaptive filtering with minimal adaptation delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 286-289, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
LMS adaptive filtering, minimal adaptation delay, convergence behaviour, function preserving transformations, SFG representation, carry-save arithmetic, systolic folded pipelined architecture, VLSI, delays, systolic arrays, pipeline processing, adaptive filters, digital filters, digital signal processing chips, convergence of numerical methods, systolic architecture, signal flow graphs, signal flow graph, least mean squares methods, LMS algorithm |
33 | Vamsi Krishna, Abdel Ejnioui, N. Ranganathan |
A tree matching chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 280-285, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
tree matching chip, online interpreter systems, linear systolic array algorithms, fixed size linear array, Cadence design tools, parallel algorithms, VLSI, compilers, object recognition, image recognition, systolic arrays, digital signal processing chips, code optimization, 3D object recognition, vision systems, systolic architecture |
33 | Santanu Chattopadhyay, S. Mitra 0001, Parimal Pal Chaudhuri |
Cellular automata based architecture of a database query processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 320-321, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
cellular automata based architecture, database query processor, programmable query processor chip, fast database access, multiple attractor cellular automata, class-relation storage, true/false classifier, classification, VLSI, query processing, relational databases, relational database, cellular automata, microprocessor chips, database machines |
33 | Enric Pastor, Jordi Cortadella, Oriol Roig |
A new look at the conditions for the synthesis of speed-independent circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 230-, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
gate-level synthesis, gate library constraint, fan-in reduction, VLSI, logic design, logic CAD, integrated circuit design, circuit CAD, integrated logic circuits, circuit optimisation, optimization techniques, speed-independent circuits |
33 | Manjit Borah, Robert Michael Owens, Mary Jane Irwin |
Fast algorithm for performance-oriented Steiner routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 198-203, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
performance-oriented Steiner routing, fast routing algorithm, Elmore delay minimisation, layout generators, computational complexity, VLSI, data structures, data structures, delays, iterative methods, network routing, circuit layout CAD, integrated circuit layout, iterative techniques |
33 | O. A. Petlin, Stephen B. Furber |
Scan testing of asynchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 224-229, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits |
33 | J. T. Mowchenko, Y. Yang |
Optimizing wiring space in slicing floorplans. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 54-, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
wiring space optimisation, slicing floorplans, net density, sibling rectangles, circuit modules, routed layouts, VLSI, heuristic, network routing, circuit layout CAD, circuit optimisation, integrated circuit layout, branch and bound algorithm, wiring, IC layout |
33 | Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges |
Statistical estimation of delay fault detectabilities and fault grading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 184-187, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
delay fault detectabilities, fault grading, STAFAN, transition observabilities, fanout stems, fanout free region, gate line transition controllabilities, VLSI, fault diagnosis, logic testing, logic testing, statistical analysis, fault coverage, benchmark circuits, statistical estimation |
33 | Sanjay Khanna, Shaodi Gao, Krishnaiyan Thulasiraman |
Parallel hierarchical global routing for general cell layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 212-, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
parallel hierarchical global routing, general cell layout, hierarchical decomposition strategy, network flow optimization, parallel algorithms, parallel processing, VLSI, integer programming, integer programming, routing algorithm, network routing, circuit layout CAD, integrated circuit layout, shared-memory machine |
33 | Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh |
A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 192-, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
integrated circuit technology, n-guardring, p-guardring, latchup prevention, remote transient, I/O buffer n-channel transistor, 2D device simulator, TMA-MEDICI, substrate resistance, 0.8 micron, VLSI, circuit analysis computing, CMOS integrated circuits, CMOS technology, transients, steady state simulation |
33 | S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta |
A single chip, pipelined, cascadable, multichannel, signal processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 150-155, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
delay lines, single chip signal processor, cascadable processor, multichannel signal processor, programmable delay line, memory mapped peripheral, online diagnostics, shadow accumulators, double metal CMOS process, 144 pin CPGA, VLSI, timing, pipeline processing, digital signal processing chips, pipelined processor, CMOS digital integrated circuits, array multipliers, DSP architecture, 2 micron |
33 | Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani |
Optimal algorithms for planar over-the-cell routing in the presence of obstacles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 3-7, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
planar over-the-cell routing, arbitrary shaped obstacles, two layer standard cell design methodology, ALGO-PROBES algorithm, VLSI, network routing, optimal algorithms, circuit layout CAD, circuit optimisation, integrated circuit layout |
33 | Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri |
Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 57-62, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
multi-output logic module, cellular automata array, design turn-around time, field programmability, rapid circuit realization, logic blocks, AND-XOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture |
33 | Priyadarsan Patra, Donald S. Fussell |
Fully asynchronous, robust, high-throughput arithmetic structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 141-145, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
fully asynchronous structures, high-throughput arithmetic structures, bit serial adders, scaleability, VLSI, digital arithmetic, asynchronous circuits, adders, integrated logic circuits, multiplying circuits, RSA cryptosystems, delay-insensitive, bit serial multipliers |
33 | A. Pal, R. K. Gorai, V. V. S. S. Raju |
Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 63-68, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
multiplexing equipment, multiplexer network, ratio parameters, Actel ACT1, MCNC benchmark problems, field programmable gate arrays, FPGAs, VLSI, Boolean functions, Boolean functions, logic design, iterative methods, combinational circuits, combinational circuits, logic CAD, multiplexing, search space, tree network, iterative approach |
33 | Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross |
Efficient variable ordering and partial representation algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 81-86, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
partial representation algorithm, ordered partial decision diagrams, information-theoretic criteria, CAD problems, VLSI, data structures, data structures, entropy, Boolean functions, Boolean function, logic CAD, BDDs, variable ordering, truth table |
33 | Alok Kumar, Anshul Kumar, M. Balakrishnan |
Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 75-80, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
heuristic search based approach, VITAL, partial binding sub-tasks, design styles, component types, scheduling, scheduling, computational complexity, VLSI, high level synthesis, search problems, cost estimates, allocation, computation time, binding, design constraints, solution quality, data path synthesis, benchmark designs |
33 | Jin-Tai Yan, Pei-Yung Hsiao |
A new fuzzy-clustering-based approach for two-way circuit partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 359-364, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
fuzzy-clustering-based approach, two-way circuit partitioning, circuit netlist, undirected edge-weighted graph, tree net model, clustering distance, area information, area-balanced constraints, circuit benchmarks, VLSI, simulated annealing, network topology, trees (mathematics), fuzzy set theory, logic partitioning, fuzzy c-means clustering, fuzzy memberships |
33 | Jason P. Hurst, Adit D. Singh |
A differential built-in current sensor design for high speed IDDQ testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 419-423, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
built-in current sensor design, high speed IDDQ testing, differential architecture, quiescent current detection, BIST environment, n-well technology, MOSIS, 31.25 MHz, VLSI, built-in self test, built-in self-test, integrated circuit testing, design for testability, integrated circuit design, CMOS digital integrated circuits, electric current measurement, 2 micron, electric sensing devices |
33 | Debabrata Ghosh, Soumitra Kumar Nandy |
Wave pipelined architecture folding: a method to achieve low power and low area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 184-, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
wave pipelined architecture folding, clock-free wave pipelining scheme, chip area reduction, VLSI, low power design, logic design, pipeline processing, integrated circuit design, digital integrated circuits |
33 | Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal |
Functional test generation for non-scan sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 47-52, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
nonscan sequential circuits, functional test vectors, growth and disappearance fault model, complete stuck fault coverage, algebraic transformations, synthesized FSMs, VLSI, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, automatic testing, functional test generation |
33 | Laxmi N. Bhuyan |
Introduction to session R2 (session overiew): advanced computer architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Conference on Computer Science ![In: Proceedings of the 13th ACM Annual Conference on Computer Science, New Orleans, Louisiana, USA, 1985, pp. 98-99, 1985, ACM, 0-89791-150-4. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
32 | David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil |
Fault Emulation for Dependability Evaluation of VLSI Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(4), pp. 422-431, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu 0001 |
Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 71-77, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Minoru Watanabe, Fuminori Kobayashi |
A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 268-273, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu 0001 |
Interconnect implications of growth-based structural models for VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 99-106, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Yuhai Ma, Wanchun Shi |
Intelligent Analysis and Off-Line Debugging of VLSI Device Test Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(3), pp. 273-293, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
error type, off-line debugging environment, FCE (Fuzzy Comprehensive Evaluation), reference set, evaluation space, evaluation factor, evaluation remark, test entity, relevance coefficient, fuzzy set, fuzzy relation, test program |
32 | Arturo I. Concepcion, David R. Millican |
Developing the VLSI laboratory for the computer architecture course. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCSE ![In: Proceedings of the 27th SIGCSE Technical Symposium on Computer Science Education, SIGCSE 1996, Philadelphia, Pennsylvania, USA, February 15-17, 1996, pp. 47-52, 1996, ACM, 0-89791-757-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
31 | Wayne H. Wolf, I. Burak Özer, Tiehan Lv |
VLSI Systems for Embedded Video. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 25-26 April 2002, Pittsburgh, PA, USA, pp. 3-6, 2002, IEEE Computer Society, 0-7695-1486-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Wu Jigang, Thambipillai Srikanthan, Xiaodong Wang |
Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(10), pp. 1387-1400, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Degradable VLSI array, algorithm, routing, reconfiguration, faulttolerance |
31 | Wu Jigang, Thambipillai Srikanthan |
Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(3), pp. 243-253, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Degradable VLSI array, fault tolerance, algorithms, routing, reconfiguration |
31 | Shuenn-Yuh Lee, Chia-Chyang Chen |
VLSI implementation of programmable FFT architectures for OFDM communication system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCMC ![In: Proceedings of the International Conference on Wireless Communications and Mobile Computing, IWCMC 2006, Vancouver, British Columbia, Canada, July 3-6, 2006, pp. 893-898, 2006, ACM, 1-59593-306-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FFT processor, low power, VLSI architecture |
31 | Rong Zheng 0002, Zhenglin Wang, Kamal E. Alameh |
An Opto-VLSI Based Tunable Fiber Ring Laser. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 350-353, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Opto-VLSI processing, Erbium-doped fiber (EDF), tunable fiber laser |
31 | Wu Jigang, Heiko Schröder, Thambipillai Srikanthan |
New Architecture and Algorithms for Degradable VLSI/WSI Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COCOON ![In: Computing and Combinatorics, 8th Annual International Conference, COCOON 2002, Singapore, August 15-17, 2002, Proceedings, pp. 181-190, 2002, Springer, 3-540-43996-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Degradable VLSI/WSI array, fault-tolerance, reconfiguration, NP-completeness, greedy algorithm |
31 | Chris C. N. Chu, D. F. Wong 0001 |
VLSI Circuit Performance Optimization by Geometric Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 105(1-4), pp. 37-60, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
unary geometric programming, circuit performance optimization, VLSI design, Lagrangian relaxation, gate sizing, transistor sizing, wire sizing |
31 | Hyeongseok Yu, Byung Wook Kim, Yeon Gon Cho, Jun-Dong Cho, Jea Woo Kim, Hyun Cheol Park, Ki Won Lee |
Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modern. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 404-408, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Decision feedback equalizer, reusable VLSI implementation, FIR filter, QAM |
31 | Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang |
Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 173-184, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
real-time, Wireless communications, DSP, VLSI architecture, wideband CDMA, channel estimation |
31 | Lu Chen, Bingxue Shi |
CMOS PWM VLSI Implementation of Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN (3) ![In: Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, IJCNN 2000, Neural Computing: New Challenges and Perspectives for the New Millennium, Como, Italy, July 24-27, 2000, Volume 3, pp. 485-488, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Neural Network, VLSI, Pulse Width Modulation |
31 | Ignacio S. McQuirk, Berthold K. P. Horn, Hae-Seung Lee, John L. Wyatt Jr. |
Estimating the Focus of Expansion in Analog VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Vis. ![In: Int. J. Comput. Vis. 28(3), pp. 261-277, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
passive navigation, analog VLSI, motion vision, focus of expansion |
31 | Ian D. Walker, Joseph R. Cavallaro |
Parallel VLSI architectures for real-time kinematics of redundant robots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 9(1-2), pp. 25-43, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
cordic arithmetic, kinematic redundancy, VLSI, Robot kinematics, pseudoinverse |
31 | Hart Anway, Greg Farnham, Rebecca Reid |
PLINT layout system for VLSI chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 449-452, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
IC placement, IC routing, macrocell layout, standard cell layout, VLSI, computer-aided design, IC layout |
31 | Sheu-Chih Cheng, Hsueh-Ming Hang |
The Impact of Rate Control Algorithms on Video Codec Hardware Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (2) ![In: Proceedings 1997 International Conference on Image Processing, ICIP '97, Santa Barbara, California, USA, October 26-29, 1997, pp. 807-810, 1997, IEEE Computer Society, 0-8186-8183-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
rate control algorithms, video codec hardware design, system-level VLSI design, optimal rate-distortion performance, internal buffer size, performance, video coding, image quality, VLSI implementation, video codecs, DCT coefficients, picture quality, hardware cost |
31 | Weisheng Chong, Masanori Hariyama, Michitaka Kameyama |
Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 243-248, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Bassam Shaer |
Concurrent Pseudo-Exhaustive Testing of Combinational VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 289-290, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | José A. B. Fortes |
Future Challenges in VLSI Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 5-7, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Peter Rieder, Sven Simon 0001, Christian V. Schimpfle |
Application Specific Efficient VLSI Architectures for Orthogonal Single- and Multiwavelet Transforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 21(2), pp. 77-90, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Jinn-Wang Yeh, Wen-Jiunn Cheng, Chein-Wei Jen |
VASS - A VLSI array system synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 12(2), pp. 135-158, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
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