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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 15571 occurrences of 3952 keywords
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Found 29152 publication records. Showing 29152 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
34 | Heonchul Park, Viktor K. Prasanna |
A Fast Algorithm for Performing Vector Quantization and its VLSI Implementation. |
VLSI Design |
1994 |
DBLP DOI BibTeX RDF |
|
34 | A. Bandyopadhyay, P. R. Verma, A. B. Bhattacharyya, M. J. Zarabi |
LATCHSIM - A Lath-Up Simulator in VLSI CAD Environment for CMOS and BiCMOS Circuits. |
VLSI Design |
1994 |
DBLP DOI BibTeX RDF |
|
34 | M. K. Kidambi, Akhilesh Tyagi, Mohammed R. Madani, Magdy A. Bayoumi |
Parameterized Modeling of Open-Circuit Critical Volume for Three-Dimensional Defects in VLSI Processing. |
VLSI Design |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri |
Architecture for VLSI Design of CA Based Byte Error Correcting Code Decoders. |
VLSI Design |
1994 |
DBLP DOI BibTeX RDF |
|
34 | P. Pal Chowdhury, R. Barua |
Cellular Automata Based VLSI Architecture for Computing Multiplication and Inverses in GF (2m). |
VLSI Design |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Dinesh Bhatia, Ramesh Rajagopalan, Srinivas Katkoori |
Hierarchical Reconfiguration of VLSI/WSI Arrays. |
VLSI Design |
1994 |
DBLP DOI BibTeX RDF |
|
34 | S. K. Lahiri 0001, M. K. Das, A. Das Gupta, I. Manna |
3D Effects in VLSI/ULSI MOSFETs: A Novel Analytical Approach to Model Threshold Voltage. |
VLSI Design |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Arup K. Bhattacharya, Syed S. Haider |
A VLSI Architecture of an Inverse Discrete Cosine Transform. |
VLSI Design |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Mourad B. Takla, Donald W. Bouldin, Daniel B. Koch |
Early Exploration of the Multi-Dimensional VLSI Design Space. |
VLSI Design |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Indradeep Ghosh, Bandana Majumdar |
Design of an Application Specific VLSI Chip for Image Rotation. |
VLSI Design |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Feng-Ming Yang, Stefan Wolter, Rainer Laur |
VLSI Architecture for HDTV Motion Estimation Based on Block-Matching Algorithm. |
VLSI Design |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Joseph B. Costello |
On the Brink of a New Era in VLSI Design. |
VLSI Design |
1994 |
DBLP BibTeX RDF |
|
34 | Himanshu S. Mazumdar |
A Multilayered Feed Forward Neural Network Suitable for VLSI Implementation. |
VLSI Design |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Sunil D. Sherlekar |
Export of VLSI Design and CAD: Present and Future. |
VLSI Design |
1993 |
DBLP BibTeX RDF |
|
34 | G. Pannerselvam, A. Sarkar, Subir Bandyopadhyay, Graham A. Jullien |
Area Efficient VLSI Design with Cells of Controllable Complexity. |
VLSI Design |
1993 |
DBLP DOI BibTeX RDF |
|
34 | S. Bapat, James P. Cohoon |
A Parallel VLSI Circuit Layout Methodology. |
VLSI Design |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Mario Kovac, N. Ranganathan, M. Varanasi |
SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division. |
VLSI Design |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Osamu Karatsu |
On the History and Future Detecion of VLSI Design and CAD - Japanese Perspective. |
VLSI Design |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin |
A Massively Parallel, Micro-Grained VLSI Architecture. |
VLSI Design |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Krishnaiyan Thulasiraman, Prasad R. Chalasani, Parimala Thulasiraman, M. A. Comeau |
Parallel Network Primal-Dual Method on a Shared Memory Multiprocessor and a Unified Approach to VLSI Layout Compaction and Wire Balancing. |
VLSI Design |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Kanti Prasad, Aditya Goel |
Preparing Engineers to Meet the Challenges of the 21st Century Through VLSI Education. |
VLSI Design |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Biswadip Mitra, Parimal Pal Chaudhuri |
A Scheme for Synthesizing Testable VLSI Designs with Minimum Area Overhead. |
VLSI Design |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Pradip Bose, John-David Wellman |
MIPS-Driven Early Design and Analysis of VLSI CPU Chips. |
VLSI Design |
1993 |
DBLP DOI BibTeX RDF |
|
34 | V. Visvanathan, Nibedita Mohanty, S. Ramanathan |
An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters. |
VLSI Design |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Aditya Agrawal, P. V. Srinivas, Gade Sreenivas, Uttiya Dasgupta |
LATCHECK: A Latchup Checker for VLSI Layouts. |
VLSI Design |
1993 |
DBLP DOI BibTeX RDF |
|
34 | N. Ranganathan, Rajiv Mehrotra, S. Kurji |
A CMOS VLSI Chip for Motion Detection. |
VLSI Design |
1992 |
DBLP DOI BibTeX RDF |
|
34 | Jaisimha Bannur |
A Designer's Perspective on VLSI Tools and Methodology. |
VLSI Design |
1992 |
DBLP DOI BibTeX RDF |
|
34 | M. V. V. Satyanarayana |
Structured Construction of VLSI Circuits Using Adjacency Lists. |
VLSI Design |
1992 |
DBLP DOI BibTeX RDF |
|
34 | Pei-Yung Hsiao, Lih-Der Jang |
Using a Balanced Quad List Quad Tree to Speed Up a Hierarchical VLSI Compaction Scheme. |
VLSI Design |
1992 |
DBLP DOI BibTeX RDF |
|
34 | Pei-Yung Hsiao, Chiao-Yi Lin, Chia-Chun Tsai |
Minimum Partition for the Space Region of VLSI Layout. |
VLSI Design |
1992 |
DBLP DOI BibTeX RDF |
|
34 | Kanad Ghose, Arun Gupta |
Scalable, Pipelined, Cmos VLSI Content Addressable Memory Chips - Architecture And Implementation. |
VLSI Design |
1992 |
DBLP DOI BibTeX RDF |
|
34 | Mokhtar Aboelaze, De-Lei Lee, Benjamin W. Wah |
A programmable VLSI array with constant I/O pins. |
Algorithms and Parallel VLSI Architectures |
1991 |
DBLP BibTeX RDF |
|
34 | D. K. Arvind 0001 |
Distributed simulation of parallel VLSI architectures. |
Algorithms and Parallel VLSI Architectures |
1991 |
DBLP BibTeX RDF |
|
34 | Patrice Quinton, Yves Robert |
Algorithms and Parallel VLSI Architectures. |
Algorithms and Parallel VLSI Architectures |
1991 |
DBLP BibTeX RDF |
|
34 | Hussein M. Alnuweiri |
A New Class of Optimal Bounded-Degree VLSI Sorting Networks. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
VLSI sorting networks, optimal VLSI sorters, rotate-sort, enumeration-sort, reduced-area, K-shuffle layouts, VLSI, optimisation, logic design, sorting, time complexity, bounded-degree |
34 | Philip S. Liu, Tzay Y. Young |
VLSI Array Design Under Constraint of Limited I/O Bandwidth. |
IEEE Trans. Computers |
1983 |
DBLP DOI BibTeX RDF |
matrix inversion array, multiplication array, reconfigurable VLSI array, image processing, performance analysis, signal processing, VLSI architecture, VLSI implementation, Design constraints |
33 | Arijit Mondal, Partha Pratim Chakrabarti, Pallab Dasgupta |
Accelerating Synchronous Sequential Circuits Using an Adaptive Clock. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
VLSI, CAD, delays, Timing, sequential circuits, Timing optimization |
33 | Shailendra Jain, Vasantha Erraguntla, Sriram R. Vangal, Yatin Vasant Hoskote, Nitin Borkar, Tulasi Mandepudi, V. P. Karthik |
A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
multiply-accumulate, Fused and continuous MAC, VLSI, Floating-point |
33 | Xiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiaodong Yang, Sangwoo Kim, Stephan Mueller, Hendrik T. Mau, Lawrence T. Pileggi |
A fast simulation approach for inductive effects of VLSI interconnects. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
inductance, circuit simulation, VLSI interconnects |
33 | Tong Zhang 0002, Keshab K. Parhi |
On the high-speed VLSI implementation of errors-and-erasures correcting reed-solomon decoders. |
ACM Great Lakes Symposium on VLSI |
2002 |
DBLP DOI BibTeX RDF |
erasure, VLSI architectures, Reed-Solomon codes, Berlekamp-Massey algorithm |
33 | Kuo-Hsing Cheng, Shun-Wen Cheng |
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
full-swing logic, Low power design, VLSI design, hybrid logic, prime implicant |
33 | Santanu Dutta, Deepak Singh, Essam Abu-Ghoush, Vijay Mehra |
Architecture and Implementation of a High-Definition Video Co-Processor for Digital Television Applications. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
ATSC standard, picture processing, VLSI design, video processing, Digital television, HDTV, media processor |
33 | Bedabrata Pain, Guang Yang 0003, Monico Ortiz, Kenneth McCarty, Julie Heynssens, Bruce Hancock, Thomas Cunningham, Chris Wrigley, Charlie Ho |
A Single-Chip Programmable Digital CMOS Imager with Enhanced Low-Light Detection Capability. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
low-power VLSI, camera-on-a-chip, digital imager, CMOS imager, APS, active pixel sensor |
33 | Yehea I. Ismail, Eby G. Friedman, José Luis Neves |
Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
Lossless Transmission Lines, VLSI, Dynamic, Power, CMOS, Inductance, Short-circuit |
33 | Jim E. Crenshaw, Majid Sarrafzadeh |
Low Power Driven Scheduling and Binding. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
high level synthesis, low power design, design automation, VLSI CAD |
33 | Saeid Sadeghi-Emamchaie, Graham A. Jullien, Vassil S. Dimitrov, William C. Miller |
Digital Arithmetic Using Analog Arrays. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
Cellular Neural Networks, Double-Base Number System, Analog VLSI |
33 | R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili |
A Low Power Floating Point Accumulator. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
low power CMOS, Digital arithmetic, VLSI architecture, floating point |
33 | Tony Tsang |
A Compilable Read-Only-Memory Library for ASIC Deep Sub-micron Applications. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
circuit technique, VLSI, compiler, ASIC, deep sub-micron, ROM |
33 | Giuseppe Ascia, Vincenzo Catania |
A Framework for a Parallel Architecture Dedicated to Soft Computing. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
VLSI, Parallel Architecture, Soft Computing |
33 | Sandip Das 0001, Susmita Sur-Kolay, Bhargab B. Bhattacharya |
Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
nonslicible floorplan, switchbox, Manhattan-diagonal model, channel, VLSI routing |
33 | Sam S. Appleton, Shannon V. Morton, Michael J. Liebelt |
A new method for asynchronous pipeline control. |
Great Lakes Symposium on VLSI |
1997 |
DBLP DOI BibTeX RDF |
asynchronous pipeline control, static logic control, dynamic logic control, flow controlled asynchronous method, asynchronous circuits, VLSI architecture |
33 | Jianzhong Shi, Akash Randhar, Dinesh Bhatia |
Macro Block Based FPGA Floorplanning. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
macro block based FPGA floorplanning, FPGA based designs, very large designs, performance driven designs, constraint-based FPGA floorplanning, flexible macro blocks, fixed macro blocks, input constraint set, topological placement, FPGA architectural constraints, large benchmark examples, VLSI floorplanning, heuristic algorithm, integrated circuit layout, ASIC design |
33 | Masato Edahiro, Richard J. Lipton |
Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model. |
Great Lakes Symposium on VLSI |
1996 |
DBLP DOI BibTeX RDF |
VLSI, CAD, Placement, Layout, Buffer, Clock |
33 | S. Ramanathan, V. Visvanathan |
A systolic architecture for LMS adaptive filtering with minimal adaptation delay. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
LMS adaptive filtering, minimal adaptation delay, convergence behaviour, function preserving transformations, SFG representation, carry-save arithmetic, systolic folded pipelined architecture, VLSI, delays, systolic arrays, pipeline processing, adaptive filters, digital filters, digital signal processing chips, convergence of numerical methods, systolic architecture, signal flow graphs, signal flow graph, least mean squares methods, LMS algorithm |
33 | Vamsi Krishna, Abdel Ejnioui, N. Ranganathan |
A tree matching chip. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
tree matching chip, online interpreter systems, linear systolic array algorithms, fixed size linear array, Cadence design tools, parallel algorithms, VLSI, compilers, object recognition, image recognition, systolic arrays, digital signal processing chips, code optimization, 3D object recognition, vision systems, systolic architecture |
33 | Santanu Chattopadhyay, S. Mitra 0001, Parimal Pal Chaudhuri |
Cellular automata based architecture of a database query processor. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
cellular automata based architecture, database query processor, programmable query processor chip, fast database access, multiple attractor cellular automata, class-relation storage, true/false classifier, classification, VLSI, query processing, relational databases, relational database, cellular automata, microprocessor chips, database machines |
33 | Enric Pastor, Jordi Cortadella, Oriol Roig |
A new look at the conditions for the synthesis of speed-independent circuits. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
gate-level synthesis, gate library constraint, fan-in reduction, VLSI, logic design, logic CAD, integrated circuit design, circuit CAD, integrated logic circuits, circuit optimisation, optimization techniques, speed-independent circuits |
33 | Manjit Borah, Robert Michael Owens, Mary Jane Irwin |
Fast algorithm for performance-oriented Steiner routing. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
performance-oriented Steiner routing, fast routing algorithm, Elmore delay minimisation, layout generators, computational complexity, VLSI, data structures, data structures, delays, iterative methods, network routing, circuit layout CAD, integrated circuit layout, iterative techniques |
33 | O. A. Petlin, Stephen B. Furber |
Scan testing of asynchronous sequential circuits. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits |
33 | J. T. Mowchenko, Y. Yang |
Optimizing wiring space in slicing floorplans. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
wiring space optimisation, slicing floorplans, net density, sibling rectangles, circuit modules, routed layouts, VLSI, heuristic, network routing, circuit layout CAD, circuit optimisation, integrated circuit layout, branch and bound algorithm, wiring, IC layout |
33 | Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges |
Statistical estimation of delay fault detectabilities and fault grading. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
delay fault detectabilities, fault grading, STAFAN, transition observabilities, fanout stems, fanout free region, gate line transition controllabilities, VLSI, fault diagnosis, logic testing, logic testing, statistical analysis, fault coverage, benchmark circuits, statistical estimation |
33 | Sanjay Khanna, Shaodi Gao, Krishnaiyan Thulasiraman |
Parallel hierarchical global routing for general cell layout. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
parallel hierarchical global routing, general cell layout, hierarchical decomposition strategy, network flow optimization, parallel algorithms, parallel processing, VLSI, integer programming, integer programming, routing algorithm, network routing, circuit layout CAD, integrated circuit layout, shared-memory machine |
33 | Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh |
A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
integrated circuit technology, n-guardring, p-guardring, latchup prevention, remote transient, I/O buffer n-channel transistor, 2D device simulator, TMA-MEDICI, substrate resistance, 0.8 micron, VLSI, circuit analysis computing, CMOS integrated circuits, CMOS technology, transients, steady state simulation |
33 | S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta |
A single chip, pipelined, cascadable, multichannel, signal processor. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
delay lines, single chip signal processor, cascadable processor, multichannel signal processor, programmable delay line, memory mapped peripheral, online diagnostics, shadow accumulators, double metal CMOS process, 144 pin CPGA, VLSI, timing, pipeline processing, digital signal processing chips, pipelined processor, CMOS digital integrated circuits, array multipliers, DSP architecture, 2 micron |
33 | Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani |
Optimal algorithms for planar over-the-cell routing in the presence of obstacles. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
planar over-the-cell routing, arbitrary shaped obstacles, two layer standard cell design methodology, ALGO-PROBES algorithm, VLSI, network routing, optimal algorithms, circuit layout CAD, circuit optimisation, integrated circuit layout |
33 | Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri |
Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
multi-output logic module, cellular automata array, design turn-around time, field programmability, rapid circuit realization, logic blocks, AND-XOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture |
33 | Priyadarsan Patra, Donald S. Fussell |
Fully asynchronous, robust, high-throughput arithmetic structures. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
fully asynchronous structures, high-throughput arithmetic structures, bit serial adders, scaleability, VLSI, digital arithmetic, asynchronous circuits, adders, integrated logic circuits, multiplying circuits, RSA cryptosystems, delay-insensitive, bit serial multipliers |
33 | A. Pal, R. K. Gorai, V. V. S. S. Raju |
Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
multiplexing equipment, multiplexer network, ratio parameters, Actel ACT1, MCNC benchmark problems, field programmable gate arrays, FPGAs, VLSI, Boolean functions, Boolean functions, logic design, iterative methods, combinational circuits, combinational circuits, logic CAD, multiplexing, search space, tree network, iterative approach |
33 | Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross |
Efficient variable ordering and partial representation algorithm. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
partial representation algorithm, ordered partial decision diagrams, information-theoretic criteria, CAD problems, VLSI, data structures, data structures, entropy, Boolean functions, Boolean function, logic CAD, BDDs, variable ordering, truth table |
33 | Alok Kumar, Anshul Kumar, M. Balakrishnan |
Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
heuristic search based approach, VITAL, partial binding sub-tasks, design styles, component types, scheduling, scheduling, computational complexity, VLSI, high level synthesis, search problems, cost estimates, allocation, computation time, binding, design constraints, solution quality, data path synthesis, benchmark designs |
33 | Jin-Tai Yan, Pei-Yung Hsiao |
A new fuzzy-clustering-based approach for two-way circuit partitioning. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
fuzzy-clustering-based approach, two-way circuit partitioning, circuit netlist, undirected edge-weighted graph, tree net model, clustering distance, area information, area-balanced constraints, circuit benchmarks, VLSI, simulated annealing, network topology, trees (mathematics), fuzzy set theory, logic partitioning, fuzzy c-means clustering, fuzzy memberships |
33 | Jason P. Hurst, Adit D. Singh |
A differential built-in current sensor design for high speed IDDQ testing. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
built-in current sensor design, high speed IDDQ testing, differential architecture, quiescent current detection, BIST environment, n-well technology, MOSIS, 31.25 MHz, VLSI, built-in self test, built-in self-test, integrated circuit testing, design for testability, integrated circuit design, CMOS digital integrated circuits, electric current measurement, 2 micron, electric sensing devices |
33 | Debabrata Ghosh, Soumitra Kumar Nandy |
Wave pipelined architecture folding: a method to achieve low power and low area. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
wave pipelined architecture folding, clock-free wave pipelining scheme, chip area reduction, VLSI, low power design, logic design, pipeline processing, integrated circuit design, digital integrated circuits |
33 | Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal |
Functional test generation for non-scan sequential circuits. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
nonscan sequential circuits, functional test vectors, growth and disappearance fault model, complete stuck fault coverage, algebraic transformations, synthesized FSMs, VLSI, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, automatic testing, functional test generation |
33 | Laxmi N. Bhuyan |
Introduction to session R2 (session overiew): advanced computer architectures. |
ACM Conference on Computer Science |
1985 |
DBLP DOI BibTeX RDF |
|
32 | David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil |
Fault Emulation for Dependability Evaluation of VLSI Systems. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu 0001 |
Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Minoru Watanabe, Fuminori Kobayashi |
A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. |
ARC |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu 0001 |
Interconnect implications of growth-based structural models for VLSI circuits. |
SLIP |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Yuhai Ma, Wanchun Shi |
Intelligent Analysis and Off-Line Debugging of VLSI Device Test Programs. |
J. Electron. Test. |
1999 |
DBLP DOI BibTeX RDF |
error type, off-line debugging environment, FCE (Fuzzy Comprehensive Evaluation), reference set, evaluation space, evaluation factor, evaluation remark, test entity, relevance coefficient, fuzzy set, fuzzy relation, test program |
32 | Arturo I. Concepcion, David R. Millican |
Developing the VLSI laboratory for the computer architecture course. |
SIGCSE |
1996 |
DBLP DOI BibTeX RDF |
|
31 | Wayne H. Wolf, I. Burak Özer, Tiehan Lv |
VLSI Systems for Embedded Video. |
ISVLSI |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Wu Jigang, Thambipillai Srikanthan, Xiaodong Wang |
Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
Degradable VLSI array, algorithm, routing, reconfiguration, faulttolerance |
31 | Wu Jigang, Thambipillai Srikanthan |
Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
Degradable VLSI array, fault tolerance, algorithms, routing, reconfiguration |
31 | Shuenn-Yuh Lee, Chia-Chyang Chen |
VLSI implementation of programmable FFT architectures for OFDM communication system. |
IWCMC |
2006 |
DBLP DOI BibTeX RDF |
FFT processor, low power, VLSI architecture |
31 | Rong Zheng 0002, Zhenglin Wang, Kamal E. Alameh |
An Opto-VLSI Based Tunable Fiber Ring Laser. |
DELTA |
2006 |
DBLP DOI BibTeX RDF |
Opto-VLSI processing, Erbium-doped fiber (EDF), tunable fiber laser |
31 | Wu Jigang, Heiko Schröder, Thambipillai Srikanthan |
New Architecture and Algorithms for Degradable VLSI/WSI Arrays. |
COCOON |
2002 |
DBLP DOI BibTeX RDF |
Degradable VLSI/WSI array, fault-tolerance, reconfiguration, NP-completeness, greedy algorithm |
31 | Chris C. N. Chu, D. F. Wong 0001 |
VLSI Circuit Performance Optimization by Geometric Programming. |
Ann. Oper. Res. |
2001 |
DBLP DOI BibTeX RDF |
unary geometric programming, circuit performance optimization, VLSI design, Lagrangian relaxation, gate sizing, transistor sizing, wire sizing |
31 | Hyeongseok Yu, Byung Wook Kim, Yeon Gon Cho, Jun-Dong Cho, Jea Woo Kim, Hyun Cheol Park, Ki Won Lee |
Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modern. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
Decision feedback equalizer, reusable VLSI implementation, FIR filter, QAM |
31 | Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang |
Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers. |
ASAP |
2000 |
DBLP DOI BibTeX RDF |
real-time, Wireless communications, DSP, VLSI architecture, wideband CDMA, channel estimation |
31 | Lu Chen, Bingxue Shi |
CMOS PWM VLSI Implementation of Neural Network. |
IJCNN (3) |
2000 |
DBLP DOI BibTeX RDF |
Neural Network, VLSI, Pulse Width Modulation |
31 | Ignacio S. McQuirk, Berthold K. P. Horn, Hae-Seung Lee, John L. Wyatt Jr. |
Estimating the Focus of Expansion in Analog VLSI. |
Int. J. Comput. Vis. |
1998 |
DBLP DOI BibTeX RDF |
passive navigation, analog VLSI, motion vision, focus of expansion |
31 | Ian D. Walker, Joseph R. Cavallaro |
Parallel VLSI architectures for real-time kinematics of redundant robots. |
J. Intell. Robotic Syst. |
1994 |
DBLP DOI BibTeX RDF |
cordic arithmetic, kinematic redundancy, VLSI, Robot kinematics, pseudoinverse |
31 | Hart Anway, Greg Farnham, Rebecca Reid |
PLINT layout system for VLSI chips. |
DAC |
1985 |
DBLP DOI BibTeX RDF |
IC placement, IC routing, macrocell layout, standard cell layout, VLSI, computer-aided design, IC layout |
31 | Sheu-Chih Cheng, Hsueh-Ming Hang |
The Impact of Rate Control Algorithms on Video Codec Hardware Design. |
ICIP (2) |
1997 |
DBLP DOI BibTeX RDF |
rate control algorithms, video codec hardware design, system-level VLSI design, optimal rate-distortion performance, internal buffer size, performance, video coding, image quality, VLSI implementation, video codecs, DCT coefficients, picture quality, hardware cost |
31 | Weisheng Chong, Masanori Hariyama, Michitaka Kameyama |
Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Bassam Shaer |
Concurrent Pseudo-Exhaustive Testing of Combinational VLSI Circuits. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
31 | José A. B. Fortes |
Future Challenges in VLSI Design. |
ISVLSI |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Peter Rieder, Sven Simon 0001, Christian V. Schimpfle |
Application Specific Efficient VLSI Architectures for Orthogonal Single- and Multiwavelet Transforms. |
J. VLSI Signal Process. |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Jinn-Wang Yeh, Wen-Jiunn Cheng, Chein-Wei Jen |
VASS - A VLSI array system synthesizer. |
J. VLSI Signal Process. |
1996 |
DBLP DOI BibTeX RDF |
|
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