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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2239 occurrences of 940 keywords
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Results
Found 7472 publication records. Showing 7472 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
210 | Vivek De |
Leakage-tolerant design techniques for high performance processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 28-28, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
186 | David T. Blaauw, Anirudh Devgan, Farid N. Najm |
Leakage power: trends, analysis and avoidance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
101 | Nikhil Jayakumar, Sunil P. Khatri |
A Predictably Low-Leakage ASIC Design Style. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(3), pp. 276-285, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
99 | Ashesh Rastogi, Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu |
On Composite Leakage Current Maximization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(4), pp. 405-420, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Leakage Maximizing Pattern Generation (LMPG), Sub-threshold leakage, Band-To-Band Tunneling (BTBT) leakage, Leakage maximization, Weighted max-satisfiability problem, Branch-and-bound heuristic, Gate leakage |
94 | Puneet Gupta 0001, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester |
Gate-length biasing for runtime-leakage control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8), pp. 1475-1485, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
94 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir |
LEAF: A System Level Leakage-Aware Floorplanner for SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 274-279, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
LEAF, leakage-aware floorplanning, temperature-aware leakage power, dynamic power profile, system on chip, SoC designs |
93 | Wei Wang, Yu Hu 0001, Yinhe Han 0001, Xiaowei Li 0001, You-Sheng Zhang |
Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 22(5), pp. 673-680, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
don’t care bits, minimum leakage vector, leakage power, leakage current |
91 | Nikhil Jayakumar, Sunil P. Khatri |
An ASIC design methodology with predictably low leakage, using leakage-immune standard cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 128-133, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
standby current, leakage current, standard cells, MTCMOS |
82 | Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma |
Defocus-Aware Leakage Estimation and Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2), pp. 230-240, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
82 | Jason Helge Anderson, Farid N. Najm |
Active leakage power optimization for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3), pp. 423-437, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
82 | Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie 0001, Wenping Wang |
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 165-170, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
82 | Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen |
Cache leakage control mechanism for hard real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 248-256, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
cache leakage control policy, hard real-time system |
81 | Geoffrey C.-F. Yeap |
Leakage current in low standby power and high performance devices: trends and challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 22-27, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
gate tunneling leakage, low standby power, off-state sub-threshold leakage, system-on-a-ship (SoC), high performance, CMOS technology, leakage current |
79 | Seongmoo Heo, Kenneth C. Barr, Mark Hampton, Krste Asanovic |
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 137-147, 2002, IEEE Computer Society, 0-7695-1605-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Dynamic Leakage Reduction |
76 | Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil D. Dutt |
Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 297-308, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
multiple sleep mode, peripheral circuits, sram memory, temperature reduction, leakage power |
76 | Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin |
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(4), pp. 52:1-52:26, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
scheduling, placement, Reconfigurable computing, leakage, partially dynamical reconfiguration |
76 | Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma |
Leakage reduction, delay compensation using partition-based tunable body-biasing techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(4), pp. 53:1-53:22, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low-power design, process variations, leakage current, Body biasing |
76 | Wei Zhang 0002, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin |
Reducing dynamic and leakage energy in VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(1), pp. 1-28, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
dynamic energy, schedule slacks, compiler, VLIW architecture, leakage energy |
76 | Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky |
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 522-527, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
leakage, technology mapping, logical effort |
76 | Andrew B. Kahng, Swamy Muddu, Puneet Sharma |
Defocus-aware leakage estimation and control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 263-268, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ACLV, yield, leakage, lithography |
76 | Amit Agarwal 0001, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy 0001 |
Leakage in nano-scale technologies: mechanisms, impact and design considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 6-11, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
process variation, leakage current, circuit design |
73 | Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown |
Analysis and Optimization of Enhanced MTCMOS Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 234-239, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
70 | Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu |
A Study on Impact of Leakage Current on Dynamic Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1069-1072, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
70 | Kamal S. Khouri, Niraj K. Jha |
Leakage power analysis and reduction during behavioral synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(6), pp. 876-885, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
70 | Hongliang Chang, Sachin S. Sapatnekar |
Prediction of leakage power under process uncertainties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(2), pp. 12, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
process variation, yield, leakage, Circuit |
70 | Baozhen Yu, Michael L. Bushnell |
A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 214-219, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
power cutoff, standby current, stacking, leakage current, dynamic power |
70 | Stefanos Kaxiras, Polychronis Xekalakis, Georgios Keramidas |
A simple mechanism to adapt leakage-control policies to temperature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 54-59, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
hybrid leakage mechanism, thermal adaptation, drowsy cache, cache decay |
69 | Jie Gu 0003, John Keane 0001, Chris H. Kim |
Modeling and analysis of leakage induced damping effect in low voltage LSIs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 382-387, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
damping effect, supply noise, gate leakage, subthreshold leakage |
67 | Lei He 0001, Weiping Liao, Mircea R. Stan |
System level leakage reduction considering the interdependence of temperature and leakage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 12-17, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
microarchitecture, leakage power, temperature |
67 | Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns |
Leakage and leakage sensitivity computation for combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 96-99, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
iddq analysis, sensitivity, power estimation, leakage power |
64 | Hushrav Mogal, Kia Bazargan |
Microarchitecture floorplanning for sub-threshold leakage reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1238-1243, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
64 | Min Ni, Seda Ogrenci Memik |
Thermal-induced leakage power optimization by redundant resource allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 297-302, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
64 | Nam Sung Kim, David T. Blaauw, Trevor N. Mudge |
Quantitative analysis and optimization techniques for on-chip cache leakage power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(10), pp. 1147-1156, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
64 | Narender Hanchate, Nagarajan Ranganathan |
A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 228-233, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
64 | Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal 0001, Chris H. Kim, Kaushik Roy 0001 |
Gate leakage reduction for scaled devices using transistor stacking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(4), pp. 716-730, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
64 | Wenjie Jiang, Vivek Tiwari, Erik de la Iglesia, Amit Sinha |
Topological Analysis for Leakage Prediction of Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 39-44, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
64 | Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar |
Reducing leakage in a high-performance deep-submicron instruction cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(1), pp. 77-89, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
64 | Wei Zhang 0002, Bramha Allu |
Reducing branch predictor leakage energy by exploiting loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 6(2), pp. 11, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
compiler, Branch prediction, leakage energy |
64 | Michele Boreale |
Quantifying Information Leakage in Process Calculi. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP (2) ![In: Automata, Languages and Programming, 33rd International Colloquium, ICALP 2006, Venice, Italy, July 10-14, 2006, Proceedings, Part II, pp. 119-131, 2006, Springer, 3-540-35907-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
information theory, process calculi, secrecy, information leakage |
64 | Yu Wang 0002, Yongpan Liu, Rong Luo, Huazhong Yang, Hui Wang 0004 |
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 238-243, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
leakage current reduction, two-phase fine-grain sleep transistor insertion, mixed integer linear programming |
64 | Wei Zhang 0002, Bramha Allu |
Loop-based leakage control for branch predictors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004, pp. 149-155, 2004, ACM, 1-58113-890-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
compiler, branch prediction, leakage energy |
64 | Songqing Zhang, Vineet Wason, Kaustav Banerjee |
A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 156-161, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
die-to-die variations, electrothermal couplings, subthreshold leakage power distribution, yield estimation, process variations, within-die variations |
64 | Rajeev R. Rao, Ashish Srivastava, David T. Blaauw, Dennis Sylvester |
Statistical estimation of leakage current considering inter- and intra-die process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 84-89, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
variability, Monte Carlo, leakage current |
64 | Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy 0001 |
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 169-174, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
doping profiles, leakage, tunneling, threshold voltage |
64 | Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi |
Let caches decay: reducing leakage energy via exploitation of cache generational behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 20(2), pp. 161-190, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
generational behavior, Cache memories, leakage power, cache decay |
63 | Tsung-Yi Wu, Jr-Luen Tzeng, Kuang-Yao Chen |
A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 672-677, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
MLV controller, probability-based algorithm, leakage current reduction, minimum leakage vector |
63 | Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi |
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 654-659, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm |
63 | Amit Agarwal 0001, Kaushik Roy 0001 |
A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 18-21, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
diode, low leakage cache, SRAM, gate leakage |
63 | Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown |
Efficient techniques for gate leakage estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 100-103, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
pattern-dependent, pattern-independent, estimation, leakage, gate leakage |
61 | Kanupriya Gulati, Sunil P. Khatri, Peng Li 0001 |
Closed-loop modeling of power and temperature profiles of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 287, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
sub-threshold leakage, dynamic power |
61 | Kaviraj Chopra, Sarma B. K. Vrudhula |
Implicit pseudo boolean enumeration algorithms for input vector control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 767-772, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
power, CMOS, SAT, binary decision diagrams, leakage, symbolic methods |
58 | Sung Woo Chung, Kevin Skadron |
On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(1), pp. 7-24, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Low-power design, Microprocessors, Cache memories, Energy-aware systems |
58 | Yongpan Liu, Robert P. Dick, Li Shang, Huazhong Yang |
Accurate temperature-dependent integrated circuit leakage power estimation is easy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1526-1531, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
58 | Lin Yuan, Gang Qu 0001 |
Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 548-551, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
58 | Lin Yuan, Gang Qu 0001 |
A combined gate replacement and input vector control approach for leakage current reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(2), pp. 173-182, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
58 | Jun-Cheol Park, Vincent John Mooney III |
Sleepy Stack Leakage Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(11), pp. 1250-1263, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
58 | Dongwoo Lee, David T. Blaauw, Dennis Sylvester |
Runtime Leakage Minimization Through Probability-Aware Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(10), pp. 1075-1088, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
58 | Micah G. O'Halloran, Rahul Sarpeshkar |
An analog storage cell with 5e-/sec leakage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
58 | Dongwoo Lee, David T. Blaauw, Dennis Sylvester |
Static leakage reduction through simultaneous Vt/Tox and state assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7), pp. 1014-1029, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
58 | Shengqi Yang, Wayne H. Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie 0001 |
Low-leakage robust SRAM cell design for sub-100nm technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 539-544, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
58 | Domenik Helms, Eike Schmidt, Wolfgang Nebel |
Leakage in CMOS Circuits - An Introduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 17-35, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
58 | Ge Yang 0004, Zhongda Wang, Sung-Mo Kang |
Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 222-227, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
58 | Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar |
An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24, 2001, pp. 147-157, 2001, IEEE Computer Society, 0-7695-1019-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
58 | Daniel Eckerbert, Per Larsson-Edefors |
Cycle-true leakage current modeling for CMOS gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 507-510, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
58 | Kamal S. Khouri, Niraj K. Jha |
Leakage Power Analysis and Reduction during Behavioral Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 561-564, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
58 | Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy 0001 |
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 239-244, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
58 | Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong |
A linear statistical analysis for full-chip leakage power with spatial correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 227-232, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
statistical leakage analysis, strong and weak correlation, linear, look-up table |
58 | Xiaoming Chen 0003, Yu Wang 0002, Yu Cao 0001, Yuchun Ma, Huazhong Yang |
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 39-44, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic vdd scaling, leakage power, negative bias temperature instability (NBTI), dual vdd |
58 | Yuan-Shin Hwang, Jia-Jhe Li |
Snug set-associative caches: Reducing leakage power of instruction and data caches with no performance penalties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(1), pp. 6, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Caches, leakage power, drowsy caches, cache decay |
58 | Yifan Zhu, Frank Mueller 0001 |
DVSleak: combining leakage reduction and voltage scaling in feedback EDF scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 31-40, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
scheduling, real-time systems, dynamic voltage scaling, leakage, feedback control |
58 | Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang |
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 92-97, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
post-placement optimization, scheduling, field-programmable gate array, leakage |
58 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir |
Floorplan driven leakage power aware IP-based SoC design space exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 118-123, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
floorplan, leakage power, temperature |
58 | Chengyi Zhang, Hongwei Zhou, Minxuan Zhang, Zuocheng Xing |
An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 588-594, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Periodically Drowsy Speculative Recover, Adaptive, Leakage Power, Drowsy cache |
58 | Sung Woo Chung, Kevin Skadron |
Using Branch Prediction Information for Near-Optimal I-Cache Leakage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 24-37, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Low Power, Branch Prediction, Leakage, Instruction Cache, Drowsy Cache |
58 | Zhiyu Liu, Volkan Kursun |
Leakage current starved domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 428-433, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
gate oxide tunneling, sleep mode, domino logic, subthreshold leakage current, dual threshold voltage |
58 | Zhiyu Liu, Volkan Kursun |
Leakage Biased Sleep Switch Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 318-323, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
gate oxide tunneling, sleep mode, Domino logic, subthreshold leakage current, dual threshold voltage |
58 | Yan Meng, Timothy Sherwood, Ryan Kastner |
Leakage power reduction of embedded memories on FPGAs through location assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 612-617, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
location assignment, leakage power, embedded memory |
58 | Nasir Mohyuddin, Rashed Zafar Bhatti, Michel Dubois 0001 |
Controlling leakage power with the replacement policy in slumberous caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005, pp. 161-170, 2005, ACM, 1-59593-019-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
tranquility level, leakage power, replacement policy, drowsy cache |
58 | Robert Bai, Nam Sung Kim, Dennis Sylvester, Trevor N. Mudge |
Total leakage optimization strategies for multi-level caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 381-384, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low power, cache memory, gate leakage |
58 | Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri |
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 43-46, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
leakage power, self-adjusting, body-biasing |
58 | Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif |
Approaches to run-time and standby mode leakage reduction in global buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 188-193, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
pulsed buses, leakage, repeaters, MTCMOS |
58 | Stefanos Kaxiras, Polychronis Xekalakis |
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 108-113, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
4T SRAM, architecture, sensor, leakage, temperature |
58 | Vishal Khandelwal, Ankur Srivastava 0001 |
Active mode leakage reduction using fine-grained forward body biasing strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 150-155, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
forward body biasing, leakage power optimization |
58 | Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester |
Parametric yield estimation considering leakage variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 442-447, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
variability, leakage, parametric yield |
58 | Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar |
Tradeoffs between date oxide leakage and delay for dual Tox circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 761-766, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
dual Tox circuits, leakage power |
58 | Ashish Srivastava, Robert Bai, David T. Blaauw, Dennis Sylvester |
Modeling and analysis of leakage power considering within-die process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 64-67, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
variability, Monte Carlo, leakage current |
57 | Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty |
Managing standby and active mode leakage power in deep sub-micron design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 274-279, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
SRAM leakage control, TGSRAM, battery lifetime, drowsy mode, thick gate shadow latch, transistor leakage, MTCMOS |
57 | Cassondra Neau, Kaushik Roy 0001 |
Optimal body bias selection for leakage improvement and process compensation over different technology generations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 116-121, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
band-to-band tunneling, leakage components, process compensation, substrate bias, process variation, leakage current, CMOS scaling, body bias |
57 | Benton H. Calhoun, Frank Honoré, Anantha P. Chandrakasan |
Design methodology for fine-grained leakage control in MTCMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 104-109, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
fine-grain sleep regions, sneak leakage, low power, design methodology, leakage, circuit design, sleep mode, MTCMOS |
55 | Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001 |
Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(6), pp. 660-671, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
55 | Chris H. Kim, Steven Hsu, Ram Krishnamurthy 0001, Shekhar Borkar, Kaushik Roy 0001 |
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 100-105, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
55 | Maziar Goudarzi, Tohru Ishihara, Hamid Noori |
Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings, pp. 224-239, 2008, Springer, 978-3-540-77559-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
process variation, cache memory, Leakage power, power reduction |
54 | Debasis Samanta, Ajit Pal |
Synthesis of Dual-VT Dynamic CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 303-308, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
nora logic, unate decomposition, low power, Logic synthesis, high performance, leakage power, domino logic, dynamic circuits, dual-VT |
52 | Duk-Hyung Lee, Dong-Kone Kwak, Kyeong-Sik Min |
Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 632-637, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
52 | Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong |
A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 481-486, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
statistical analysis, spatial correlation, dynamic power |
52 | Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry |
Input Vector Reordering for Leakage Power Reduction in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9), pp. 1555-1564, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
52 | Jun Seomun, Jae-Hyun Kim, Youngsoo Shin |
Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11), pp. 1956-1968, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
52 | Puneet Gupta 0001, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester |
Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9), pp. 1614-1624, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
52 | Xiaoji Ye, Yaping Zhan, Peng Li 0001 |
Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 853-858, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
52 | Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester |
Analytical yield prediction considering leakage/performance correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9), pp. 1685-1695, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
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