Search results for "SRAM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
104	Jian Liu, Rafic Z. Makki	Power supply current detectability of SRAM defects.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	short-circuit currents, fault currents, power supply circuits, power supply current detectability, SRAM defects, SRAM cell, power supply current, I/sub DDQ/, quiescent power supply current, i/sub DDT/, transient power supply current, shorts, disturb-type pattern sensitivity, total current leakage, SRAM size, current detectability, large circuit effects, simulation, fault diagnosis, leakage currents, transients, SRAM chips, open defects, electric current measurement, physical defect
100	F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh 0004	Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability.	ISQED	2003	DBLP DOI BibTeX RDF
91	Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan	A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	nano-CMOS, power, leakage, SRAM, static noise margin
91	Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun	Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers.	DAC	2010	DBLP DOI BibTeX RDF	optimization, design space exploration, SRAM, virtual prototype, iterative design
90	Sreeharsha Tavva, Dhireesha Kudithipudi	Variation tolerant 9T SRAM cell design.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	bitline leakage, static random access memory (SRAM), process variations, static noise margin, embedded sram
84	Keejong Kim, Chris H. Kim, Kaushik Roy 0001	TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique.	ISQED	2005	DBLP DOI BibTeX RDF
83	Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan	SRAM-based NBTI/PBTI sensor system design.	DAC	2010	DBLP DOI BibTeX RDF	PBTI, sensor system design, sensor, redundancy, process variation, aging, yield, SRAM, NBTI
83	Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang	Design and analysis of ultra-thin-body SOI based subthreshold SRAM.	ISLPED	2009	DBLP DOI BibTeX RDF	poisson's equation, subthreshold SRAM, ultra-thin-body, soi, static noise margin
81	Qi Zhao 0006, Jun (Jim) Xu, Zhen Liu	Design of a novel statistics counter architecture with optimal space and time efficiency.	SIGMETRICS/Performance	2006	DBLP DOI BibTeX RDF	statistics counter, data streaming, router
81	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for SRAM cluster interconnect testing at board level.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
76	Sanjeev K. Jain, Pankaj Agarwal	A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology.	VLSI Design	2006	DBLP DOI BibTeX RDF
75	Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen 0024, Yu Cao 0001, Lawrence T. Clark	In-situ characterization and extraction of SRAM variability.	DAC	2010	DBLP DOI BibTeX RDF	SRAM test, data retention voltage, threshold voltage variation, write margin, extraction
75	Prabhat Jain, G. Edward Suh, Srinivas Devadas	Embedded intelligent SRAM.	DAC	2003	DBLP DOI BibTeX RDF	computation partitioning, embedded, SRAM, intelligent
73	Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy 0001	A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM.	ISLPED	2007	DBLP DOI BibTeX RDF	low power SRAM, low voltage SRAM, schmitt trigger, subthreshold SRAM, process variations
71	Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham	Cache Design for Low Power and High Yield.	ISQED	2008	DBLP DOI BibTeX RDF	reduce voltage swing, sram yield, SRAM 6T cell, cache design, parametric failure
67	Sherif A. Tawfik, Volkan Kursun	Low power and robust 7T dual-Vt SRAM circuit.	ISCAS	2008	DBLP DOI BibTeX RDF
67	Jun-Cheol Park, Vincent John Mooney III	Pareto Points in SRAM Design Using the Sleepy Stack Approach.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
67	R. Castagnetti, R. Venkatraman, Brandon Bartz, Carl Monzel, T. Briscoe, Andres Teene, S. Ramesh 0004	A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC.	ISQED	2005	DBLP DOI BibTeX RDF
66	Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King 0001, Borivoje Nikolic	FinFET-based SRAM design.	ISLPED	2005	DBLP DOI BibTeX RDF	double gate transistors, low power, memory, SRAM
65	Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy 0001	Process variation tolerant SRAM array for ultra low voltage applications.	DAC	2008	DBLP DOI BibTeX RDF	Schmitt trigger SRAM, low voltage/sub-threshold SRAM, process tolerance
65	Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka	Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	SRAM test, SRAM-based reconfigurable cell, memory tester, marching test
65	Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li 0001, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin	A built-in self-test and self-diagnosis scheme for embedded SRAM.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	self-diagnosis scheme, fault diagnosis, fault diagnosis, built-in self test, built-in self-test, system-on-chip, memory test, SRAM chips, embedded SRAM
64	Mohamed H. Abu-Rahma, Kinshuk Chowdhury, Joseph Wang, Zhiqin Chen, Sei Seung Yoon, Mohab Anis	A methodology for statistical estimation of read access yield in SRAMs.	DAC	2008	DBLP DOI BibTeX RDF	access failure, random variations, memory, variability, statistical modeling, yield, SRAM, worst-case
62	Bradly K. Fawcett, J. Watson	Reconfigurable Processing With Field Programmable Gate Arrays.	ASAP	1996	DBLP DOI BibTeX RDF	reconfigurable processing, internal architecture, computationally-intensive tasks, programmable solution, XC6200 FPGA architecture, SRAM control store, on-chip memory capability, field programmable gate arrays, interconnections, reconfigurable architectures, processors, coprocessors, coprocessors, SRAM chips, SRAM-based field programmable gate arrays
59	Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li 0001, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi	The impact of BEOL lithography effects on the SRAM cell performance and yield.	ISQED	2009	DBLP DOI BibTeX RDF
59	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
59	Zhiyu Liu, Volkan Kursun	Characterization of a Novel Nine-Transistor SRAM Cell.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
59	Zhiyu Liu, Sherif A. Tawfik, Volkan Kursun	Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations.	ISQED	2008	DBLP DOI BibTeX RDF	static noise margin distribution, robust operation, active power, standby power distribution, double gate MOSFET, process variations, Cache memory
59	Jordan Lai	SRAM Design Techniques for Sub-nano CMOS Technology.	MTDT	2006	DBLP DOI BibTeX RDF
59	Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy 0001	A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
59	Shengqi Yang, Wayne H. Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie 0001	Low-leakage robust SRAM cell design for sub-100nm technologies.	ASP-DAC	2005	DBLP DOI BibTeX RDF
58	Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil D. Dutt	Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	multiple sleep mode, peripheral circuits, sram memory, temperature reduction, leakage power
58	Adam C. Cabe, Zhenyu Qi, Mircea R. Stan	Stacking SRAM banks for ultra low power standby mode operation.	DAC	2010	DBLP DOI BibTeX RDF	stacked SRAM, low-power memory
58	Jian Wang, Soner Yaldiz, Xin Li 0001, Lawrence T. Pileggi	SRAM parametric failure analysis.	DAC	2009	DBLP DOI BibTeX RDF	failure probability estimation, response surface model, SRAM, parametric failure
58	Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran	Fundamental Data Retention Limits in SRAM Standby Experimental Results.	ISQED	2008	DBLP DOI BibTeX RDF	standby, data retention, low power, SRAM, error control code
58	Huifang Qin, Animesh Kumar, Kannan Ramchandran, Jan M. Rabaey, Prakash Ishwar	Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation.	ISQED	2008	DBLP DOI BibTeX RDF	DRV, low power, ECC, leakage, SRAM, variation, low voltage, error tolerant
58	Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy 0001	Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry.	VTS	2008	DBLP DOI BibTeX RDF	Design, yield, failure, SRAM, variation
58	Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro	Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	reliability, fault tolerant systems, SEU, SRAM-based FPGA
58	Keejong Kim, Hamid Mahmoodi, Kaushik Roy 0001	A low-power SRAM using bit-line charge-recycling technique.	ISLPED	2007	DBLP DOI BibTeX RDF	write margin, write power, low power, process variation, SRAM, charge-recycling
58	Luca Sterpone, Massimo Violante	A new decompression system for the configuration process of SRAM-based FPGAS.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	configuration mechanisms, compression algorithm, SRAM-based FPGA
58	Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane Irwin	A comparative study of power efficient SRAM designs.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF	low power, decoder, SRAM
58	Amr M. Fahim, Muhammad M. Khellah, Mohamed I. Elmasry	A Low-Power High-Performance Embedded SRAM Macrocell.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	low power, memory, DSP, high performance, SRAM
57	Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering.	ISLPED	2006	DBLP DOI BibTeX RDF	data-bit reordering, low power SRAM, two-port SRAM, real-time image processing, majority logic
57	Hiroyuki Goto, Shigeo Nakamura, Kazuhiko Iwasaki	Experimental fault analysis of 1 Mb SRAM chips.	VTS	1997	DBLP DOI BibTeX RDF	stuck-at cell faults, stuck-at bit-line faults, stuck-at word-line fault, neighborhood-pattern-sensitive faults, load capacity, margin fault detection, 1 Mbit, 70 C, 30 pF, memory testing, fault analysis, SRAM chips, SRAM chips
57	Zhao Zhang 0010, Zhichun Zhu, Xiaodong Zhang 0001	Design and Optimization of Large Size and Low Overhead Off-Chip Caches.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
57	Sriram Ramabhadran, George Varghese	Efficient implementation of a statistics counter architecture.	SIGMETRICS	2003	DBLP DOI BibTeX RDF	statistics counter, router
54	Satish Anand Verkila, Siva Kumar Bondada, Bharadwaj S. Amrutur	A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read.	VLSI Design	2008	DBLP DOI BibTeX RDF
54	Jason Meyer, Fatih Kocan	Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
51	Kuande Wang, Li Chen, Jinsheng Yang	AN ultra low power fault tolerant SRAM design in 90nm CMOS.	CCECE	2009	DBLP DOI BibTeX RDF
51	Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi	Low power 8T SRAM using 32nm independent gate FinFET technology.	SoCC	2008	DBLP DOI BibTeX RDF
51	Farshad Moradi, Dag T. Wisland, Snorre Aunet, Hamid Mahmoodi, Tuan Vu Cao	65NM sub-threshold 11T-SRAM for ultra low voltage applications.	SoCC	2008	DBLP DOI BibTeX RDF
51	Yijun Liu, Pinghua Chen, Wenyan Wang, Zhenkun Li	The Design and Implementation of a Power Efficient Embedded SRAM.	PATMOS	2007	DBLP DOI BibTeX RDF
51	Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing.	ISVLSI	2007	DBLP DOI BibTeX RDF
51	Gregory K. Chen, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim	Yield-driven near-threshold SRAM design.	ICCAD	2007	DBLP DOI BibTeX RDF
51	Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto, Tetsuro Matsuno	A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
51	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment.	DATE	2006	DBLP DOI BibTeX RDF
51	Yu-Jen Chen, Chen-Han Tsai, Liang-Gee Chen	Architecture design of area-efficient SRAM-based multi-symbol arithmetic encoder in H.264/AVC.	ISCAS	2006	DBLP DOI BibTeX RDF
51	G. Razavipour, A. Motamedi, Ali Afzali-Kusha	WL-VC SRAM: a low leakage memory circuit for deep sub-micron design.	ISCAS	2006	DBLP DOI BibTeX RDF
51	Behnam Amelifard, Massoud Pedram, Farzan Fallah	Low-leakage SRAM Design with Dual V_t Transistors.	ISQED	2006	DBLP DOI BibTeX RDF
51	H. Kondou, Sumio Fukai, Yohei Ishikawa	Multiple-valued SRAM with FG-MOSFETs.	APCCAS	2006	DBLP DOI BibTeX RDF
51	Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy 0001	Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
51	Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu	SRAM delay fault modeling and test algorithm development.	ASP-DAC	2004	DBLP DOI BibTeX RDF
51	Yong Liu 0023, Zhiqiang Gao, Xiangqing He	A Flexible Embedded SRAM Compiler.	DELTA	2002	DBLP DOI BibTeX RDF
50	Yong Zhang 0049, Peng Li 0001, Garng M. Huang	Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis.	DAC	2010	DBLP DOI BibTeX RDF	separatrix, SRAM, dynamic stability
50	Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	Quality of a Bit (QoB): A New Concept in Dependable SRAM.	ISQED	2008	DBLP DOI BibTeX RDF	Quality of a bit, SRAM
50	Mohammad Sharifkhani, Manoj Sachdev	A low power SRAM architecture based on segmented virtual grounding.	ISLPED	2006	DBLP DOI BibTeX RDF	static-random access memory, write power reduction, low-power, SRAM, leakage reduction
50	Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar	Impact of NBTI on SRAM Read Stability and Design for Reliability.	ISQED	2006	DBLP DOI BibTeX RDF	Static Noise Margin (SNM), Reaction-Diffusion (R-D) Model, Cache, SRAM, Negative Bias Temperature Instability (NBTI)
50	Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy 0001	A forward body-biased low-leakage SRAM cache: device and architecture considerations.	ISLPED	2003	DBLP DOI BibTeX RDF	forward body-biasing, super high VT, SRAM, leakage power
49	Ding-Ming Kwai, Hung-Wen Chang, Hung-Jen Liao, Ching-Hua Chiao, Yung-Fa Chou	etection of SRAM cell stability by lowering array supply voltage.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cell stability detection, array supply voltage reduction, design-for-test technique, static random access memory, memory array, test mode, detection capability, logic testing, integrated circuit testing, design for testability, CMOS technology, SRAM chips, CMOS memory circuits, DFT technique, circuit stability, 0.18 micron
49	Hari Balachandran, D. M. H. Walker	Improvement of SRAM-based failure analysis using calibrated Iddq testing.	VTS	1996	DBLP DOI BibTeX RDF	defect-bitmap dictionary, voltage testing, microprocessor cache memory, integrated circuit testing, calibration, calibration, SRAM, cache storage, failure analysis, failure analysis, IDDQ testing, current testing, defect classification, SRAM chips, integrated circuit yield, integrated circuit yield
49	Doe Hyun Yoon, Mattan Erez	Memory mapped ECC: low-cost error protection for last level caches.	ISCA	2009	DBLP DOI BibTeX RDF	reliability, error correction, soft error, last-level caches
49	Zhiyu Liu, Volkan Kursun	High Read Stability and Low Leakage Cache Memory Cell.	ISCAS	2007	DBLP DOI BibTeX RDF
49	Qikai Chen, Arjun Guha, Kaushik Roy 0001	An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function.	VLSI Design	2007	DBLP DOI BibTeX RDF
49	Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo	Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
49	Joohee Kim, Marios C. Papaefthymiou	Constant-load energy recovery memory for efficient high-speed operation.	ISLPED	2004	DBLP DOI BibTeX RDF	adiabatic circuitry, charge recovery, cache memories, on-chip memories, low-power computing, low-energy design
49	Doug Malone	Design Validation of .18 um 1 Ghz Cache and Register Arrays.	MTDT	1999	DBLP DOI BibTeX RDF
48	Kiyoo Itoh 0001	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.	ISLPED	2009	DBLP DOI BibTeX RDF	0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
48	Yiming Li 0005, Chih-Hong Hwang, Shao-Ming Yu	Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors.	International Conference on Computational Science (4)	2007	DBLP DOI BibTeX RDF	computational statistics, SRAM, modeling and simulation, FinFET
43	Norbert Sram	Fuzzy alapú és statisztikai hipotézisvizsgálaton alapuló referencia modellek hatásvizsgálata és fejlesztése		2017	RDF
43	Jan G. Svec, Marek Fric, Frantisek Sram, Harm K. Schutte	Mucosal waves on the vocal folds: conceptualization based on videokymography.	MAVEBA	2007	DBLP BibTeX RDF
43	Jan G. Svec, Frantisek Sram, Marek Fric, Q. Qiu, Harm K. Schutte	What can be seen in videokymographic images?	MAVEBA	2005	DBLP BibTeX RDF
43	Jan G. Svec, Frantisek Sram	Kymographic imaging of the vocal fold oscillations.	INTERSPEECH	2002	DBLP DOI BibTeX RDF
43	Paavo Alku, Jan G. Svec, Erkki Vilkman, Frantisek Sram	Analysis of voice production in breathy, normal and pressed phonation by comparing inverse filtering and videokymography.	INTERSPEECH	2000	DBLP DOI BibTeX RDF
43	David Hentrich, Erdal Oruklu, Jafar Saniie	Performance evaluation of SRAM cells in 22nm predictive CMOS technology.	EIT	2009	DBLP DOI BibTeX RDF
43	Animesh Kumar, Jan M. Rabaey, Kannan Ramchandran	SRAM supply voltage scaling: A reliability perspective.	ISQED	2009	DBLP DOI BibTeX RDF
43	Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy 0001	Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
43	Wei Dong 0002, Peng Li 0001, Garng M. Huang	SRAM dynamic stability: theory, variability and analysis.	ICCAD	2008	DBLP DOI BibTeX RDF
43	Aditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang	Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield.	ICCD	2008	DBLP DOI BibTeX RDF
43	Yi Xu, Zhiqiang Gao, Xiangqing He	A Flexible Embedded SRAM IP Compiler.	ISCAS	2007	DBLP DOI BibTeX RDF
43	Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran	Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM.	ISCAS	2007	DBLP DOI BibTeX RDF
43	Afshin Nourivand, Chunyan Wang 0004, M. Omair Ahmad	An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM.	ISCAS	2007	DBLP DOI BibTeX RDF
43	Chung-Kuan Tsai, Malgorzata Marek-Sadowska	Analysis of Process Variation's Effect on SRAM's Read Stability.	ISQED	2006	DBLP DOI BibTeX RDF
43	Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
43	Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy 0001	A Feasibility Study of Subthreshold SRAM Across Technology Generations.	ICCD	2005	DBLP DOI BibTeX RDF
43	Jinn-Shyan Wang, Po-Hui Yang, Wayne Tseng	Low-power embedded SRAM macros with current-mode read/write operations.	ISLPED	1998	DBLP DOI BibTeX RDF
43	Koji Nii, Hiroshi Makino, Yoshiki Tsujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano	A low power SRAM using auto-backgate-controlled MT-CMOS.	ISLPED	1998	DBLP DOI BibTeX RDF
42	Anuj Pushkarna, Hamid Mahmoodi	Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	reliability, aging, SRAM, power gating
42	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	A statistical simulation method for reliability analysis of SRAM core-cells.	DAC	2010	DBLP DOI BibTeX RDF	SRAM core-cell, Monte-Carlo, reliability analysis
42	Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy 0001	A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors.	DAC	2009	DBLP DOI BibTeX RDF	low power SRAM, supply voltage over-scaling, graceful degradation
42	Rouwaida Kanj, Zhuo Li 0001, Rajiv V. Joshi, Frank Liu 0001, Sani R. Nassif	A Root-Finding Method for Assessing SRAM Stability.	ISQED	2008	DBLP DOI BibTeX RDF	stability, memory, yield, sram, roots