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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 989 occurrences of 488 keywords
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Results
Found 3882 publication records. Showing 3880 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
104 | Jian Liu, Rafic Z. Makki |
Power supply current detectability of SRAM defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 367-, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
short-circuit currents, fault currents, power supply circuits, power supply current detectability, SRAM defects, SRAM cell, power supply current, I/sub DDQ/, quiescent power supply current, i/sub DDT/, transient power supply current, shorts, disturb-type pattern sensitivity, total current leakage, SRAM size, current detectability, large circuit effects, simulation, fault diagnosis, leakage currents, transients, SRAM chips, open defects, electric current measurement, physical defect |
100 | F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh 0004 |
Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 119-124, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
91 | Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan |
A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 323-328, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
nano-CMOS, power, leakage, SRAM, static noise margin |
91 | Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun |
Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 138-143, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
optimization, design space exploration, SRAM, virtual prototype, iterative design |
90 | Sreeharsha Tavva, Dhireesha Kudithipudi |
Variation tolerant 9T SRAM cell design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 55-60, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
bitline leakage, static random access memory (SRAM), process variations, static noise margin, embedded sram |
84 | Keejong Kim, Chris H. Kim, Kaushik Roy 0001 |
TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 59-64, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
83 | Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan |
SRAM-based NBTI/PBTI sensor system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 849-852, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
PBTI, sensor system design, sensor, redundancy, process variation, aging, yield, SRAM, NBTI |
83 | Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang |
Design and analysis of ultra-thin-body SOI based subthreshold SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 9-14, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
poisson's equation, subthreshold SRAM, ultra-thin-body, soi, static noise margin |
81 | Qi Zhao 0006, Jun (Jim) Xu, Zhen Liu |
Design of a novel statistics counter architecture with optimal space and time efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS/Performance ![In: Proceedings of the Joint International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS/Performance 2006, Saint Malo, France, June 26-30, 2006, pp. 323-334, 2006, ACM, 1-59593-319-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
statistics counter, data streaming, router |
81 | Chen-Huan Chiang, Sandeep K. Gupta 0001 |
BIST TPG for SRAM cluster interconnect testing at board level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 58-65, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing |
76 | Sanjeev K. Jain, Pankaj Agarwal |
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 495-498, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
75 | Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen 0024, Yu Cao 0001, Lawrence T. Clark |
In-situ characterization and extraction of SRAM variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 711-716, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
SRAM test, data retention voltage, threshold voltage variation, write margin, extraction |
75 | Prabhat Jain, G. Edward Suh, Srinivas Devadas |
Embedded intelligent SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 869-874, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
computation partitioning, embedded, SRAM, intelligent |
73 | Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy 0001 |
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 171-176, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
low power SRAM, low voltage SRAM, schmitt trigger, subthreshold SRAM, process variations |
71 | Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham |
Cache Design for Low Power and High Yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 103-107, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
reduce voltage swing, sram yield, SRAM 6T cell, cache design, parametric failure |
67 | Sherif A. Tawfik, Volkan Kursun |
Low power and robust 7T dual-Vt SRAM circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1452-1455, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
67 | Jun-Cheol Park, Vincent John Mooney III |
Pareto Points in SRAM Design Using the Sleepy Stack Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, pp. 163-177, 2005, Springer, 978-0-387-73660-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
67 | R. Castagnetti, R. Venkatraman, Brandon Bartz, Carl Monzel, T. Briscoe, Andres Teene, S. Ramesh 0004 |
A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 193-196, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
66 | Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King 0001, Borivoje Nikolic |
FinFET-based SRAM design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 2-7, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
double gate transistors, low power, memory, SRAM |
65 | Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy 0001 |
Process variation tolerant SRAM array for ultra low voltage applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 108-113, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Schmitt trigger SRAM, low voltage/sub-threshold SRAM, process tolerance |
65 | Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka |
Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 28-31, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
SRAM test, SRAM-based reconfigurable cell, memory tester, marching test |
65 | Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li 0001, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin |
A built-in self-test and self-diagnosis scheme for embedded SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 45-50, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
self-diagnosis scheme, fault diagnosis, fault diagnosis, built-in self test, built-in self-test, system-on-chip, memory test, SRAM chips, embedded SRAM |
64 | Mohamed H. Abu-Rahma, Kinshuk Chowdhury, Joseph Wang, Zhiqin Chen, Sei Seung Yoon, Mohab Anis |
A methodology for statistical estimation of read access yield in SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 205-210, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
access failure, random variations, memory, variability, statistical modeling, yield, SRAM, worst-case |
62 | Bradly K. Fawcett, J. Watson |
Reconfigurable Processing With Field Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 293-302, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
reconfigurable processing, internal architecture, computationally-intensive tasks, programmable solution, XC6200 FPGA architecture, SRAM control store, on-chip memory capability, field programmable gate arrays, interconnections, reconfigurable architectures, processors, coprocessors, coprocessors, SRAM chips, SRAM-based field programmable gate arrays |
59 | Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li 0001, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi |
The impact of BEOL lithography effects on the SRAM cell performance and yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 607-612, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
59 | Behnam Amelifard, Farzan Fallah, Massoud Pedram |
Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(7), pp. 851-860, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
59 | Zhiyu Liu, Volkan Kursun |
Characterization of a Novel Nine-Transistor SRAM Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(4), pp. 488-492, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
59 | Zhiyu Liu, Sherif A. Tawfik, Volkan Kursun |
Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 305-310, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
static noise margin distribution, robust operation, active power, standby power distribution, double gate MOSFET, process variations, Cache memory |
59 | Jordan Lai |
SRAM Design Techniques for Sub-nano CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
59 | Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy 0001 |
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(3), pp. 349-357, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
59 | Shengqi Yang, Wayne H. Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie 0001 |
Low-leakage robust SRAM cell design for sub-100nm technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 539-544, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
58 | Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil D. Dutt |
Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 297-308, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
multiple sleep mode, peripheral circuits, sram memory, temperature reduction, leakage power |
58 | Adam C. Cabe, Zhenyu Qi, Mircea R. Stan |
Stacking SRAM banks for ultra low power standby mode operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 699-704, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
stacked SRAM, low-power memory |
58 | Jian Wang, Soner Yaldiz, Xin Li 0001, Lawrence T. Pileggi |
SRAM parametric failure analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 496-501, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
failure probability estimation, response surface model, SRAM, parametric failure |
58 | Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran |
Fundamental Data Retention Limits in SRAM Standby Experimental Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 92-97, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
standby, data retention, low power, SRAM, error control code |
58 | Huifang Qin, Animesh Kumar, Kannan Ramchandran, Jan M. Rabaey, Prakash Ishwar |
Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 30-34, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
DRV, low power, ECC, leakage, SRAM, variation, low voltage, error tolerant |
58 | Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy 0001 |
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 101-106, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Design, yield, failure, SRAM, variation |
58 | Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro |
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(1), pp. 47-54, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
reliability, fault tolerant systems, SEU, SRAM-based FPGA |
58 | Keejong Kim, Hamid Mahmoodi, Kaushik Roy 0001 |
A low-power SRAM using bit-line charge-recycling technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 177-182, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
write margin, write power, low power, process variation, SRAM, charge-recycling |
58 | Luca Sterpone, Massimo Violante |
A new decompression system for the configuration process of SRAM-based FPGAS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 241-246, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
configuration mechanisms, compression algorithm, SRAM-based FPGA |
58 | Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane Irwin |
A comparative study of power efficient SRAM designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000, pp. 117-122, 2000, ACM, 1-58113-251-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low power, decoder, SRAM |
58 | Amr M. Fahim, Muhammad M. Khellah, Mohamed I. Elmasry |
A Low-Power High-Performance Embedded SRAM Macrocell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 13-17, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
low power, memory, DSP, high performance, SRAM |
57 | Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto |
A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 61-66, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
data-bit reordering, low power SRAM, two-port SRAM, real-time image processing, majority logic |
57 | Hiroyuki Goto, Shigeo Nakamura, Kazuhiko Iwasaki |
Experimental fault analysis of 1 Mb SRAM chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 31-36, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
stuck-at cell faults, stuck-at bit-line faults, stuck-at word-line fault, neighborhood-pattern-sensitive faults, load capacity, margin fault detection, 1 Mbit, 70 C, 30 pF, memory testing, fault analysis, SRAM chips, SRAM chips |
57 | Zhao Zhang 0010, Zhichun Zhu, Xiaodong Zhang 0001 |
Design and Optimization of Large Size and Low Overhead Off-Chip Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(7), pp. 843-855, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
57 | Sriram Ramabhadran, George Varghese |
Efficient implementation of a statistics counter architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the International Conference on Measurements and Modeling of Computer Systems, SIGMETRICS 2003, June 9-14, 2003, San Diego, CA, USA, pp. 261-271, 2003, ACM, 1-58113-664-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
statistics counter, router |
54 | Satish Anand Verkila, Siva Kumar Bondada, Bharadwaj S. Amrutur |
A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 560-565, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
54 | Jason Meyer, Fatih Kocan |
Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(2), pp. 182-195, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Kuande Wang, Li Chen, Jinsheng Yang |
AN ultra low power fault tolerant SRAM design in 90nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, CCECE 2009, 3-6 May 2009, Delta St. John's Hotel and Conference Centre, St. John's, Newfoundland, Canada, pp. 1076-1079, 2009, IEEE, 978-1-4244-3508-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
51 | Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi |
Low power 8T SRAM using 32nm independent gate FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 247-250, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
51 | Farshad Moradi, Dag T. Wisland, Snorre Aunet, Hamid Mahmoodi, Tuan Vu Cao |
65NM sub-threshold 11T-SRAM for ultra low voltage applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 113-118, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
51 | Yijun Liu, Pinghua Chen, Wenyan Wang, Zhenkun Li |
The Design and Implementation of a Power Efficient Embedded SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 86-96, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto |
A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 107-112, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Gregory K. Chen, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim |
Yield-driven near-threshold SRAM design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 660-666, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto, Tetsuro Matsuno |
A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 192-197, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
51 | Behnam Amelifard, Farzan Fallah, Massoud Pedram |
Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 995-1000, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
51 | Yu-Jen Chen, Chen-Han Tsai, Liang-Gee Chen |
Architecture design of area-efficient SRAM-based multi-symbol arithmetic encoder in H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
51 | G. Razavipour, A. Motamedi, Ali Afzali-Kusha |
WL-VC SRAM: a low leakage memory circuit for deep sub-micron design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
51 | Behnam Amelifard, Massoud Pedram, Farzan Fallah |
Low-leakage SRAM Design with Dual V_t Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 729-734, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
51 | H. Kondou, Sumio Fukai, Yohei Ishikawa |
Multiple-valued SRAM with FG-MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1305-1308, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
51 | Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy 0001 |
Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(11), pp. 1286-1295, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
51 | Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu |
SRAM delay fault modeling and test algorithm development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 104-109, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
51 | Yong Liu 0023, Zhiqiang Gao, Xiangqing He |
A Flexible Embedded SRAM Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 474-476, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
50 | Yong Zhang 0049, Peng Li 0001, Garng M. Huang |
Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 567-572, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
separatrix, SRAM, dynamic stability |
50 | Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto |
Quality of a Bit (QoB): A New Concept in Dependable SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 98-102, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Quality of a bit, SRAM |
50 | Mohammad Sharifkhani, Manoj Sachdev |
A low power SRAM architecture based on segmented virtual grounding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 256-261, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
static-random access memory, write power reduction, low-power, SRAM, leakage reduction |
50 | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
Impact of NBTI on SRAM Read Stability and Design for Reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 210-218, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Static Noise Margin (SNM), Reaction-Diffusion (R-D) Model, Cache, SRAM, Negative Bias Temperature Instability (NBTI) |
50 | Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy 0001 |
A forward body-biased low-leakage SRAM cache: device and architecture considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 6-9, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
forward body-biasing, super high VT, SRAM, leakage power |
49 | Ding-Ming Kwai, Hung-Wen Chang, Hung-Jen Liao, Ching-Hua Chiao, Yung-Fa Chou |
etection of SRAM cell stability by lowering array supply voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 268-273, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SRAM cell stability detection, array supply voltage reduction, design-for-test technique, static random access memory, memory array, test mode, detection capability, logic testing, integrated circuit testing, design for testability, CMOS technology, SRAM chips, CMOS memory circuits, DFT technique, circuit stability, 0.18 micron |
49 | Hari Balachandran, D. M. H. Walker |
Improvement of SRAM-based failure analysis using calibrated Iddq testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 130-137, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
defect-bitmap dictionary, voltage testing, microprocessor cache memory, integrated circuit testing, calibration, calibration, SRAM, cache storage, failure analysis, failure analysis, IDDQ testing, current testing, defect classification, SRAM chips, integrated circuit yield, integrated circuit yield |
49 | Doe Hyun Yoon, Mattan Erez |
Memory mapped ECC: low-cost error protection for last level caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 116-127, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
reliability, error correction, soft error, last-level caches |
49 | Zhiyu Liu, Volkan Kursun |
High Read Stability and Low Leakage Cache Memory Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2774-2777, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Qikai Chen, Arjun Guha, Kaushik Roy 0001 |
An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 615-620, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo |
Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(11), pp. 1238-1249, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Joohee Kim, Marios C. Papaefthymiou |
Constant-load energy recovery memory for efficient high-speed operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 240-243, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
adiabatic circuitry, charge recovery, cache memories, on-chip memories, low-power computing, low-energy design |
49 | Doug Malone |
Design Validation of .18 um 1 Ghz Cache and Register Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 7th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT '99), August 9-10, 1999, San Jose, CA, USA, pp. 54-, 1999, IEEE Computer Society, 0-7695-0259-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
48 | Kiyoo Itoh 0001 |
Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 273-274, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet |
48 | Yiming Li 0005, Chih-Hong Hwang, Shao-Ming Yu |
Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (4) ![In: Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27 - 30, 2007, Proceedings, Part IV, pp. 227-234, 2007, Springer, 978-3-540-72589-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
computational statistics, SRAM, modeling and simulation, FinFET |
43 | Norbert Sram |
Fuzzy alapú és statisztikai hipotézisvizsgálaton alapuló referencia modellek hatásvizsgálata és fejlesztése ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2017 |
RDF |
|
43 | Jan G. Svec, Marek Fric, Frantisek Sram, Harm K. Schutte |
Mucosal waves on the vocal folds: conceptualization based on videokymography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MAVEBA ![In: Fifth International Workshop on Models and Analysis of Vocal Emissions for Biomedical Applications, MAVEBA 2007, Florence, Italy, December 13-15, 2007, pp. 171-172, 2007, Firenze University Press / ISCA, 978-88-8453-674-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
43 | Jan G. Svec, Frantisek Sram, Marek Fric, Q. Qiu, Harm K. Schutte |
What can be seen in videokymographic images? ![Search on Bibsonomy](Pics/bibsonomy.png) |
MAVEBA ![In: Fourth International Workshop on Models and Analysis of Vocal Emissions for Biomedical Applications, MAVEBA 2005, Florence, Italy, October 29-31, 2005, pp. 119, 2005, Firenze University Press / ISCA, 88-8453-319-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
43 | Jan G. Svec, Frantisek Sram |
Kymographic imaging of the vocal fold oscillations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INTERSPEECH ![In: 7th International Conference on Spoken Language Processing, ICSLP2002 - INTERSPEECH 2002, Denver, Colorado, USA, September 16-20, 2002, pp. 957-960, 2002, ISCA. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
43 | Paavo Alku, Jan G. Svec, Erkki Vilkman, Frantisek Sram |
Analysis of voice production in breathy, normal and pressed phonation by comparing inverse filtering and videokymography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INTERSPEECH ![In: Sixth International Conference on Spoken Language Processing, ICSLP 2000 / INTERSPEECH 2000, Beijing, China, October 16-20, 2000, pp. 885-888, 2000, ISCA. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | David Hentrich, Erdal Oruklu, Jafar Saniie |
Performance evaluation of SRAM cells in 22nm predictive CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2009 IEEE International Conference on Electro/Information Technology, EIT 2009, Windsor, Ontario, Canada, June 7-9, 2009, pp. 470-475, 2009, IEEE, 978-1-4244-3355-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
43 | Animesh Kumar, Jan M. Rabaey, Kannan Ramchandran |
SRAM supply voltage scaling: A reliability perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 782-787, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
43 | Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy 0001 |
Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1), pp. 174-183, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Wei Dong 0002, Peng Li 0001, Garng M. Huang |
SRAM dynamic stability: theory, variability and analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 378-385, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Aditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang |
Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 457-462, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Yi Xu, Zhiqiang Gao, Xiangqing He |
A Flexible Embedded SRAM IP Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3756-3759, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran |
Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1867-1870, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Afshin Nourivand, Chunyan Wang 0004, M. Omair Ahmad |
An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2790-2793, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Chung-Kuan Tsai, Malgorzata Marek-Sadowska |
Analysis of Process Variation's Effect on SRAM's Read Stability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 603-610, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy 0001 |
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12), pp. 1859-1880, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy 0001 |
A Feasibility Study of Subthreshold SRAM Across Technology Generations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 417-424, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Jinn-Shyan Wang, Po-Hui Yang, Wayne Tseng |
Low-power embedded SRAM macros with current-mode read/write operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 282-287, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
43 | Koji Nii, Hiroshi Makino, Yoshiki Tsujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano |
A low power SRAM using auto-backgate-controlled MT-CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 293-298, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
42 | Anuj Pushkarna, Hamid Mahmoodi |
Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 373-376, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
reliability, aging, SRAM, power gating |
42 | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
A statistical simulation method for reliability analysis of SRAM core-cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 853-856, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
SRAM core-cell, Monte-Carlo, reliability analysis |
42 | Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy 0001 |
A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 670-675, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low power SRAM, supply voltage over-scaling, graceful degradation |
42 | Rouwaida Kanj, Zhuo Li 0001, Rajiv V. Joshi, Frank Liu 0001, Sani R. Nassif |
A Root-Finding Method for Assessing SRAM Stability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 804-809, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
stability, memory, yield, sram, roots |
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