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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 254 occurrences of 125 keywords
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Results
Found 229 publication records. Showing 229 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
57 | Huawei Li 0001, Zhongcheng Li, Yinghua Min |
Reduction of Number of Paths to be Tested in Delay Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 477-485, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
linearly independent, analytical delay model, delay testing, path sensitization |
52 | Huawei Li 0001, Zhongcheng Li, Yinghua Min |
Delay Testing with Double Observations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 96-, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
linearly independent, test generation, observation, delay testing |
45 | Rene David, S. Rahal, J. L. Rainard |
Some relationships between delay testing and stuck-open testing in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 339-343, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
stuck-open, combinational circuits, CMOS, Delay testing, robust test |
39 | Eun Sei Park, M. Ray Mercer |
An efficient delay test generation system for combinational logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(7), pp. 926-938, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
39 | Eun Sei Park, M. Ray Mercer |
An Efficient Delay Test Generation System for Combinational Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 522-528, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
39 | Yuan-Chieh Hsu, Sandeep K. Gupta 0001 |
A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(11), pp. 1312-1318, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
robust path delay testing, at-speed delay testing, fault simulation, Delay testing |
37 | Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 121-126, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
BIST, Random Testing, Delay Testing, Bridging Faults |
37 | Yung-Chieh Lin, Feng Lu 0002, Kai Yang, Kwang-Ting Cheng |
Constraint extraction for pseudo-functional scan-based delay testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 166-171, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand |
Delay Testing Viability of Gate Oxide Short Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 20(2), pp. 195-200, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
gate oxide short (GOS), VLSI, delay testing, defect |
35 | Seiichiro Tani, Mitsuo Teramoto, Tomoo Fukazawa, Kazuyoshi Matsuhiro |
Efficient Path Selection for Delay Testing Based on Path Clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(1-2), pp. 75-85, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
clustering, delay testing, delay fault, path delay |
34 | Premachandran R. Menon, Weifeng Xu, Russell Tessier |
Design-specific path delay testing in lookup-table-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5), pp. 867-877, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Ming-Chien Tsai, Ching-Hwa Cheng |
A full-synthesizable high-precision built-in delay time measurement circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 123-124, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Ming-Chien Tsai, Ching-Hwa Cheng, Chiou-Mao Yang |
An All-Digital High-Precision Built-In Delay Time Measurement Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 249-254, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukherjee |
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 97-104, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
delay defects, delay fault modeling, delay testing, critical paths, statistical timing analysis |
33 | Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch |
An optimized BIST test pattern generator for delay testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 94-100, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test |
32 | Srimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal |
Energy models for delay testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6), pp. 728-739, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
30 | Angela Krstic, Kwang-Ting Cheng |
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(1), pp. 43-54, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
resynthesis for testability, timing defects, delay testing, path delay faults, VLSI testing |
30 | Mehdi Baradaran Tahoori, Subhasish Mitra |
Application-Dependent Delay Testing of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3), pp. 553-563, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Ananta K. Majhi, Vishwani D. Agrawal |
Tutorial: Delay Fault Models and Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 364-369, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
delay fault models, gate delay model, line delay model, path delay model, segment delay model, transition model, Delay test |
27 | Angela Krstic, Kwang-Ting Cheng |
Generation of high quality tests for functional sensitizable paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 374-379, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high quality tests, functional sensitizable paths, long paths, untestable paths, faulty conditions, test derivation, logic testing, delays, timing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, delay testing, test vectors, timing information |
27 | Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng |
Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3), pp. 416-425, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Chih-Ang Chen, Sandeep K. Gupta |
Design of efficient BIST test pattern generators for delay testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12), pp. 1568-1575, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
27 | Antonis M. Paschalis, Dimitris Gizopoulos, Nikolaos Gaitanis |
Concurrent Delay Testing in Totally Self-Checking Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(1-2), pp. 55-61, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
concurrent on-line detection, duplication systems, path delay faults, totally self-checking circuits, error indicators |
25 | Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams |
Enhancing test efficiency for delay fault testing using multiple-clocked schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 371-374, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
transition fault model, delay testing, statistical timing analysis |
25 | Gefu Xu, Adit D. Singh |
Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 763-768, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi |
Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 156-161, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | S. Cremoux, Christophe Fagot, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch |
A new test pattern generation method for delay fault testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 296-301, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
test pattern generation method, directed random generation technique, random test vectors, test sequence length, delay fault coverage, learning (artificial intelligence), VLSI, logic testing, delays, built-in self test, integrated circuit testing, BIST, automatic testing, delay fault testing, digital integrated circuits, learning tool, high speed circuits |
24 | Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura 0001 |
Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 358-363, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng |
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 15-22, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing |
23 | Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu |
An Application-Independent Delay Testing Methodology for Island-Style FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 478-486, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
segment delay fault, FPGA, delay testing, path delay fault |
23 | Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal |
Path Delay Testing: Variable-Clock Versus Rated-Clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 470-475, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
rated-clock testing, slow-clock testing, Delay testing, path delay faults, sequential circuit test |
22 | Arnaud Virazel, René David, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch |
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(3-4), pp. 233-241, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
non-robust test, BIST, random testing, delay testing, robust test |
22 | Kun Young Chung, Sandeep K. Gupta 0001 |
Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 1089-1097, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Joonhwan Yi, John P. Hayes |
High-level delay test generation for modular circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3), pp. 576-590, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Egor S. Sogomonyan, Adit D. Singh, Michael Gössel |
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(1-2), pp. 87-96, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
design-for-testability, BIST, scan design |
20 | Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand |
Delay Testing of MOS Transistor with Gate Oxide Short. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 168-173, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Pamela S. Gillis, Francis Woytowich, Andrew Ferko, Kevin McCauley |
Low Overhead Delay Testing of ASICS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 534-542, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Xiaowei Li 0001, Paul Y. S. Cheung |
High-Level BIST Synthesis for Delay Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 318-, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Haihua Yan, Adit D. Singh |
Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 242-251, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | C. P. Ravikumar, Nitin Agrawal 0003, Parul Agarwal |
Hierarchical Delay Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 10(3), pp. 231-244, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
delay test generation, path selection, hierarchical testing |
19 | Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl |
Considering possible opens in non-tree topology wire delay calculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 17-22, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
non-tree topologies, yield, static timing analysis, delay analysis |
19 | Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams |
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 407-416, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Eric W. MacDonald, Nur A. Touba |
Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(6), pp. 587-595, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | I-De Huang, Sandeep K. Gupta 0001 |
Selection of Paths for Delay Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 208-215, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Mehdi Baradaran Tahoori, Subhasish Mitra |
Interconnect Delay Testing of Designs on Programmable Logic Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 635-644, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal |
The optimistic update theorem for path delay testing in sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(3), pp. 285-290, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
test generation, Fault simulation, timing analysis, path delay faults |
17 | Huawei Li 0001, Yue Zhang, Xiaowei Li 0001 |
Delay Test Pattern Generation Considering Crosstalk-Induced Effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 178-183, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir |
Refined statistical static timing analysis through. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 149-154, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
delay correlations, Bayesian learning, statistical timing |
17 | Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura 0001, Ali Keshavarzi |
Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1276-1284, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Toshiaki Satoh, Hiroyuki Yotsuyanagi, Masaki Hashizume |
On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3DIC ![In: 2019 International 3D Systems Integration Conference (3DIC), Sendai, Japan, October 8-10, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-4870-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
15 | Prasanjeet Das, Sandeep K. Gupta 0001 |
Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013, pp. 1-6, 2013, IEEE Computer Society, 978-1-4673-5542-1. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
15 | Richard Putman, Rahul Gawde |
Enhanced Timing-Based Transition Delay Testing for Small Delay Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 336-342, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda |
Delay Testing: Improving Test Quality and Avoiding Over-testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSJ Trans. Syst. LSI Des. Methodol. ![In: IPSJ Trans. Syst. LSI Des. Methodol. 4, pp. 117-130, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Hong Shin Jun, Sung Soo Chung, Sang H. Baeg |
Removing JTAG Bottlenecks in System Interconnect Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 173-180, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Yung-Chieh Lin, Feng Lu 0002, Kwang-Ting Cheng |
Pseudofunctional testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8), pp. 1535-1546, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | René David, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
Hardware Generation of Random Single Input Change Test Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(2), pp. 145-157, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
single input change, generation, hardware, random testing, test sequence |
15 | Uwe Sparmann, Holger Müller, Sudhakar M. Reddy |
Minimal Delay Test Sets for Unate Gate Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 155-, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
14 | Sying-Jyan Wang, Tung-Hua Yeh |
High-level test synthesis for delay fault testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 45-50, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Bram Kruseman, Ananta K. Majhi, Guido Gronthoud |
On Performance Testing with Path Delay Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 29-34, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Seongmoon Wang, Xiao Liu, Srimat T. Chakradhar |
Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1296-1301, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo |
Test Generation for Multiple-Threshold Gate-Delay Fault Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 244-, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
13 | Mohammad Tehranipoor, Kenneth M. Butler |
Power Supply Noise: A Survey on Effects and Research. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 27(2), pp. 51-67, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
power supply noise (PSN), transition delay fault testing, timing analysis, design and test, path delay testing |
13 | Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi |
A Selective Trigger Scan Architecture for VLSI Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(3), pp. 316-328, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Delay Testing, Test Compression, Test Application Time, Scan Test, Test Data Volume, Test Power |
13 | Kyriakos Christou, Maria K. Michael, Spyros Tragoudas |
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 203-222, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Zero-suppressed binary decision diagram, Irredundant sum-of-products, Critical path delay faults, Compact test generation, Delay testing, Path delay faults |
13 | Paolo Bernardi, Kyriakos Christou, Michelangelo Grosso, Maria K. Michael, Ernesto Sánchez 0001, Matteo Sonza Reorda |
Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoWorkshops ![In: Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings, pp. 224-234, 2008, Springer, 978-3-540-78760-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
microprocessor, BDD, MOEA, path-delay testing |
13 | Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski |
Timing-Aware Multiple-Delay-Fault Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 246-253, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
defect-diagnosis, diagnosis, ATPG, DFT, delay-testing |
13 | I-De Huang, Yi-Shing Chang, Sandeep K. Gupta 0001, Sreejit Chakravarty |
An Industrial Case Study of Sticky Path-Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 395-402, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
sticky paths, timing false paths, path reprioritization, delay testing, test quality |
13 | Donghwi Lee, Erik H. Volkerink, Intaik Park, Jeff Rearick |
Empirical Validation of Yield Recovery Using Idle-Cycle Insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(4), pp. 362-372, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
false failure, ATPG, delay testing, functional test, structural test, IR drop, yield loss |
13 | Kwang-Ting (Tim) Cheng |
Design and CAD for Nanotechnologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(4), pp. 300, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
process diagnosis, CAD, redundancy, CMOS, delay testing, SEU |
13 | Nisar Ahmed, Mohammad Tehranipoor |
Improving Transition Delay Test Using a Hybrid Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(5), pp. 402-412, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
launch-off-capture, delay testing, test quality |
13 | Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram |
Timing-based delay test for screening small delay defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 320-325, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
test generation, delay testing |
13 | Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato |
Path delay test compaction with process variation tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 845-850, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
process variation, delay testing, path delay fault, test compaction |
13 | Ilia Polian, Bernd Becker 0001 |
Scalable Delay Fault BIST for Use with Low-Cost ATE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(2), pp. 181-197, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
thermal constraints, BIST, SAT, delay testing, IP cores, symbolic methods |
13 | Xiao Liu 0010, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran |
Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(4), pp. 437-445, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
stuck-at vectors, delay testing, transition fault |
13 | Ilia Polian, Bernd Becker 0001 |
Multiple Scan Chain Design for Two-Pattern Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(1), pp. 37-48, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
scan chain insertion, delay testing, design for test, core-based test |
13 | Yun Shao 0002, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara |
On Selecting Testable Paths in Scan Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(4), pp. 447-456, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
testable path, delay testing, delay fault, path delay fault, path selection |
13 | Spyros Tragoudas, N. Denny |
Path delay fault testing using test points. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(1), pp. 1-10, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
path delay fault simulation (coverage), testing digital circuits, design for testability, Automatic test pattern generation, delay testing, path delay fault testing |
13 | Dimitrios Kagaris, Spyros Tragoudas |
Using a WLFSR to Embed Test Pattern Pairs in Minimum Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(3), pp. 305-313, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
weighted random LFSRs, two-pattern test sets, built-in self-test, delay testing |
13 | Maria K. Michael, Spyros Tragoudas |
ATPG tools for delay faults at the functional level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(1), pp. 33-57, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
functional-level testing, path delay fault simulation (coverage), testing digital circuits, Automatic test pattern generation, Binary Decision Diagrams, delay testing, Boolean Satisfiability, path delay fault testing |
13 | Ilia Polian, Bernd Becker 0001 |
Stop & Go BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, pp. 147-151, 2002, IEEE Computer Society, 0-7695-1641-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Thermal constraints, BIST, Delay testing, IP cores |
13 | Arun Krishnamachary, Jacob A. Abraham |
Test generation for resistive opens in CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002, pp. 65-70, 2002, ACM, 1-58113-462-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
resistive opens, delay testing, defect detection |
13 | Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich |
Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 3-8, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Microprocessor, Delay Testing |
13 | Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche |
Test Challenges in Nanometer Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(3-4), pp. 209-218, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
circuit marginality testing, process marginality testing, defect based testing, path delay testing |
13 | Ilia Polian, Bernd Becker 0001 |
Multiple Scan Chain Design for Two-Pattern Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 88-93, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Scan chain insertion, Delay testing, Design for test, Core-based test |
13 | Tek Jau Tan, Chung-Len Lee |
Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 158-162, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Oscillation test, Delay testing, System test, SOC testing, Embedded testing |
13 | Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi |
False-Path Removal Using Delay Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 463-476, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
design for testability, fault simulation, Delay testing, path delay faults, synthesis for testability, redundancy removal |
13 | Emil Gizdarski |
Detection of Delay Faults in Memory Address Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(4), pp. 381-387, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Built-In Self-Test, delay testing, stuck-open faults, RAM testing |
13 | Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao, David M. Wu |
Cold Delay Defect Screening. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 183-188, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Manufacturing quality, Reliability, Delay Testing |
13 | Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina |
At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 3-8, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
delay testing, at-speed testing, microprocessor testing |
13 | Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal |
Deriving Logic Systems for Path Delay Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 47(8), pp. 829-846, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
simulation, timing analysis, Delay testing, multivalued logic, path delay faults, digital test |
13 | Zhongcheng Li, Yinghua Min, Robert K. Brayton |
A New Low-Cost Method for Identifying Untestable Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 76-81, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
non-robustly untestable, Delay testing, path delay fault, implication |
13 | Thomas M. Storey, Bruce McWilliam |
A Test Methodology for High Performance MCMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 10(1-2), pp. 109-118, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
LOCST, AC BIST, delay testing, boundary scan, LSSD, MCM testing |
13 | Wangning Long, Shiyuan Yang, Zhongcheng Li, Yinghua Min |
Memory Efficient ATPG for Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 326-331, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Delay Testing, Automatic Test Generation, IC Testing, Path Sensitization |
13 | Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto |
Application of a Design for Delay Testability Approach to High Speed Logic LSIs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 112-115, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Delay Test Generation, Design for Testability, Delay Testing |
13 | Mukund Sivaraman, Andrzej J. Strojwas |
Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 494-501, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
fabrication process, coverage, delay testing, delay fault, path sensitization |
13 | Ankan K. Pramanick, Sudhakar M. Reddy |
Efficient multiple path propagating tests for delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(3), pp. 157-172, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
delay testing, path delay faults, robust tests, test efficiency |
13 | Eun Sei Park, M. Ray Mercer, Thomas W. Williams |
The Total Delay Fault Model and Statistical Delay Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(6), pp. 688-698, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
delay fault model, delay fault coverage, statistical delay fault coverage, defect level model, logic testing, delay testing, delay faults |
13 | Jean Davies Lesser, John J. Shedletsky |
An Experimental Delay Test Generator for LSI Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 29(3), pp. 235-248, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
test generation, Delay testing |
12 | Zhen Chen, Boxue Yin, Dong Xiang |
Conflict driven scan chain configuration for high transition fault coverage and low test power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 666-671, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Kee Sup Kim, Subhasish Mitra, Paul G. Ryan |
Delay Defect Characteristics and Testing Strategies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(5), pp. 8-16, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
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