Search results for "delay-testing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
57	Huawei Li 0001, Zhongcheng Li, Yinghua Min	Reduction of Number of Paths to be Tested in Delay Testing.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	linearly independent, analytical delay model, delay testing, path sensitization
52	Huawei Li 0001, Zhongcheng Li, Yinghua Min	Delay Testing with Double Observations.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF	linearly independent, test generation, observation, delay testing
45	Rene David, S. Rahal, J. L. Rainard	Some relationships between delay testing and stuck-open testing in CMOS circuits.	EURO-DAC	1990	DBLP DOI BibTeX RDF	stuck-open, combinational circuits, CMOS, Delay testing, robust test
39	Eun Sei Park, M. Ray Mercer	An efficient delay test generation system for combinational logic circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
39	Eun Sei Park, M. Ray Mercer	An Efficient Delay Test Generation System for Combinational Logic Circuits.	DAC	1990	DBLP DOI BibTeX RDF
39	Yuan-Chieh Hsu, Sandeep K. Gupta 0001	A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	robust path delay testing, at-speed delay testing, fault simulation, Delay testing
37	Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults.	IOLTW	2000	DBLP DOI BibTeX RDF	BIST, Random Testing, Delay Testing, Bridging Faults
37	Yung-Chieh Lin, Feng Lu 0002, Kai Yang, Kwang-Ting Cheng	Constraint extraction for pseudo-functional scan-based delay testing.	ASP-DAC	2005	DBLP DOI BibTeX RDF
35	Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand	Delay Testing Viability of Gate Oxide Short Defects.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	gate oxide short (GOS), VLSI, delay testing, defect
35	Seiichiro Tani, Mitsuo Teramoto, Tomoo Fukazawa, Kazuyoshi Matsuhiro	Efficient Path Selection for Delay Testing Based on Path Clustering.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	clustering, delay testing, delay fault, path delay
34	Premachandran R. Menon, Weifeng Xu, Russell Tessier	Design-specific path delay testing in lookup-table-based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
34	Ming-Chien Tsai, Ching-Hwa Cheng	A full-synthesizable high-precision built-in delay time measurement circuit.	ASP-DAC	2009	DBLP DOI BibTeX RDF
34	Ming-Chien Tsai, Ching-Hwa Cheng, Chiou-Mao Yang	An All-Digital High-Precision Built-In Delay Time Measurement Circuit.	VTS	2008	DBLP DOI BibTeX RDF
33	Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukherjee	Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis.	VTS	2000	DBLP DOI BibTeX RDF	delay defects, delay fault modeling, delay testing, critical paths, statistical timing analysis
33	Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch	An optimized BIST test pattern generator for delay testing.	VTS	1997	DBLP DOI BibTeX RDF	BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test
32	Srimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal	Energy models for delay testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
30	Angela Krstic, Kwang-Ting Cheng	Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	resynthesis for testability, timing defects, delay testing, path delay faults, VLSI testing
30	Mehdi Baradaran Tahoori, Subhasish Mitra	Application-Dependent Delay Testing of FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
29	Ananta K. Majhi, Vishwani D. Agrawal	Tutorial: Delay Fault Models and Coverage.	VLSI Design	1998	DBLP DOI BibTeX RDF	delay fault models, gate delay model, line delay model, path delay model, segment delay model, transition model, Delay test
27	Angela Krstic, Kwang-Ting Cheng	Generation of high quality tests for functional sensitizable paths.	VTS	1995	DBLP DOI BibTeX RDF	high quality tests, functional sensitizable paths, long paths, untestable paths, faulty conditions, test derivation, logic testing, delays, timing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, delay testing, test vectors, timing information
27	Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng	Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
27	Chih-Ang Chen, Sandeep K. Gupta	Design of efficient BIST test pattern generators for delay testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
27	Antonis M. Paschalis, Dimitris Gizopoulos, Nikolaos Gaitanis	Concurrent Delay Testing in Totally Self-Checking Systems.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	concurrent on-line detection, duplication systems, path delay faults, totally self-checking circuits, error indicators
25	Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams	Enhancing test efficiency for delay fault testing using multiple-clocked schemes.	DAC	2002	DBLP DOI BibTeX RDF	transition fault model, delay testing, statistical timing analysis
25	Gefu Xu, Adit D. Singh	Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing.	VLSI Design	2007	DBLP DOI BibTeX RDF
25	Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi	Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
24	S. Cremoux, Christophe Fagot, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch	A new test pattern generation method for delay fault testing.	VTS	1996	DBLP DOI BibTeX RDF	test pattern generation method, directed random generation technique, random test vectors, test sequence length, delay fault coverage, learning (artificial intelligence), VLSI, logic testing, delays, built-in self test, integrated circuit testing, BIST, automatic testing, delay fault testing, digital integrated circuits, learning tool, high speed circuits
24	Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura 0001	Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?.	VTS	2006	DBLP DOI BibTeX RDF
24	Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng	On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set.	VTS	2000	DBLP DOI BibTeX RDF	Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing
23	Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu	An Application-Independent Delay Testing Methodology for Island-Style FPGA.	DFT	2004	DBLP DOI BibTeX RDF	segment delay fault, FPGA, delay testing, path delay fault
23	Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal	Path Delay Testing: Variable-Clock Versus Rated-Clock.	VLSI Design	1998	DBLP DOI BibTeX RDF	rated-clock testing, slow-clock testing, Delay testing, path delay faults, sequential circuit test
22	Arnaud Virazel, René David, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch	Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	non-robust test, BIST, random testing, delay testing, robust test
22	Kun Young Chung, Sandeep K. Gupta 0001	Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing.	ITC	2003	DBLP DOI BibTeX RDF
22	Joonhwan Yi, John P. Hayes	High-level delay test generation for modular circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
20	Egor S. Sogomonyan, Adit D. Singh, Michael Gössel	A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	design-for-testability, BIST, scan design
20	Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand	Delay Testing of MOS Transistor with Gate Oxide Short.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
20	Pamela S. Gillis, Francis Woytowich, Andrew Ferko, Kevin McCauley	Low Overhead Delay Testing of ASICS.	ITC	2004	DBLP DOI BibTeX RDF
20	Xiaowei Li 0001, Paul Y. S. Cheung	High-Level BIST Synthesis for Delay Testing.	DFT	1998	DBLP DOI BibTeX RDF
19	Haihua Yan, Adit D. Singh	Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study.	ITC	2004	DBLP DOI BibTeX RDF
19	C. P. Ravikumar, Nitin Agrawal 0003, Parul Agarwal	Hierarchical Delay Test Generation.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	delay test generation, path selection, hierarchical testing
19	Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl	Considering possible opens in non-tree topology wire delay calculation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	non-tree topologies, yield, static timing analysis, delay analysis
19	Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams	Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme.	ITC	2002	DBLP DOI BibTeX RDF
17	Eric W. MacDonald, Nur A. Touba	Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
17	I-De Huang, Sandeep K. Gupta 0001	Selection of Paths for Delay Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
17	Mehdi Baradaran Tahoori, Subhasish Mitra	Interconnect Delay Testing of Designs on Programmable Logic Devices.	ITC	2004	DBLP DOI BibTeX RDF
17	Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal	The optimistic update theorem for path delay testing in sequential circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	test generation, Fault simulation, timing analysis, path delay faults
17	Huawei Li 0001, Yue Zhang, Xiaowei Li 0001	Delay Test Pattern Generation Considering Crosstalk-Induced Effects.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
17	Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir	Refined statistical static timing analysis through.	DAC	2006	DBLP DOI BibTeX RDF	delay correlations, Bayesian learning, statistical timing
17	Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura 0001, Ali Keshavarzi	Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism.	ITC	2004	DBLP DOI BibTeX RDF
15	Toshiaki Satoh, Hiroyuki Yotsuyanagi, Masaki Hashizume	On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection.	3DIC	2019	DBLP DOI BibTeX RDF
15	Prasanjeet Das, Sandeep K. Gupta 0001	Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning.	VTS	2013	DBLP DOI BibTeX RDF
15	Richard Putman, Rahul Gawde	Enhanced Timing-Based Transition Delay Testing for Small Delay Defects.	VTS	2006	DBLP DOI BibTeX RDF
15	Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda	Delay Testing: Improving Test Quality and Avoiding Over-testing.	IPSJ Trans. Syst. LSI Des. Methodol.	2011	DBLP DOI BibTeX RDF
15	Hong Shin Jun, Sung Soo Chung, Sang H. Baeg	Removing JTAG Bottlenecks in System Interconnect Test.	ITC	2004	DBLP DOI BibTeX RDF
15	Yung-Chieh Lin, Feng Lu 0002, Kwang-Ting Cheng	Pseudofunctional testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
15	René David, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Hardware Generation of Random Single Input Change Test Sequences.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	single input change, generation, hardware, random testing, test sequence
15	Uwe Sparmann, Holger Müller, Sudhakar M. Reddy	Minimal Delay Test Sets for Unate Gate Networks.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
14	Sying-Jyan Wang, Tung-Hua Yeh	High-level test synthesis for delay fault testability.	DATE	2007	DBLP DOI BibTeX RDF
14	Bram Kruseman, Ananta K. Majhi, Guido Gronthoud	On Performance Testing with Path Delay Patterns.	VTS	2007	DBLP DOI BibTeX RDF
14	Seongmoon Wang, Xiao Liu, Srimat T. Chakradhar	Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets.	DATE	2004	DBLP DOI BibTeX RDF
14	Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo	Test Generation for Multiple-Threshold Gate-Delay Fault Model.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
13	Mohammad Tehranipoor, Kenneth M. Butler	Power Supply Noise: A Survey on Effects and Research.	IEEE Des. Test Comput.	2010	DBLP DOI BibTeX RDF	power supply noise (PSN), transition delay fault testing, timing analysis, design and test, path delay testing
13	Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi	A Selective Trigger Scan Architecture for VLSI Testing.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Delay Testing, Test Compression, Test Application Time, Scan Test, Test Data Volume, Test Power
13	Kyriakos Christou, Maria K. Michael, Spyros Tragoudas	On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Zero-suppressed binary decision diagram, Irredundant sum-of-products, Critical path delay faults, Compact test generation, Delay testing, Path delay faults
13	Paolo Bernardi, Kyriakos Christou, Michelangelo Grosso, Maria K. Michael, Ernesto Sánchez 0001, Matteo Sonza Reorda	Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors.	EvoWorkshops	2008	DBLP DOI BibTeX RDF	microprocessor, BDD, MOEA, path-delay testing
13	Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski	Timing-Aware Multiple-Delay-Fault Diagnosis.	ISQED	2008	DBLP DOI BibTeX RDF	defect-diagnosis, diagnosis, ATPG, DFT, delay-testing
13	I-De Huang, Yi-Shing Chang, Sandeep K. Gupta 0001, Sreejit Chakravarty	An Industrial Case Study of Sticky Path-Delay Faults.	VTS	2008	DBLP DOI BibTeX RDF	sticky paths, timing false paths, path reprioritization, delay testing, test quality
13	Donghwi Lee, Erik H. Volkerink, Intaik Park, Jeff Rearick	Empirical Validation of Yield Recovery Using Idle-Cycle Insertion.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	false failure, ATPG, delay testing, functional test, structural test, IR drop, yield loss
13	Kwang-Ting (Tim) Cheng	Design and CAD for Nanotechnologies.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	process diagnosis, CAD, redundancy, CMOS, delay testing, SEU
13	Nisar Ahmed, Mohammad Tehranipoor	Improving Transition Delay Test Using a Hybrid Method.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	launch-off-capture, delay testing, test quality
13	Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram	Timing-based delay test for screening small delay defects.	DAC	2006	DBLP DOI BibTeX RDF	test generation, delay testing
13	Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato	Path delay test compaction with process variation tolerance.	DAC	2005	DBLP DOI BibTeX RDF	process variation, delay testing, path delay fault, test compaction
13	Ilia Polian, Bernd Becker 0001	Scalable Delay Fault BIST for Use with Low-Cost ATE.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	thermal constraints, BIST, SAT, delay testing, IP cores, symbolic methods
13	Xiao Liu 0010, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran	Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	stuck-at vectors, delay testing, transition fault
13	Ilia Polian, Bernd Becker 0001	Multiple Scan Chain Design for Two-Pattern Testing.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	scan chain insertion, delay testing, design for test, core-based test
13	Yun Shao 0002, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara	On Selecting Testable Paths in Scan Designs.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	testable path, delay testing, delay fault, path delay fault, path selection
13	Spyros Tragoudas, N. Denny	Path delay fault testing using test points.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	path delay fault simulation (coverage), testing digital circuits, design for testability, Automatic test pattern generation, delay testing, path delay fault testing
13	Dimitrios Kagaris, Spyros Tragoudas	Using a WLFSR to Embed Test Pattern Pairs in Minimum Time.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	weighted random LFSRs, two-pattern test sets, built-in self-test, delay testing
13	Maria K. Michael, Spyros Tragoudas	ATPG tools for delay faults at the functional level.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	functional-level testing, path delay fault simulation (coverage), testing digital circuits, Automatic test pattern generation, Binary Decision Diagrams, delay testing, Boolean Satisfiability, path delay fault testing
13	Ilia Polian, Bernd Becker 0001	Stop & Go BIST.	IOLTW	2002	DBLP DOI BibTeX RDF	Thermal constraints, BIST, Delay testing, IP cores
13	Arun Krishnamachary, Jacob A. Abraham	Test generation for resistive opens in CMOS.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	resistive opens, delay testing, defect detection
13	Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich	Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.	VTS	2002	DBLP DOI BibTeX RDF	Microprocessor, Delay Testing
13	Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche	Test Challenges in Nanometer Technologies.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	circuit marginality testing, process marginality testing, defect based testing, path delay testing
13	Ilia Polian, Bernd Becker 0001	Multiple Scan Chain Design for Two-Pattern Testing.	VTS	2001	DBLP DOI BibTeX RDF	Scan chain insertion, Delay testing, Design for test, Core-based test
13	Tek Jau Tan, Chung-Len Lee	Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment.	VTS	2001	DBLP DOI BibTeX RDF	Oscillation test, Delay testing, System test, SOC testing, Embedded testing
13	Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi	False-Path Removal Using Delay Fault Simulation.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	design for testability, fault simulation, Delay testing, path delay faults, synthesis for testability, redundancy removal
13	Emil Gizdarski	Detection of Delay Faults in Memory Address Decoders.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	Built-In Self-Test, delay testing, stuck-open faults, RAM testing
13	Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao, David M. Wu	Cold Delay Defect Screening.	VTS	2000	DBLP DOI BibTeX RDF	Manufacturing quality, Reliability, Delay Testing
13	Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina	At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor.	VTS	2000	DBLP DOI BibTeX RDF	delay testing, at-speed testing, microprocessor testing
13	Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal	Deriving Logic Systems for Path Delay Test Generation.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	simulation, timing analysis, Delay testing, multivalued logic, path delay faults, digital test
13	Zhongcheng Li, Yinghua Min, Robert K. Brayton	A New Low-Cost Method for Identifying Untestable Path Delay Faults.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF	non-robustly untestable, Delay testing, path delay fault, implication
13	Thomas M. Storey, Bruce McWilliam	A Test Methodology for High Performance MCMs.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	LOCST, AC BIST, delay testing, boundary scan, LSSD, MCM testing
13	Wangning Long, Shiyuan Yang, Zhongcheng Li, Yinghua Min	Memory Efficient ATPG for Path Delay Faults.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Delay Testing, Automatic Test Generation, IC Testing, Path Sensitization
13	Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto	Application of a Design for Delay Testability Approach to High Speed Logic LSIs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Delay Test Generation, Design for Testability, Delay Testing
13	Mukund Sivaraman, Andrzej J. Strojwas	Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults.	ICCAD	1996	DBLP DOI BibTeX RDF	fabrication process, coverage, delay testing, delay fault, path sensitization
13	Ankan K. Pramanick, Sudhakar M. Reddy	Efficient multiple path propagating tests for delay faults.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	delay testing, path delay faults, robust tests, test efficiency
13	Eun Sei Park, M. Ray Mercer, Thomas W. Williams	The Total Delay Fault Model and Statistical Delay Fault Coverage.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	delay fault model, delay fault coverage, statistical delay fault coverage, defect level model, logic testing, delay testing, delay faults
13	Jean Davies Lesser, John J. Shedletsky	An Experimental Delay Test Generator for LSI Logic.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	test generation, Delay testing
12	Zhen Chen, Boxue Yin, Dong Xiang	Conflict driven scan chain configuration for high transition fault coverage and low test power.	ASP-DAC	2009	DBLP DOI BibTeX RDF
12	Kee Sup Kim, Subhasish Mitra, Paul G. Ryan	Delay Defect Characteristics and Testing Strategies.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF