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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2051 occurrences of 802 keywords
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Results
Found 1533 publication records. Showing 1518 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
94 | Brian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee |
Diagnosis of realistic bridging faults with single stuck-at information. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
match requirement, match restriction, realistic bridging faults diagnosis, single stuck-at dictionaries, single stuck-at information, stuck-at diagnosis, stuck-at methods, fault diagnosis, logic testing, fault location, failure analysis, failure recovery |
76 | Sreejit Chakravarty |
A characterization of robust test-pairs for stuck-open faults. |
J. Electron. Test. |
1991 |
DBLP DOI BibTeX RDF |
fault simulation, robust tests, stuck-open faults, test generation algorithms |
72 | Hyung Ki Lee, Dong Sam Ha, Kwanghyun Kim |
Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational Circuits. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
68 | Zaifu Zhang, Robert D. McLeod, Witold Pedrycz |
A neural network algorithm for testing stuck-open faults in CMOS combinational circuits. |
J. Electron. Test. |
1993 |
DBLP DOI BibTeX RDF |
stuck-open and gate delay faults, Neural networks, test pattern generation |
67 | Irith Pomeranz, Sudhakar M. Reddy |
On achieving complete fault coverage for sequential machines. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
67 | Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer |
On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
DO-RE-ME technique, MPG-D model, defective part level prediction, benchmark circuit simulations, stuck-at fault detection tests, bridging surrogate detection, stuck-at fault coverage, predictor accuracy, industrial circuit, test pattern sequences, integrated circuit testing, automatic test pattern generation, ATPG, fault simulation, logic circuit, circuit simulation, integrated logic circuits, correlation coefficient |
65 | Michiko Inoue, Emil Gizdarski, Hideo Fujiwara |
A class of sequential circuits with combinational test generation complexity under single-fault assumption. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault |
63 | Bin Liu, Fabrizio Lombardi, Wei-Kang Huang |
Testing programmable interconnect systems: an algorithmic approach. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
programmable circuits, interconnected systems, programmable interconnect systems testing, algorithmic approach, programmable wiring networks, comprehensive fault model, network faults, open faults, switch faults, stuck-off faults, programming faults, minimal configuration number, node-disjoint path-sets, network adjacencies, post-processing algorithm, fault diagnosis, graphs, interconnections, fault detection, fault coverage, circuit analysis computing, stuck-at faults, switching, bridge faults, automatic test software, circuit testing, figure of merit, programming phases, stuck-on faults, short circuits |
63 | Hiroyuki Goto, Shigeo Nakamura, Kazuhiko Iwasaki |
Experimental fault analysis of 1 Mb SRAM chips. |
VTS |
1997 |
DBLP DOI BibTeX RDF |
stuck-at cell faults, stuck-at bit-line faults, stuck-at word-line fault, neighborhood-pattern-sensitive faults, load capacity, margin fault detection, 1 Mbit, 70 C, 30 pF, memory testing, fault analysis, SRAM chips, SRAM chips |
62 | Janusz A. Starzyk, Dong Liu |
Locating stuck faults in analog circuits. |
ISCAS (3) |
2002 |
DBLP DOI BibTeX RDF |
|
62 | Niraj K. Jha, Qiao Tong |
Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
61 | Mostafa I. H. Abd-El-Barr, Yanging Xu, Carl McCrosky |
Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
Transistor stuck-open fault, multi-level CMOS circuits testing, robust CMOS testing, test pattern generation, two-pattern test |
61 | Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis |
Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools. |
J. Electron. Test. |
1998 |
DBLP DOI BibTeX RDF |
cell fault model (CFM), fault simulation, test pattern generation, stuck-at fault model |
61 | Peter C. Maxwell |
The use of IDDQ testing in low stuck-at coverage situations. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
stuck-at coverage situations, quality goal, graded coverage, composite metric, fault diagnosis, logic testing, logic tests, integrated circuit testing, automatic testing, application specific integrated circuits, ASIC, CMOS logic circuits, IDDQ testing, IC testing |
57 | Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
Faults in scan cells, stuck-at and stuck-on faults |
55 | Irith Pomeranz, Sudhakar M. Reddy |
Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
53 | Tapan J. Chakraborty, Vishwani D. Agrawal |
Simulation of at-speed tests for stuck-at faults. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
stuck-at fault detectability, at-speed test simulation, delayed signal transitions, timing hazards, fault simulation method, delay-hazard robust test coverage, timing considerations, high performance circuits, fault diagnosis, logic testing, delays, timing, integrated circuit testing, circuit analysis computing, hazards and race conditions, path delays, high speed test |
53 | Tapan J. Chakraborty, Vishwani D. Agrawal |
Robust testing for stuck-at faults. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
logic circuit testing, d-robust tests, fault diagnosis, logic testing, delays, sequential circuits, sequential circuits, fault models, combinational circuits, combinational circuit, robust testing, single stuck-at faults, circuit models |
53 | Rene David, S. Rahal, J. L. Rainard |
Some relationships between delay testing and stuck-open testing in CMOS circuits. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
stuck-open, combinational circuits, CMOS, Delay testing, robust test |
52 | Irith Pomeranz, Sudhakar M. Reddy |
Test sequences to achieve high defect coverage for synchronous sequential circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
52 | Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò |
Fault simulation of unconventional faults in CMOS circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1991 |
DBLP DOI BibTeX RDF |
|
52 | Michael Nicolaidis |
Shorts in self-checking circuits. |
J. Electron. Test. |
1991 |
DBLP DOI BibTeX RDF |
strongly fault-secure circuits, transistor faults, error detecting codes, self-checking circuits, totally self-checking circuits |
50 | Manoj Singh Gaur, Raghavendra Narasimhan, Vijay Laxmi, Ujjwal Kumar |
Structural Fault Modelling in Nano Devices. |
NanoNet |
2008 |
DBLP DOI BibTeX RDF |
Structural fault, stuck-at-0, stuck-at-1, MRF, bridge, TMR |
50 | Parag K. Lala, Anup Singh, Alvernon Walker |
A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs. |
DFT |
1999 |
DBLP DOI BibTeX RDF |
DCVSL, Stuck-ON/OFF, Stuck-at Faults, Self-testing |
50 | Kent L. Einspahr, Sharad C. Seth |
A switch-level test generation system for synchronous and asynchronous circuits. |
J. Electron. Test. |
1995 |
DBLP DOI BibTeX RDF |
reverse time processing, stuck-open and stuck-at faults, time-frame expansion, sequential circuits, Automatic test generation |
47 | Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy |
On Improving Defect Coverage of Stuck-at Fault Tests. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Cédric Fournet, C. A. R. Hoare, Sriram K. Rajamani, Jakob Rehof |
Stuck-Free Conformance. |
CAV |
2004 |
DBLP DOI BibTeX RDF |
|
47 | Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz |
Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
47 | Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell |
A Complete Characterization of Path Delay Faults through Stuck-at Faults. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
46 | Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001 |
Simulating Resistive Bridging and Stuck-At Faults. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
Resistive stuck-at faults, probabilistic fault coverage, Resistive bridging faults, bridging fault simulation |
46 | Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana |
Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using IDDQ Testing in BiCMOS and CMOS Circuits. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
input pattern classification, BiCMOS circuits, quiescent power supply current monitoring, enhanced I/sub DDQ/, fault diagnosis, bridging faults, CMOS circuits, I/sub DDQ/ testing, stuck-ON faults |
46 | Alok Agrawal, Alexander Saldanha, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
Compact and complete test set generation for multiple stuck-faults. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
Multiple stuck faults, complete test set generation, irrepressible faults |
46 | Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs |
Dynamic diagnosis of sequential circuits based on stuck-at faults. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
dynamic diagnosis, stuck-at fault simulation, cause-effect analysis, effect-cause analysis, error propagation back-trace, fault diagnosis, logic testing, sequential circuits, synchronous sequential circuit, matching algorithm |
46 | Tapan J. Chakraborty, Vishwani D. Agrawal |
Design for high-speed testability of stuck-at faults. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
design for high-speed testability, stuck-at fault detection, signal transition, timing hazard, multivalue algebra, dh-robust test, sequential feedback, reconvergent fanout, cycle-free sequential circuit, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, partial scan, test generation algorithm, critical path delay |
45 | Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
Detectability of internal bridging faults in scan chains. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
45 | Feng Shi 0010, Yiorgos Makris |
A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines. |
ASYNC |
2006 |
DBLP DOI BibTeX RDF |
|
45 | Sunjaya Djaja, Glenn H. Chapman, Desmond Y. H. Cheung, Yves Audet |
Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS). |
DFT |
2003 |
DBLP DOI BibTeX RDF |
photodiode APS, fault-tolerance, redundancy, SOC, CMOS image sensor, active pixel sensor |
43 | Wuudiann Ke, Premachandran R. Menon |
Multifault testability of delay-testable circuits. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
delay-testable circuits, multifault testability, path-delay-fault testability, multiple stuck-at-fault testability, multilevel combinational circuits, robust path-delay-fault test set, logic testing, delays, combinational circuits, multivalued logic circuits |
43 | Andrej Zemva, Franc Brglez |
Detectable perturbations: a paradigm for technology-specific multi-fault test generation. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
detectable perturbations, technology-specific multi-fault test generation, multiple bridging, open faults, single-output modules, multi-output modules, mutation faults, technology-mapped cells, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, stuck-at faults, cellular arrays, benchmark circuits, generic system |
42 | V. Kim, T. Chen |
Assessing SRAM test coverage for sub-micron CMOS technologies. |
VTS |
1997 |
DBLP DOI BibTeX RDF |
submicron CMOS technologies, SRAM test coverage assessment, memory fault probability model, memory array, data retention faults, memory fault coverages, memory test algorithms, functional fault class coverages, 0.5 to 1 mum, stuck-at faults, transition faults, stuck-open faults, coupling faults, physical defects, CMOS memory circuits |
42 | Salvador Manich, Michael Nicolaidis, Joan Figueras |
Enhancing realistic fault secureness in parity prediction array arithmetic operators by IDDQ monitoring. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
mathematical operators, parity prediction array arithmetic operators, IDDQ current monitoring, fault diagnosis, logic testing, fault detection, stuck-at faults, bridging faults, multiplying circuits, multiplier circuit, arithmetic circuits, logic arrays, stuck-open faults, topological design, SPICE simulation, fault secureness |
42 | Samy Makar, Edward J. McCluskey |
Checking experiments to test latches. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults |
41 | Niraj K. Jha |
Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
CVS parity trees, strongly self-checking parity, single stuck-at, stuck-open, stuck-on fault detection, cascode voltage switch, differential cascode voltage switch, EX-OR gates, single-ended cascode voltage switch, logic testing, fault location, logic gates, two-rail checkers |
40 | Irith Pomeranz, Sudhakar M. Reddy |
Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
40 | Subhamoy Maitra, Goutam Paul 0001 |
Recovering RC4 Permutation from 2048 Keystream Bytes if jIs Stuck. |
ACISP |
2008 |
DBLP DOI BibTeX RDF |
Cryptanalysis, Stream Cipher, Permutation, Fault Analysis, RC4, Keystream |
40 | Hitoshi Miyanaka, Norihiko Wada, Tetsushi Kamegawa, Noritaka Sato, Shingo Tsukui, Hiroki Igarashi, Fumitoshi Matsuno |
Development of an unit type robot "KOHGA2" with stuck avoidance ability. |
ICRA |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara |
Efficient path delay test generation based on stuck-at test generation using checker circuitry. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Gang Chen 0011, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski |
New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Hitoshi Kimura, Shigeo Hirose, Keisuke Shimizu |
Stuck Evasion Control for Active-wheel Passive-joint Snake-like Mobile Robot 'Genbu'. |
ICRA |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu |
Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, M. Enamul Amyeen |
Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara |
A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Baris Arslan, Alex Orailoglu |
Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Meine van der Meulen |
Model Checking the Design of an Unrestricted, Stuck-at Fault Tolerant, Asynchronous Sequential Circuit Using SMV. |
FMCAD |
2002 |
DBLP DOI BibTeX RDF |
|
40 | Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu |
Test Generation for Double Stuck-at Faults. |
Asian Test Symposium |
2001 |
DBLP DOI BibTeX RDF |
|
40 | Michael J. Bryan, Srinivas Devadas, Kurt Keutzer |
Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1992 |
DBLP DOI BibTeX RDF |
|
40 | Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya |
CMOS Stuck-open Fault Detection Using Single Test Patterns. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
40 | Sarma Sastry, Melvin A. Breuer |
Detectability of CMOS stuck-open faults using random and pseudorandom test sequences. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1988 |
DBLP DOI BibTeX RDF |
|
38 | Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya |
Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability. |
J. Electron. Test. |
2006 |
DBLP DOI BibTeX RDF |
universal tests, stuck-at fault, path-delay fault, synthesis-for-testability, unate function, symmetric boolean function |
38 | Shalini Ghosh, F. Joel Ferguson |
Estimating detection probability of interconnect opens using stuck-at tests. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
break fault, interconnect open, stuck-at test |
38 | Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty |
Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
stuck-at fault diagnosis, Fault simulation |
38 | Xiao Sun 0002, Carmie Hull |
Functional Verification Coverage vs. Physical Stuck-at Fault Coverage. |
DFT |
1998 |
DBLP DOI BibTeX RDF |
functional property, stuck-at fault coverage, verification coverage, UIO, verification, validation, ATPG, FSM, signature analysis, test application time |
38 | Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki |
Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
DFT circuit, test generation, pass-transistor logic, stuck-on fault |
38 | Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham |
Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
waveform analysis, nonrobust tests, stuck-fault detection, signal waveform analysis, signal waveform integration, directed random test generation techniques, fault diagnosis, logic testing, redundancy, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, detectability, fault coverage, test application time, redundant faults |
38 | Karen Panetta Lentz, Elias S. Manolakos, Edward C. Czeck |
On the simulation of Multiple Stuck-at Faults using Multiple Domain Concurrent and Comparative Simulation. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
multiple stuck-at fault simulation, multiple domain simulation, comparative simulation, MDCCS, discrete event concurrent simulation, CPU time efficiency, digital logic fault simulation, fault diagnosis, logic testing, discrete event simulation, circuit analysis computing, fault location, concurrent engineering |
38 | Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng |
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions |
37 | Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israel Koren, Zahava Koren |
Quantitative Analysis of In-Field Defects in Image Sensor Arrays. |
DFT |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Michelle L. La Haye, Glenn H. Chapman, Cory Jung, Desmond Y. H. Cheung, Sunjaya Djaja, Benjamin Wang, Gary Liaw, Yves Audet |
Characteristics of Fault-Tolerant Photodiode and Photogate Active Pixel Sensor (APS). |
DFT |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Michiko Inoue, Emil Gizdarski, Hideo Fujiwara |
Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. |
J. Electron. Test. |
2002 |
DBLP DOI BibTeX RDF |
internally balanced structure, test generation, sequential circuit, combinational circuit, balanced structure |
37 | Chien-Mo James Li, Edward J. McCluskey |
Diagnosis of Sequence-Dependent Chips. |
VTS |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Kunihito Yamamori, Toru Abe, Susumu Horiguchi |
Performance Evaluation of a Partial Retraining Scheme for Defective Multi-Layer Neural Networks. |
ACSAC |
2001 |
DBLP DOI BibTeX RDF |
|
37 | A. B. M. Harun-ur Rashid, Mazuhidul Karim, Syed Mahfuzul Aziz |
Testing complementary pass-transistor logic circuits. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
37 | Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi |
False-Path Removal Using Delay Fault Simulation. |
J. Electron. Test. |
2000 |
DBLP DOI BibTeX RDF |
design for testability, fault simulation, Delay testing, path delay faults, synthesis for testability, redundancy removal |
37 | Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou |
On Testability of Multiple Precharged Domino Logic. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Piotr R. Sidorowicz |
Modeling and Testing Transistor Faults in Content-Addressable Memories. |
MTDT |
1999 |
DBLP DOI BibTeX RDF |
|
37 | Moritoshi Yasunaga, I. Hachiya, K. Moki, Jung Hwan Kim |
Fault-tolerant self-organizing map implemented by wafer-scale integration. |
IEEE Trans. Very Large Scale Integr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
37 | Wen-Ben Jone, Patrick H. Madden |
Multiple fault testing using minimal single fault test set for fanout-free circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
37 | Patrick Kam Lui, Jon C. Muzio |
Constrained parity testing. |
J. Electron. Test. |
1991 |
DBLP DOI BibTeX RDF |
compaction testing, parity testing, Built-in self-test, signature analysis |
36 | Wuudiann Ke, Premachandran R. Menon |
Multifault and delay-fault testability of multilevel circuits. |
J. Electron. Test. |
1995 |
DBLP DOI BibTeX RDF |
testing, testability, delay-faults, multiple stuck-at faults |
36 | Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck |
Deterministic test generation for non-classical faults on the gate level. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST |
36 | Sumit Ghosh, Tapan J. Chakraborty |
On behavior fault modeling for digital designs. |
J. Electron. Test. |
1991 |
DBLP DOI BibTeX RDF |
fault coverage correlation, fault model, fault simulation, stuck-at fault, behavior model |
36 | Michele Favalli, Piero Olivo, Bruno Riccò, Fabio Somenzi |
Fault simulation for general FCMOS ICs. |
J. Electron. Test. |
1991 |
DBLP DOI BibTeX RDF |
fault simulation, bridging faults, CMOS circuits, stuck-open faults, critical path analysis |
34 | Tobias Drey, Fabian Fischbach, Pascal Jansen, Julian Frommel, Michael Rietzler, Enrico Rukzio |
To Be or Not to Be Stuck, or Is It a Continuum?: A Systematic Literature Review on the Concept of Being Stuck in Games. |
Proc. ACM Hum. Comput. Interact. |
2021 |
DBLP DOI BibTeX RDF |
|
34 | Malay Kule, Hafizur Rahaman 0001, Bhargab B. Bhattacharya |
Maximal Defect-Free Component in Nanoscale Crossbar Circuits Amidst Stuck-Open and Stuck-Closed Faults. |
J. Circuits Syst. Comput. |
2019 |
DBLP DOI BibTeX RDF |
|
34 | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu |
Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud |
Stuck-open fault diagnosis with stuck-at model. |
ETS |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud |
A novel stuck-at based method for transistor stuck-open fault diagnosis. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Yeong-Ruey Shieh, Cheng-Wen Wu |
Design of CMOS PSCD Circuits and Checkers for Stuck-At and Stuck-On Faults. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
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34 | Irith Pomeranz, Sudhakar M. Reddy |
Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage. |
VTS |
1998 |
DBLP DOI BibTeX RDF |
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34 | Manjit S. Cheema, Parag K. Lala |
A new technique for totally self-checking CMOS circuit design for stuck-on and stuck-off faults. |
VTS |
1992 |
DBLP DOI BibTeX RDF |
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34 | François Darlay |
Detection of multiple stuck-on/stuck-open faults by single faults test sets in MOS transistor networks. |
Microprocessing and Microprogramming |
1991 |
DBLP DOI BibTeX RDF |
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34 | Joseph L. A. Hughes, Edward J. McCluskey |
Multiple Stuck-At Fault Coverage of Single Stuck-At Fault Test Sets. |
ITC |
1986 |
DBLP BibTeX RDF |
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32 | Osman Hasan, Naeem Abbasi, Sofiène Tahar |
Formal Probabilistic Analysis of Stuck-at Faults in Reconfigurable Memory Arrays. |
IFM |
2009 |
DBLP DOI BibTeX RDF |
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32 | Jan Schat |
Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns. |
DDECS |
2008 |
DBLP DOI BibTeX RDF |
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32 | Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. |
DFT |
2008 |
DBLP DOI BibTeX RDF |
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32 | Elham K. Moghaddam, Shaahin Hessabi |
An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
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32 | Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001 |
Simulating Resistive-Bridging and Stuck-At Faults. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
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32 | Ruifeng Guo, Subhasish Mitra, M. Enamul Amyeen, Jinkyu Lee, Srihari Sivaraj, Srikanth Venkataraman |
Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
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32 | Chien-Mo James Li, Edward J. McCluskey |
Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
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32 | Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya |
Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
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