The FacetedDBLP logo    Search for: in:

Disable automatic phrases ?     Syntactic query expansion: ?

Searching for stuck with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1972-1978 (16) 1979-1981 (17) 1982-1983 (18) 1984-1986 (28) 1987-1988 (30) 1989-1990 (43) 1991 (26) 1992 (23) 1993 (27) 1994 (33) 1995 (83) 1996 (40) 1997 (56) 1998 (57) 1999 (69) 2000 (71) 2001 (46) 2002 (57) 2003 (66) 2004 (78) 2005 (74) 2006 (90) 2007 (91) 2008 (86) 2009 (58) 2010 (17) 2011-2012 (26) 2013-2014 (20) 2015 (19) 2016 (16) 2017 (19) 2018 (20) 2019 (25) 2020 (16) 2021-2022 (30) 2023 (20) 2024 (7)
Publication types (Num. hits)
article(531) incollection(1) inproceedings(984) phdthesis(1) proceedings(1)
Venues (Conferences, Journals, ...)
GrowBag graphs for keyword ? (Num. hits/coverage)

Group by:
The graphs summarize 2051 occurrences of 802 keywords

Results
Found 1533 publication records. Showing 1518 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
94Brian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee Diagnosis of realistic bridging faults with single stuck-at information. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF match requirement, match restriction, realistic bridging faults diagnosis, single stuck-at dictionaries, single stuck-at information, stuck-at diagnosis, stuck-at methods, fault diagnosis, logic testing, fault location, failure analysis, failure recovery
76Sreejit Chakravarty A characterization of robust test-pairs for stuck-open faults. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF fault simulation, robust tests, stuck-open faults, test generation algorithms
72Hyung Ki Lee, Dong Sam Ha, Kwanghyun Kim Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational Circuits. Search on Bibsonomy DAC The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
68Zaifu Zhang, Robert D. McLeod, Witold Pedrycz A neural network algorithm for testing stuck-open faults in CMOS combinational circuits. Search on Bibsonomy J. Electron. Test. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF stuck-open and gate delay faults, Neural networks, test pattern generation
67Irith Pomeranz, Sudhakar M. Reddy On achieving complete fault coverage for sequential machines. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
67Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF DO-RE-ME technique, MPG-D model, defective part level prediction, benchmark circuit simulations, stuck-at fault detection tests, bridging surrogate detection, stuck-at fault coverage, predictor accuracy, industrial circuit, test pattern sequences, integrated circuit testing, automatic test pattern generation, ATPG, fault simulation, logic circuit, circuit simulation, integrated logic circuits, correlation coefficient
65Michiko Inoue, Emil Gizdarski, Hideo Fujiwara A class of sequential circuits with combinational test generation complexity under single-fault assumption. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault
63Bin Liu, Fabrizio Lombardi, Wei-Kang Huang Testing programmable interconnect systems: an algorithmic approach. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF programmable circuits, interconnected systems, programmable interconnect systems testing, algorithmic approach, programmable wiring networks, comprehensive fault model, network faults, open faults, switch faults, stuck-off faults, programming faults, minimal configuration number, node-disjoint path-sets, network adjacencies, post-processing algorithm, fault diagnosis, graphs, interconnections, fault detection, fault coverage, circuit analysis computing, stuck-at faults, switching, bridge faults, automatic test software, circuit testing, figure of merit, programming phases, stuck-on faults, short circuits
63Hiroyuki Goto, Shigeo Nakamura, Kazuhiko Iwasaki Experimental fault analysis of 1 Mb SRAM chips. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF stuck-at cell faults, stuck-at bit-line faults, stuck-at word-line fault, neighborhood-pattern-sensitive faults, load capacity, margin fault detection, 1 Mbit, 70 C, 30 pF, memory testing, fault analysis, SRAM chips, SRAM chips
62Janusz A. Starzyk, Dong Liu Locating stuck faults in analog circuits. Search on Bibsonomy ISCAS (3) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
62Niraj K. Jha, Qiao Tong Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring. Search on Bibsonomy EURO-DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
61Mostafa I. H. Abd-El-Barr, Yanging Xu, Carl McCrosky Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Transistor stuck-open fault, multi-level CMOS circuits testing, robust CMOS testing, test pattern generation, two-pattern test
61Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools. Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF cell fault model (CFM), fault simulation, test pattern generation, stuck-at fault model
61Peter C. Maxwell The use of IDDQ testing in low stuck-at coverage situations. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF stuck-at coverage situations, quality goal, graded coverage, composite metric, fault diagnosis, logic testing, logic tests, integrated circuit testing, automatic testing, application specific integrated circuits, ASIC, CMOS logic circuits, IDDQ testing, IC testing
57Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. Search on Bibsonomy VTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Faults in scan cells, stuck-at and stuck-on faults
55Irith Pomeranz, Sudhakar M. Reddy Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
53Tapan J. Chakraborty, Vishwani D. Agrawal Simulation of at-speed tests for stuck-at faults. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF stuck-at fault detectability, at-speed test simulation, delayed signal transitions, timing hazards, fault simulation method, delay-hazard robust test coverage, timing considerations, high performance circuits, fault diagnosis, logic testing, delays, timing, integrated circuit testing, circuit analysis computing, hazards and race conditions, path delays, high speed test
53Tapan J. Chakraborty, Vishwani D. Agrawal Robust testing for stuck-at faults. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF logic circuit testing, d-robust tests, fault diagnosis, logic testing, delays, sequential circuits, sequential circuits, fault models, combinational circuits, combinational circuit, robust testing, single stuck-at faults, circuit models
53Rene David, S. Rahal, J. L. Rainard Some relationships between delay testing and stuck-open testing in CMOS circuits. Search on Bibsonomy EURO-DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF stuck-open, combinational circuits, CMOS, Delay testing, robust test
52Irith Pomeranz, Sudhakar M. Reddy Test sequences to achieve high defect coverage for synchronous sequential circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
52Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò Fault simulation of unconventional faults in CMOS circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
52Michael Nicolaidis Shorts in self-checking circuits. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF strongly fault-secure circuits, transistor faults, error detecting codes, self-checking circuits, totally self-checking circuits
50Manoj Singh Gaur, Raghavendra Narasimhan, Vijay Laxmi, Ujjwal Kumar Structural Fault Modelling in Nano Devices. Search on Bibsonomy NanoNet The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Structural fault, stuck-at-0, stuck-at-1, MRF, bridge, TMR
50Parag K. Lala, Anup Singh, Alvernon Walker A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs. Search on Bibsonomy DFT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF DCVSL, Stuck-ON/OFF, Stuck-at Faults, Self-testing
50Kent L. Einspahr, Sharad C. Seth A switch-level test generation system for synchronous and asynchronous circuits. Search on Bibsonomy J. Electron. Test. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF reverse time processing, stuck-open and stuck-at faults, time-frame expansion, sequential circuits, Automatic test generation
47Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy On Improving Defect Coverage of Stuck-at Fault Tests. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
47Cédric Fournet, C. A. R. Hoare, Sriram K. Rajamani, Jakob Rehof Stuck-Free Conformance. Search on Bibsonomy CAV The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
47Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
47Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell A Complete Characterization of Path Delay Faults through Stuck-at Faults. Search on Bibsonomy VLSI Design The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
46Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001 Simulating Resistive Bridging and Stuck-At Faults. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Resistive stuck-at faults, probabilistic fault coverage, Resistive bridging faults, bridging fault simulation
46Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using IDDQ Testing in BiCMOS and CMOS Circuits. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF input pattern classification, BiCMOS circuits, quiescent power supply current monitoring, enhanced I/sub DDQ/, fault diagnosis, bridging faults, CMOS circuits, I/sub DDQ/ testing, stuck-ON faults
46Alok Agrawal, Alexander Saldanha, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli Compact and complete test set generation for multiple stuck-faults. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Multiple stuck faults, complete test set generation, irrepressible faults
46Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs Dynamic diagnosis of sequential circuits based on stuck-at faults. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF dynamic diagnosis, stuck-at fault simulation, cause-effect analysis, effect-cause analysis, error propagation back-trace, fault diagnosis, logic testing, sequential circuits, synchronous sequential circuit, matching algorithm
46Tapan J. Chakraborty, Vishwani D. Agrawal Design for high-speed testability of stuck-at faults. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF design for high-speed testability, stuck-at fault detection, signal transition, timing hazard, multivalue algebra, dh-robust test, sequential feedback, reconvergent fanout, cycle-free sequential circuit, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, partial scan, test generation algorithm, critical path delay
45Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz Detectability of internal bridging faults in scan chains. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
45Feng Shi 0010, Yiorgos Makris A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines. Search on Bibsonomy ASYNC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45Sunjaya Djaja, Glenn H. Chapman, Desmond Y. H. Cheung, Yves Audet Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS). Search on Bibsonomy DFT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF photodiode APS, fault-tolerance, redundancy, SOC, CMOS image sensor, active pixel sensor
43Wuudiann Ke, Premachandran R. Menon Multifault testability of delay-testable circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF delay-testable circuits, multifault testability, path-delay-fault testability, multiple stuck-at-fault testability, multilevel combinational circuits, robust path-delay-fault test set, logic testing, delays, combinational circuits, multivalued logic circuits
43Andrej Zemva, Franc Brglez Detectable perturbations: a paradigm for technology-specific multi-fault test generation. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF detectable perturbations, technology-specific multi-fault test generation, multiple bridging, open faults, single-output modules, multi-output modules, mutation faults, technology-mapped cells, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, stuck-at faults, cellular arrays, benchmark circuits, generic system
42V. Kim, T. Chen Assessing SRAM test coverage for sub-micron CMOS technologies. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF submicron CMOS technologies, SRAM test coverage assessment, memory fault probability model, memory array, data retention faults, memory fault coverages, memory test algorithms, functional fault class coverages, 0.5 to 1 mum, stuck-at faults, transition faults, stuck-open faults, coupling faults, physical defects, CMOS memory circuits
42Salvador Manich, Michael Nicolaidis, Joan Figueras Enhancing realistic fault secureness in parity prediction array arithmetic operators by IDDQ monitoring. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF mathematical operators, parity prediction array arithmetic operators, IDDQ current monitoring, fault diagnosis, logic testing, fault detection, stuck-at faults, bridging faults, multiplying circuits, multiplier circuit, arithmetic circuits, logic arrays, stuck-open faults, topological design, SPICE simulation, fault secureness
42Samy Makar, Edward J. McCluskey Checking experiments to test latches. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults
41Niraj K. Jha Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF CVS parity trees, strongly self-checking parity, single stuck-at, stuck-open, stuck-on fault detection, cascode voltage switch, differential cascode voltage switch, EX-OR gates, single-ended cascode voltage switch, logic testing, fault location, logic gates, two-rail checkers
40Irith Pomeranz, Sudhakar M. Reddy Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
40Subhamoy Maitra, Goutam Paul 0001 Recovering RC4 Permutation from 2048 Keystream Bytes if jIs Stuck. Search on Bibsonomy ACISP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Cryptanalysis, Stream Cipher, Permutation, Fault Analysis, RC4, Keystream
40Hitoshi Miyanaka, Norihiko Wada, Tetsushi Kamegawa, Noritaka Sato, Shingo Tsukui, Hiroki Igarashi, Fumitoshi Matsuno Development of an unit type robot "KOHGA2" with stuck avoidance ability. Search on Bibsonomy ICRA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
40Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara Efficient path delay test generation based on stuck-at test generation using checker circuitry. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
40Gang Chen 0011, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Hitoshi Kimura, Shigeo Hirose, Keisuke Shimizu Stuck Evasion Control for Active-wheel Passive-joint Snake-like Mobile Robot 'Genbu'. Search on Bibsonomy ICRA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
40Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
40Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, M. Enamul Amyeen Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
40Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
40Baris Arslan, Alex Orailoglu Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
40Meine van der Meulen Model Checking the Design of an Unrestricted, Stuck-at Fault Tolerant, Asynchronous Sequential Circuit Using SMV. Search on Bibsonomy FMCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
40Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu Test Generation for Double Stuck-at Faults. Search on Bibsonomy Asian Test Symposium The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
40Michael J. Bryan, Srinivas Devadas, Kurt Keutzer Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
40Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya CMOS Stuck-open Fault Detection Using Single Test Patterns. Search on Bibsonomy DAC The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
40Sarma Sastry, Melvin A. Breuer Detectability of CMOS stuck-open faults using random and pseudorandom test sequences. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
38Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability. Search on Bibsonomy J. Electron. Test. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF universal tests, stuck-at fault, path-delay fault, synthesis-for-testability, unate function, symmetric boolean function
38Shalini Ghosh, F. Joel Ferguson Estimating detection probability of interconnect opens using stuck-at tests. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF break fault, interconnect open, stuck-at test
38Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF stuck-at fault diagnosis, Fault simulation
38Xiao Sun 0002, Carmie Hull Functional Verification Coverage vs. Physical Stuck-at Fault Coverage. Search on Bibsonomy DFT The full citation details ... 1998 DBLP  DOI  BibTeX  RDF functional property, stuck-at fault coverage, verification coverage, UIO, verification, validation, ATPG, FSM, signature analysis, test application time
38Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF DFT circuit, test generation, pass-transistor logic, stuck-on fault
38Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF waveform analysis, nonrobust tests, stuck-fault detection, signal waveform analysis, signal waveform integration, directed random test generation techniques, fault diagnosis, logic testing, redundancy, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, detectability, fault coverage, test application time, redundant faults
38Karen Panetta Lentz, Elias S. Manolakos, Edward C. Czeck On the simulation of Multiple Stuck-at Faults using Multiple Domain Concurrent and Comparative Simulation. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF multiple stuck-at fault simulation, multiple domain simulation, comparative simulation, MDCCS, discrete event concurrent simulation, CPU time efficiency, digital logic fault simulation, fault diagnosis, logic testing, discrete event simulation, circuit analysis computing, fault location, concurrent engineering
38Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions
37Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israel Koren, Zahava Koren Quantitative Analysis of In-Field Defects in Image Sensor Arrays. Search on Bibsonomy DFT The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
37Michelle L. La Haye, Glenn H. Chapman, Cory Jung, Desmond Y. H. Cheung, Sunjaya Djaja, Benjamin Wang, Gary Liaw, Yves Audet Characteristics of Fault-Tolerant Photodiode and Photogate Active Pixel Sensor (APS). Search on Bibsonomy DFT The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
37Michiko Inoue, Emil Gizdarski, Hideo Fujiwara Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF internally balanced structure, test generation, sequential circuit, combinational circuit, balanced structure
37Chien-Mo James Li, Edward J. McCluskey Diagnosis of Sequence-Dependent Chips. Search on Bibsonomy VTS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
37Kunihito Yamamori, Toru Abe, Susumu Horiguchi Performance Evaluation of a Partial Retraining Scheme for Defective Multi-Layer Neural Networks. Search on Bibsonomy ACSAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
37A. B. M. Harun-ur Rashid, Mazuhidul Karim, Syed Mahfuzul Aziz Testing complementary pass-transistor logic circuits. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
37Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi False-Path Removal Using Delay Fault Simulation. Search on Bibsonomy J. Electron. Test. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF design for testability, fault simulation, Delay testing, path delay faults, synthesis for testability, redundancy removal
37Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou On Testability of Multiple Precharged Domino Logic. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
37Piotr R. Sidorowicz Modeling and Testing Transistor Faults in Content-Addressable Memories. Search on Bibsonomy MTDT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
37Moritoshi Yasunaga, I. Hachiya, K. Moki, Jung Hwan Kim Fault-tolerant self-organizing map implemented by wafer-scale integration. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
37Wen-Ben Jone, Patrick H. Madden Multiple fault testing using minimal single fault test set for fanout-free circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
37Patrick Kam Lui, Jon C. Muzio Constrained parity testing. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF compaction testing, parity testing, Built-in self-test, signature analysis
36Wuudiann Ke, Premachandran R. Menon Multifault and delay-fault testability of multilevel circuits. Search on Bibsonomy J. Electron. Test. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF testing, testability, delay-faults, multiple stuck-at faults
36Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck Deterministic test generation for non-classical faults on the gate level. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
36Sumit Ghosh, Tapan J. Chakraborty On behavior fault modeling for digital designs. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF fault coverage correlation, fault model, fault simulation, stuck-at fault, behavior model
36Michele Favalli, Piero Olivo, Bruno Riccò, Fabio Somenzi Fault simulation for general FCMOS ICs. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF fault simulation, bridging faults, CMOS circuits, stuck-open faults, critical path analysis
34Tobias Drey, Fabian Fischbach, Pascal Jansen, Julian Frommel, Michael Rietzler, Enrico Rukzio To Be or Not to Be Stuck, or Is It a Continuum?: A Systematic Literature Review on the Concept of Being Stuck in Games. Search on Bibsonomy Proc. ACM Hum. Comput. Interact. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
34Malay Kule, Hafizur Rahaman 0001, Bhargab B. Bhattacharya Maximal Defect-Free Component in Nanoscale Crossbar Circuits Amidst Stuck-Open and Stuck-Closed Faults. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
34Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors. Search on Bibsonomy IEICE Trans. Fundam. Electron. Commun. Comput. Sci. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
34Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud Stuck-open fault diagnosis with stuck-at model. Search on Bibsonomy ETS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud A novel stuck-at based method for transistor stuck-open fault diagnosis. Search on Bibsonomy ITC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Yeong-Ruey Shieh, Cheng-Wen Wu Design of CMOS PSCD Circuits and Checkers for Stuck-At and Stuck-On Faults. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
34Irith Pomeranz, Sudhakar M. Reddy Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage. Search on Bibsonomy VTS The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
34Manjit S. Cheema, Parag K. Lala A new technique for totally self-checking CMOS circuit design for stuck-on and stuck-off faults. Search on Bibsonomy VTS The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
34François Darlay Detection of multiple stuck-on/stuck-open faults by single faults test sets in MOS transistor networks. Search on Bibsonomy Microprocessing and Microprogramming The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
34Joseph L. A. Hughes, Edward J. McCluskey Multiple Stuck-At Fault Coverage of Single Stuck-At Fault Test Sets. Search on Bibsonomy ITC The full citation details ... 1986 DBLP  BibTeX  RDF
32Osman Hasan, Naeem Abbasi, Sofiène Tahar Formal Probabilistic Analysis of Stuck-at Faults in Reconfigurable Memory Arrays. Search on Bibsonomy IFM The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
32Jan Schat Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns. Search on Bibsonomy DDECS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
32Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. Search on Bibsonomy DFT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
32Elham K. Moghaddam, Shaahin Hessabi An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits. Search on Bibsonomy DSD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001 Simulating Resistive-Bridging and Stuck-At Faults. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32Ruifeng Guo, Subhasish Mitra, M. Enamul Amyeen, Jinkyu Lee, Srihari Sivaraj, Srikanth Venkataraman Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive. Search on Bibsonomy VTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32Chien-Mo James Li, Edward J. McCluskey Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
32Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
Displaying result #1 - #100 of 1518 (100 per page; Change: )
Pages: [1][2][3][4][5][6][7][8][9][10][>>]
Valid XHTML 1.1! Valid CSS! [Valid RSS]
Maintained by L3S.
Previously maintained by Jörg Diederich.
Based upon DBLP by Michael Ley.
open data data released under the ODC-BY 1.0 license